Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.86 89.86 100.00 100.00 93.75 93.75 100.00 100.00 82.14 82.14 95.83 95.83 67.44 67.44 /workspace/coverage/default/12.prim_async_alert.2259741396
92.99 3.13 100.00 0.00 93.75 0.00 100.00 0.00 89.29 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/12.prim_sync_alert.4261531992
94.50 1.51 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3701169095
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2913495451

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3818674552
/workspace/coverage/default/1.prim_async_alert.1172565460
/workspace/coverage/default/10.prim_async_alert.1930084701
/workspace/coverage/default/11.prim_async_alert.1145690433
/workspace/coverage/default/13.prim_async_alert.1036249154
/workspace/coverage/default/14.prim_async_alert.2264648080
/workspace/coverage/default/15.prim_async_alert.4078542447
/workspace/coverage/default/16.prim_async_alert.2064623406
/workspace/coverage/default/17.prim_async_alert.2800746371
/workspace/coverage/default/18.prim_async_alert.1455374239
/workspace/coverage/default/19.prim_async_alert.2655727365
/workspace/coverage/default/2.prim_async_alert.816265168
/workspace/coverage/default/3.prim_async_alert.2275994238
/workspace/coverage/default/4.prim_async_alert.2848251927
/workspace/coverage/default/5.prim_async_alert.1443478292
/workspace/coverage/default/6.prim_async_alert.2963253576
/workspace/coverage/default/7.prim_async_alert.3418732767
/workspace/coverage/default/8.prim_async_alert.2781759632
/workspace/coverage/default/9.prim_async_alert.2679312432
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3016892283
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.329414873
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2441813186
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.645786617
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1514167850
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2531757162
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.203401364
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2396608291
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1060541245
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2294922129
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3968232757
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.334161477
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.584984529
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.600545296
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3585660623
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4014532158
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1033685532
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4201077981
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2337454491
/workspace/coverage/sync_alert/0.prim_sync_alert.3554797705
/workspace/coverage/sync_alert/1.prim_sync_alert.3897322241
/workspace/coverage/sync_alert/10.prim_sync_alert.1800785778
/workspace/coverage/sync_alert/11.prim_sync_alert.766245807
/workspace/coverage/sync_alert/13.prim_sync_alert.3263509211
/workspace/coverage/sync_alert/14.prim_sync_alert.3802239661
/workspace/coverage/sync_alert/15.prim_sync_alert.404809317
/workspace/coverage/sync_alert/16.prim_sync_alert.4261843174
/workspace/coverage/sync_alert/17.prim_sync_alert.2536769480
/workspace/coverage/sync_alert/18.prim_sync_alert.495850891
/workspace/coverage/sync_alert/19.prim_sync_alert.2141794911
/workspace/coverage/sync_alert/2.prim_sync_alert.2259584927
/workspace/coverage/sync_alert/3.prim_sync_alert.2114956554
/workspace/coverage/sync_alert/4.prim_sync_alert.2659812317
/workspace/coverage/sync_alert/5.prim_sync_alert.1263670398
/workspace/coverage/sync_alert/6.prim_sync_alert.1084706871
/workspace/coverage/sync_alert/7.prim_sync_alert.3686382823
/workspace/coverage/sync_alert/8.prim_sync_alert.230224000
/workspace/coverage/sync_alert/9.prim_sync_alert.136484245
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4121462214
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.840085044
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2729367535
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2863508195
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.361949504
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.810988996
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2538074820
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.937070319
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2731069770
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4244539596
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1022838212
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2936337243
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3982819022
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.531803836
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3434068504
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3680501030
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4026928893
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2546307721
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.62801279



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.prim_async_alert.2275994238 Aug 10 05:19:47 PM PDT 24 Aug 10 05:19:47 PM PDT 24 11875631 ps
T2 /workspace/coverage/default/13.prim_async_alert.1036249154 Aug 10 05:19:41 PM PDT 24 Aug 10 05:19:41 PM PDT 24 11433036 ps
T3 /workspace/coverage/default/12.prim_async_alert.2259741396 Aug 10 05:19:43 PM PDT 24 Aug 10 05:19:43 PM PDT 24 11887134 ps
T9 /workspace/coverage/default/9.prim_async_alert.2679312432 Aug 10 05:19:38 PM PDT 24 Aug 10 05:19:38 PM PDT 24 10665485 ps
T7 /workspace/coverage/default/14.prim_async_alert.2264648080 Aug 10 05:19:41 PM PDT 24 Aug 10 05:19:41 PM PDT 24 11075586 ps
T16 /workspace/coverage/default/11.prim_async_alert.1145690433 Aug 10 05:19:42 PM PDT 24 Aug 10 05:19:43 PM PDT 24 11370187 ps
T10 /workspace/coverage/default/15.prim_async_alert.4078542447 Aug 10 05:19:45 PM PDT 24 Aug 10 05:19:45 PM PDT 24 11047586 ps
T17 /workspace/coverage/default/10.prim_async_alert.1930084701 Aug 10 05:19:43 PM PDT 24 Aug 10 05:19:44 PM PDT 24 10652556 ps
T13 /workspace/coverage/default/1.prim_async_alert.1172565460 Aug 10 05:19:38 PM PDT 24 Aug 10 05:19:39 PM PDT 24 11179627 ps
T18 /workspace/coverage/default/18.prim_async_alert.1455374239 Aug 10 05:19:43 PM PDT 24 Aug 10 05:19:43 PM PDT 24 11168281 ps
T11 /workspace/coverage/default/5.prim_async_alert.1443478292 Aug 10 05:19:38 PM PDT 24 Aug 10 05:19:38 PM PDT 24 10911687 ps
T19 /workspace/coverage/default/4.prim_async_alert.2848251927 Aug 10 05:19:36 PM PDT 24 Aug 10 05:19:37 PM PDT 24 10392573 ps
T8 /workspace/coverage/default/16.prim_async_alert.2064623406 Aug 10 05:19:38 PM PDT 24 Aug 10 05:19:39 PM PDT 24 11042057 ps
T12 /workspace/coverage/default/8.prim_async_alert.2781759632 Aug 10 05:19:39 PM PDT 24 Aug 10 05:19:39 PM PDT 24 11047714 ps
T14 /workspace/coverage/default/6.prim_async_alert.2963253576 Aug 10 05:19:36 PM PDT 24 Aug 10 05:19:37 PM PDT 24 11287367 ps
T44 /workspace/coverage/default/0.prim_async_alert.3818674552 Aug 10 05:19:37 PM PDT 24 Aug 10 05:19:37 PM PDT 24 11091562 ps
T45 /workspace/coverage/default/17.prim_async_alert.2800746371 Aug 10 05:19:39 PM PDT 24 Aug 10 05:19:39 PM PDT 24 11351573 ps
T46 /workspace/coverage/default/7.prim_async_alert.3418732767 Aug 10 05:19:45 PM PDT 24 Aug 10 05:19:46 PM PDT 24 10572579 ps
T47 /workspace/coverage/default/19.prim_async_alert.2655727365 Aug 10 05:19:38 PM PDT 24 Aug 10 05:19:38 PM PDT 24 11064840 ps
T48 /workspace/coverage/default/2.prim_async_alert.816265168 Aug 10 05:19:39 PM PDT 24 Aug 10 05:19:40 PM PDT 24 10855103 ps
T35 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3701169095 Aug 10 05:20:03 PM PDT 24 Aug 10 05:20:04 PM PDT 24 29556886 ps
T36 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2531757162 Aug 10 05:19:44 PM PDT 24 Aug 10 05:19:44 PM PDT 24 30101586 ps
T37 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2396608291 Aug 10 05:19:44 PM PDT 24 Aug 10 05:19:45 PM PDT 24 28190295 ps
T15 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.203401364 Aug 10 05:19:47 PM PDT 24 Aug 10 05:19:48 PM PDT 24 30155421 ps
T38 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2294922129 Aug 10 05:19:44 PM PDT 24 Aug 10 05:19:45 PM PDT 24 31765277 ps
T39 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.645786617 Aug 10 05:19:45 PM PDT 24 Aug 10 05:19:46 PM PDT 24 28998169 ps
T40 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4014532158 Aug 10 05:19:48 PM PDT 24 Aug 10 05:19:49 PM PDT 24 30739386 ps
T41 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3016892283 Aug 10 05:19:44 PM PDT 24 Aug 10 05:19:45 PM PDT 24 28799971 ps
T42 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.329414873 Aug 10 05:19:43 PM PDT 24 Aug 10 05:19:44 PM PDT 24 30056363 ps
T43 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3585660623 Aug 10 05:19:45 PM PDT 24 Aug 10 05:19:45 PM PDT 24 29916899 ps
T49 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2441813186 Aug 10 05:19:58 PM PDT 24 Aug 10 05:19:58 PM PDT 24 29450808 ps
T50 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1060541245 Aug 10 05:19:45 PM PDT 24 Aug 10 05:19:46 PM PDT 24 29123337 ps
T51 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3968232757 Aug 10 05:19:48 PM PDT 24 Aug 10 05:19:48 PM PDT 24 31142446 ps
T52 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.600545296 Aug 10 05:19:38 PM PDT 24 Aug 10 05:19:39 PM PDT 24 29793266 ps
T53 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.334161477 Aug 10 05:19:38 PM PDT 24 Aug 10 05:19:39 PM PDT 24 29809861 ps
T54 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1033685532 Aug 10 05:19:45 PM PDT 24 Aug 10 05:19:45 PM PDT 24 31308132 ps
T55 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1514167850 Aug 10 05:19:47 PM PDT 24 Aug 10 05:19:48 PM PDT 24 29073717 ps
T56 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.584984529 Aug 10 05:19:37 PM PDT 24 Aug 10 05:19:38 PM PDT 24 31581525 ps
T57 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4201077981 Aug 10 05:19:45 PM PDT 24 Aug 10 05:19:46 PM PDT 24 30988114 ps
T58 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2337454491 Aug 10 05:19:44 PM PDT 24 Aug 10 05:19:44 PM PDT 24 30467282 ps
T20 /workspace/coverage/sync_alert/12.prim_sync_alert.4261531992 Aug 10 05:23:34 PM PDT 24 Aug 10 05:23:35 PM PDT 24 9434450 ps
T21 /workspace/coverage/sync_alert/3.prim_sync_alert.2114956554 Aug 10 05:23:25 PM PDT 24 Aug 10 05:23:26 PM PDT 24 9604306 ps
T30 /workspace/coverage/sync_alert/17.prim_sync_alert.2536769480 Aug 10 05:23:33 PM PDT 24 Aug 10 05:23:34 PM PDT 24 8714643 ps
T22 /workspace/coverage/sync_alert/6.prim_sync_alert.1084706871 Aug 10 05:23:12 PM PDT 24 Aug 10 05:23:23 PM PDT 24 8671882 ps
T31 /workspace/coverage/sync_alert/0.prim_sync_alert.3554797705 Aug 10 05:23:19 PM PDT 24 Aug 10 05:23:20 PM PDT 24 9838328 ps
T32 /workspace/coverage/sync_alert/10.prim_sync_alert.1800785778 Aug 10 05:23:10 PM PDT 24 Aug 10 05:23:10 PM PDT 24 9379368 ps
T23 /workspace/coverage/sync_alert/11.prim_sync_alert.766245807 Aug 10 05:23:36 PM PDT 24 Aug 10 05:23:36 PM PDT 24 9449481 ps
T33 /workspace/coverage/sync_alert/7.prim_sync_alert.3686382823 Aug 10 05:23:26 PM PDT 24 Aug 10 05:23:27 PM PDT 24 9047689 ps
T34 /workspace/coverage/sync_alert/16.prim_sync_alert.4261843174 Aug 10 05:23:34 PM PDT 24 Aug 10 05:23:35 PM PDT 24 8793930 ps
T24 /workspace/coverage/sync_alert/1.prim_sync_alert.3897322241 Aug 10 05:23:20 PM PDT 24 Aug 10 05:23:20 PM PDT 24 10020484 ps
T59 /workspace/coverage/sync_alert/5.prim_sync_alert.1263670398 Aug 10 05:23:17 PM PDT 24 Aug 10 05:23:18 PM PDT 24 10053487 ps
T60 /workspace/coverage/sync_alert/14.prim_sync_alert.3802239661 Aug 10 05:23:17 PM PDT 24 Aug 10 05:23:17 PM PDT 24 9228453 ps
T61 /workspace/coverage/sync_alert/13.prim_sync_alert.3263509211 Aug 10 05:23:23 PM PDT 24 Aug 10 05:23:23 PM PDT 24 9024431 ps
T62 /workspace/coverage/sync_alert/4.prim_sync_alert.2659812317 Aug 10 05:23:38 PM PDT 24 Aug 10 05:23:38 PM PDT 24 9749577 ps
T63 /workspace/coverage/sync_alert/9.prim_sync_alert.136484245 Aug 10 05:23:21 PM PDT 24 Aug 10 05:23:21 PM PDT 24 10003874 ps
T25 /workspace/coverage/sync_alert/2.prim_sync_alert.2259584927 Aug 10 05:23:17 PM PDT 24 Aug 10 05:23:17 PM PDT 24 10566706 ps
T64 /workspace/coverage/sync_alert/8.prim_sync_alert.230224000 Aug 10 05:23:21 PM PDT 24 Aug 10 05:23:22 PM PDT 24 9244579 ps
T65 /workspace/coverage/sync_alert/19.prim_sync_alert.2141794911 Aug 10 05:23:39 PM PDT 24 Aug 10 05:23:39 PM PDT 24 9385976 ps
T26 /workspace/coverage/sync_alert/18.prim_sync_alert.495850891 Aug 10 05:23:31 PM PDT 24 Aug 10 05:23:31 PM PDT 24 9319720 ps
T27 /workspace/coverage/sync_alert/15.prim_sync_alert.404809317 Aug 10 05:23:33 PM PDT 24 Aug 10 05:23:33 PM PDT 24 8719298 ps
T66 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2538074820 Aug 10 05:23:34 PM PDT 24 Aug 10 05:23:40 PM PDT 24 27188913 ps
T67 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4121462214 Aug 10 05:23:22 PM PDT 24 Aug 10 05:23:22 PM PDT 24 27758693 ps
T28 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2729367535 Aug 10 05:23:22 PM PDT 24 Aug 10 05:23:28 PM PDT 24 28240156 ps
T29 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2936337243 Aug 10 05:23:29 PM PDT 24 Aug 10 05:23:29 PM PDT 24 27762242 ps
T68 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2863508195 Aug 10 05:23:45 PM PDT 24 Aug 10 05:23:46 PM PDT 24 26513944 ps
T4 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.937070319 Aug 10 05:23:34 PM PDT 24 Aug 10 05:23:34 PM PDT 24 29327888 ps
T69 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2731069770 Aug 10 05:23:14 PM PDT 24 Aug 10 05:23:15 PM PDT 24 26543847 ps
T70 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4244539596 Aug 10 05:23:32 PM PDT 24 Aug 10 05:23:33 PM PDT 24 27545870 ps
T5 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2913495451 Aug 10 05:23:35 PM PDT 24 Aug 10 05:23:36 PM PDT 24 26924084 ps
T71 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3434068504 Aug 10 05:23:25 PM PDT 24 Aug 10 05:23:25 PM PDT 24 29214402 ps
T72 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1022838212 Aug 10 05:25:00 PM PDT 24 Aug 10 05:25:01 PM PDT 24 27323948 ps
T73 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.62801279 Aug 10 05:23:28 PM PDT 24 Aug 10 05:23:29 PM PDT 24 30031783 ps
T6 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3680501030 Aug 10 05:23:34 PM PDT 24 Aug 10 05:23:35 PM PDT 24 28278549 ps
T74 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.531803836 Aug 10 05:23:32 PM PDT 24 Aug 10 05:23:33 PM PDT 24 28623931 ps
T75 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.810988996 Aug 10 05:23:28 PM PDT 24 Aug 10 05:23:28 PM PDT 24 28490571 ps
T76 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.361949504 Aug 10 05:23:35 PM PDT 24 Aug 10 05:23:35 PM PDT 24 28210648 ps
T77 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2546307721 Aug 10 05:23:28 PM PDT 24 Aug 10 05:23:34 PM PDT 24 27772430 ps
T78 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3982819022 Aug 10 05:23:31 PM PDT 24 Aug 10 05:23:32 PM PDT 24 28390453 ps
T79 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4026928893 Aug 10 05:23:35 PM PDT 24 Aug 10 05:23:35 PM PDT 24 28403546 ps
T80 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.840085044 Aug 10 05:23:18 PM PDT 24 Aug 10 05:23:19 PM PDT 24 28016223 ps

Test location /workspace/coverage/default/12.prim_async_alert.2259741396
Short name T3
Test name
Test status
Simulation time 11887134 ps
CPU time 0.39 seconds
Started Aug 10 05:19:43 PM PDT 24
Finished Aug 10 05:19:43 PM PDT 24
Peak memory 145796 kb
Host smart-63891273-d6ca-4044-906c-81425239d8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259741396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2259741396
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.4261531992
Short name T20
Test name
Test status
Simulation time 9434450 ps
CPU time 0.36 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 145512 kb
Host smart-09d3fcc5-7f52-4c08-8efa-fe2a18097d3f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4261531992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4261531992
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3701169095
Short name T35
Test name
Test status
Simulation time 29556886 ps
CPU time 0.4 seconds
Started Aug 10 05:20:03 PM PDT 24
Finished Aug 10 05:20:04 PM PDT 24
Peak memory 145352 kb
Host smart-a008a17a-c8f7-4f20-a272-b0a93aeb825f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3701169095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3701169095
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2913495451
Short name T5
Test name
Test status
Simulation time 26924084 ps
CPU time 0.39 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 145628 kb
Host smart-c75576e1-e4b7-4e35-92b9-fdf86fa203c9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2913495451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2913495451
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3818674552
Short name T44
Test name
Test status
Simulation time 11091562 ps
CPU time 0.43 seconds
Started Aug 10 05:19:37 PM PDT 24
Finished Aug 10 05:19:37 PM PDT 24
Peak memory 145744 kb
Host smart-ce423a09-450c-42cf-887e-1c95774c90a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818674552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3818674552
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1172565460
Short name T13
Test name
Test status
Simulation time 11179627 ps
CPU time 0.41 seconds
Started Aug 10 05:19:38 PM PDT 24
Finished Aug 10 05:19:39 PM PDT 24
Peak memory 145760 kb
Host smart-039fca91-6fbc-424d-aa37-0694c8624ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172565460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1172565460
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1930084701
Short name T17
Test name
Test status
Simulation time 10652556 ps
CPU time 0.42 seconds
Started Aug 10 05:19:43 PM PDT 24
Finished Aug 10 05:19:44 PM PDT 24
Peak memory 145784 kb
Host smart-e0b1c7a5-ffe3-4dfe-80cd-61565b01f962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930084701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1930084701
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1145690433
Short name T16
Test name
Test status
Simulation time 11370187 ps
CPU time 0.4 seconds
Started Aug 10 05:19:42 PM PDT 24
Finished Aug 10 05:19:43 PM PDT 24
Peak memory 145708 kb
Host smart-22b892d6-1bb5-40b0-9a85-378f0148269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145690433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1145690433
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1036249154
Short name T2
Test name
Test status
Simulation time 11433036 ps
CPU time 0.39 seconds
Started Aug 10 05:19:41 PM PDT 24
Finished Aug 10 05:19:41 PM PDT 24
Peak memory 145816 kb
Host smart-0f86437f-e7a3-49e5-a59d-5fe5b6d7b108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036249154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1036249154
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2264648080
Short name T7
Test name
Test status
Simulation time 11075586 ps
CPU time 0.4 seconds
Started Aug 10 05:19:41 PM PDT 24
Finished Aug 10 05:19:41 PM PDT 24
Peak memory 145824 kb
Host smart-80838345-a299-4bbc-af66-c9b66c5530d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264648080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2264648080
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.4078542447
Short name T10
Test name
Test status
Simulation time 11047586 ps
CPU time 0.4 seconds
Started Aug 10 05:19:45 PM PDT 24
Finished Aug 10 05:19:45 PM PDT 24
Peak memory 145852 kb
Host smart-c64d8a18-dd1e-45f0-ae5f-7262ec1170bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078542447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.4078542447
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2064623406
Short name T8
Test name
Test status
Simulation time 11042057 ps
CPU time 0.39 seconds
Started Aug 10 05:19:38 PM PDT 24
Finished Aug 10 05:19:39 PM PDT 24
Peak memory 145660 kb
Host smart-8f4086fd-03b6-45d9-96ac-f5b9c0061dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064623406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2064623406
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2800746371
Short name T45
Test name
Test status
Simulation time 11351573 ps
CPU time 0.38 seconds
Started Aug 10 05:19:39 PM PDT 24
Finished Aug 10 05:19:39 PM PDT 24
Peak memory 145780 kb
Host smart-a638ebdf-6c31-46f2-8a5c-b8e589e05da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800746371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2800746371
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1455374239
Short name T18
Test name
Test status
Simulation time 11168281 ps
CPU time 0.39 seconds
Started Aug 10 05:19:43 PM PDT 24
Finished Aug 10 05:19:43 PM PDT 24
Peak memory 145692 kb
Host smart-e345962a-d7b3-49a2-ba7a-4e7fa2f87d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455374239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1455374239
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.2655727365
Short name T47
Test name
Test status
Simulation time 11064840 ps
CPU time 0.4 seconds
Started Aug 10 05:19:38 PM PDT 24
Finished Aug 10 05:19:38 PM PDT 24
Peak memory 145820 kb
Host smart-0213931e-581d-4ec5-b692-12e8367b876b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655727365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2655727365
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.816265168
Short name T48
Test name
Test status
Simulation time 10855103 ps
CPU time 0.4 seconds
Started Aug 10 05:19:39 PM PDT 24
Finished Aug 10 05:19:40 PM PDT 24
Peak memory 145684 kb
Host smart-b0708e02-566a-4517-b9e2-f78208b52030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816265168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.816265168
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2275994238
Short name T1
Test name
Test status
Simulation time 11875631 ps
CPU time 0.38 seconds
Started Aug 10 05:19:47 PM PDT 24
Finished Aug 10 05:19:47 PM PDT 24
Peak memory 145672 kb
Host smart-c2024c0b-5e20-4d57-b71d-08e3f6b56871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275994238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2275994238
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2848251927
Short name T19
Test name
Test status
Simulation time 10392573 ps
CPU time 0.38 seconds
Started Aug 10 05:19:36 PM PDT 24
Finished Aug 10 05:19:37 PM PDT 24
Peak memory 145712 kb
Host smart-c046abec-bd05-484a-b7c7-26da21b9ee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848251927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2848251927
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1443478292
Short name T11
Test name
Test status
Simulation time 10911687 ps
CPU time 0.45 seconds
Started Aug 10 05:19:38 PM PDT 24
Finished Aug 10 05:19:38 PM PDT 24
Peak memory 145640 kb
Host smart-87f21ea1-28f4-48b1-8a2d-d24095f0a33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443478292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1443478292
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2963253576
Short name T14
Test name
Test status
Simulation time 11287367 ps
CPU time 0.41 seconds
Started Aug 10 05:19:36 PM PDT 24
Finished Aug 10 05:19:37 PM PDT 24
Peak memory 145796 kb
Host smart-530ee82f-33aa-41f7-96ae-7847c336667f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963253576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2963253576
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3418732767
Short name T46
Test name
Test status
Simulation time 10572579 ps
CPU time 0.39 seconds
Started Aug 10 05:19:45 PM PDT 24
Finished Aug 10 05:19:46 PM PDT 24
Peak memory 145804 kb
Host smart-c9f1a222-cc08-4c65-bdd0-4af65277578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418732767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3418732767
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2781759632
Short name T12
Test name
Test status
Simulation time 11047714 ps
CPU time 0.39 seconds
Started Aug 10 05:19:39 PM PDT 24
Finished Aug 10 05:19:39 PM PDT 24
Peak memory 145796 kb
Host smart-47485547-247f-4371-b661-c3caf20d4af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781759632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2781759632
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2679312432
Short name T9
Test name
Test status
Simulation time 10665485 ps
CPU time 0.39 seconds
Started Aug 10 05:19:38 PM PDT 24
Finished Aug 10 05:19:38 PM PDT 24
Peak memory 145680 kb
Host smart-0d00c0fb-9315-4020-86de-5d4d0b506e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679312432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2679312432
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3016892283
Short name T41
Test name
Test status
Simulation time 28799971 ps
CPU time 0.41 seconds
Started Aug 10 05:19:44 PM PDT 24
Finished Aug 10 05:19:45 PM PDT 24
Peak memory 145312 kb
Host smart-b0c5cb67-04e9-4585-a2d3-03060aba7c53
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3016892283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3016892283
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.329414873
Short name T42
Test name
Test status
Simulation time 30056363 ps
CPU time 0.39 seconds
Started Aug 10 05:19:43 PM PDT 24
Finished Aug 10 05:19:44 PM PDT 24
Peak memory 145276 kb
Host smart-36b8db22-7513-447b-a513-db81588d81ba
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=329414873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.329414873
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2441813186
Short name T49
Test name
Test status
Simulation time 29450808 ps
CPU time 0.4 seconds
Started Aug 10 05:19:58 PM PDT 24
Finished Aug 10 05:19:58 PM PDT 24
Peak memory 145256 kb
Host smart-0a1c8d58-6d29-437d-8da8-67df27e0edcb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2441813186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2441813186
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.645786617
Short name T39
Test name
Test status
Simulation time 28998169 ps
CPU time 0.4 seconds
Started Aug 10 05:19:45 PM PDT 24
Finished Aug 10 05:19:46 PM PDT 24
Peak memory 145264 kb
Host smart-d5627a19-f00f-4779-856e-0bc8b7437f1a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=645786617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.645786617
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1514167850
Short name T55
Test name
Test status
Simulation time 29073717 ps
CPU time 0.42 seconds
Started Aug 10 05:19:47 PM PDT 24
Finished Aug 10 05:19:48 PM PDT 24
Peak memory 145188 kb
Host smart-c64d696e-be29-4b66-b5ed-2258d4de8cae
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1514167850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1514167850
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2531757162
Short name T36
Test name
Test status
Simulation time 30101586 ps
CPU time 0.41 seconds
Started Aug 10 05:19:44 PM PDT 24
Finished Aug 10 05:19:44 PM PDT 24
Peak memory 145260 kb
Host smart-7b3fb92f-eb08-41f6-adfc-4bd2df871fa0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2531757162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2531757162
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.203401364
Short name T15
Test name
Test status
Simulation time 30155421 ps
CPU time 0.42 seconds
Started Aug 10 05:19:47 PM PDT 24
Finished Aug 10 05:19:48 PM PDT 24
Peak memory 145144 kb
Host smart-82666d67-e0fc-4c0a-ba1c-2b924833487b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=203401364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.203401364
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2396608291
Short name T37
Test name
Test status
Simulation time 28190295 ps
CPU time 0.41 seconds
Started Aug 10 05:19:44 PM PDT 24
Finished Aug 10 05:19:45 PM PDT 24
Peak memory 145296 kb
Host smart-e270bd2d-6765-4930-8e85-38d74c63ba09
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2396608291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2396608291
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1060541245
Short name T50
Test name
Test status
Simulation time 29123337 ps
CPU time 0.46 seconds
Started Aug 10 05:19:45 PM PDT 24
Finished Aug 10 05:19:46 PM PDT 24
Peak memory 145316 kb
Host smart-57d88083-d1f5-4746-b9d9-fdb818743d0e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1060541245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1060541245
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2294922129
Short name T38
Test name
Test status
Simulation time 31765277 ps
CPU time 0.4 seconds
Started Aug 10 05:19:44 PM PDT 24
Finished Aug 10 05:19:45 PM PDT 24
Peak memory 145252 kb
Host smart-d55abac0-5285-42ff-9c96-bf8abb478da6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2294922129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2294922129
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3968232757
Short name T51
Test name
Test status
Simulation time 31142446 ps
CPU time 0.41 seconds
Started Aug 10 05:19:48 PM PDT 24
Finished Aug 10 05:19:48 PM PDT 24
Peak memory 145288 kb
Host smart-9ef2e6a8-dc9b-4dfe-a75c-308455d8533d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3968232757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3968232757
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.334161477
Short name T53
Test name
Test status
Simulation time 29809861 ps
CPU time 0.41 seconds
Started Aug 10 05:19:38 PM PDT 24
Finished Aug 10 05:19:39 PM PDT 24
Peak memory 145192 kb
Host smart-6e43e6a6-8730-478c-b56f-f6a73fe29e0a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=334161477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.334161477
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.584984529
Short name T56
Test name
Test status
Simulation time 31581525 ps
CPU time 0.45 seconds
Started Aug 10 05:19:37 PM PDT 24
Finished Aug 10 05:19:38 PM PDT 24
Peak memory 145292 kb
Host smart-c4e81587-8798-4267-9239-e6530cd4f4ff
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=584984529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.584984529
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.600545296
Short name T52
Test name
Test status
Simulation time 29793266 ps
CPU time 0.41 seconds
Started Aug 10 05:19:38 PM PDT 24
Finished Aug 10 05:19:39 PM PDT 24
Peak memory 145312 kb
Host smart-15e64daa-e1cc-4bb4-839d-907fdee05a38
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=600545296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.600545296
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3585660623
Short name T43
Test name
Test status
Simulation time 29916899 ps
CPU time 0.41 seconds
Started Aug 10 05:19:45 PM PDT 24
Finished Aug 10 05:19:45 PM PDT 24
Peak memory 145376 kb
Host smart-16c83fc5-75f9-4bbe-a225-6c270aab752c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3585660623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3585660623
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.4014532158
Short name T40
Test name
Test status
Simulation time 30739386 ps
CPU time 0.43 seconds
Started Aug 10 05:19:48 PM PDT 24
Finished Aug 10 05:19:49 PM PDT 24
Peak memory 145268 kb
Host smart-1951d9b5-040c-4b96-bb97-76358fb3699a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4014532158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.4014532158
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1033685532
Short name T54
Test name
Test status
Simulation time 31308132 ps
CPU time 0.41 seconds
Started Aug 10 05:19:45 PM PDT 24
Finished Aug 10 05:19:45 PM PDT 24
Peak memory 145224 kb
Host smart-16f400e2-eda6-4405-b03b-f67b6959ec4c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1033685532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1033685532
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4201077981
Short name T57
Test name
Test status
Simulation time 30988114 ps
CPU time 0.42 seconds
Started Aug 10 05:19:45 PM PDT 24
Finished Aug 10 05:19:46 PM PDT 24
Peak memory 145192 kb
Host smart-d9ba9273-c30a-4093-9965-cb73080e56b0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4201077981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.4201077981
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2337454491
Short name T58
Test name
Test status
Simulation time 30467282 ps
CPU time 0.41 seconds
Started Aug 10 05:19:44 PM PDT 24
Finished Aug 10 05:19:44 PM PDT 24
Peak memory 145292 kb
Host smart-a26f306b-424a-4b9a-a44e-29b5939afbfc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2337454491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2337454491
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3554797705
Short name T31
Test name
Test status
Simulation time 9838328 ps
CPU time 0.39 seconds
Started Aug 10 05:23:19 PM PDT 24
Finished Aug 10 05:23:20 PM PDT 24
Peak memory 145508 kb
Host smart-9e9dd77f-c4b2-4851-a83a-fe6a1b292785
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3554797705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3554797705
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3897322241
Short name T24
Test name
Test status
Simulation time 10020484 ps
CPU time 0.38 seconds
Started Aug 10 05:23:20 PM PDT 24
Finished Aug 10 05:23:20 PM PDT 24
Peak memory 145524 kb
Host smart-8d3b3392-41b8-46ad-b4da-d52f36ea06b0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3897322241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3897322241
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1800785778
Short name T32
Test name
Test status
Simulation time 9379368 ps
CPU time 0.38 seconds
Started Aug 10 05:23:10 PM PDT 24
Finished Aug 10 05:23:10 PM PDT 24
Peak memory 145472 kb
Host smart-7e941964-3ffb-4e55-b73b-50864eee971e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1800785778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1800785778
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.766245807
Short name T23
Test name
Test status
Simulation time 9449481 ps
CPU time 0.39 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 145580 kb
Host smart-6cde374f-ff66-44cf-9469-7fb821a4863a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=766245807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.766245807
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3263509211
Short name T61
Test name
Test status
Simulation time 9024431 ps
CPU time 0.38 seconds
Started Aug 10 05:23:23 PM PDT 24
Finished Aug 10 05:23:23 PM PDT 24
Peak memory 145512 kb
Host smart-d6bcaf6a-4578-41de-a733-d12f96bb908c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3263509211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3263509211
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3802239661
Short name T60
Test name
Test status
Simulation time 9228453 ps
CPU time 0.39 seconds
Started Aug 10 05:23:17 PM PDT 24
Finished Aug 10 05:23:17 PM PDT 24
Peak memory 145660 kb
Host smart-be570c7a-7664-4f65-a905-e323429fc7cc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3802239661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3802239661
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.404809317
Short name T27
Test name
Test status
Simulation time 8719298 ps
CPU time 0.39 seconds
Started Aug 10 05:23:33 PM PDT 24
Finished Aug 10 05:23:33 PM PDT 24
Peak memory 145412 kb
Host smart-26bf046a-fcd9-4cc3-923c-baefddba6268
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=404809317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.404809317
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.4261843174
Short name T34
Test name
Test status
Simulation time 8793930 ps
CPU time 0.38 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 145608 kb
Host smart-bd2182e2-9899-45f3-aff8-2d7d32e286b3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4261843174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4261843174
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2536769480
Short name T30
Test name
Test status
Simulation time 8714643 ps
CPU time 0.38 seconds
Started Aug 10 05:23:33 PM PDT 24
Finished Aug 10 05:23:34 PM PDT 24
Peak memory 145452 kb
Host smart-d5d6f782-d639-47fd-aeff-ed0db74b54a8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2536769480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2536769480
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.495850891
Short name T26
Test name
Test status
Simulation time 9319720 ps
CPU time 0.4 seconds
Started Aug 10 05:23:31 PM PDT 24
Finished Aug 10 05:23:31 PM PDT 24
Peak memory 145448 kb
Host smart-44d7c353-9436-40c5-b640-a6676485a146
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=495850891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.495850891
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2141794911
Short name T65
Test name
Test status
Simulation time 9385976 ps
CPU time 0.38 seconds
Started Aug 10 05:23:39 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 145508 kb
Host smart-74355dda-7f9d-461f-9811-d85074aa0fd0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2141794911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2141794911
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2259584927
Short name T25
Test name
Test status
Simulation time 10566706 ps
CPU time 0.39 seconds
Started Aug 10 05:23:17 PM PDT 24
Finished Aug 10 05:23:17 PM PDT 24
Peak memory 144308 kb
Host smart-dbafff13-eacc-4455-b9d3-61e64f98891f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2259584927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2259584927
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2114956554
Short name T21
Test name
Test status
Simulation time 9604306 ps
CPU time 0.38 seconds
Started Aug 10 05:23:25 PM PDT 24
Finished Aug 10 05:23:26 PM PDT 24
Peak memory 145524 kb
Host smart-9f994df3-283f-4691-9e2e-d9666c54d4cd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2114956554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2114956554
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2659812317
Short name T62
Test name
Test status
Simulation time 9749577 ps
CPU time 0.4 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 145480 kb
Host smart-07a7dc8f-27f8-46ac-b4ce-141501e4f704
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2659812317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2659812317
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1263670398
Short name T59
Test name
Test status
Simulation time 10053487 ps
CPU time 0.38 seconds
Started Aug 10 05:23:17 PM PDT 24
Finished Aug 10 05:23:18 PM PDT 24
Peak memory 145596 kb
Host smart-d06a92cc-79e8-4d4e-a68b-3e4cd8a43bee
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1263670398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1263670398
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1084706871
Short name T22
Test name
Test status
Simulation time 8671882 ps
CPU time 0.38 seconds
Started Aug 10 05:23:12 PM PDT 24
Finished Aug 10 05:23:23 PM PDT 24
Peak memory 145524 kb
Host smart-d7c44734-b7c0-4b16-adab-489c284e479f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1084706871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1084706871
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3686382823
Short name T33
Test name
Test status
Simulation time 9047689 ps
CPU time 0.37 seconds
Started Aug 10 05:23:26 PM PDT 24
Finished Aug 10 05:23:27 PM PDT 24
Peak memory 145488 kb
Host smart-5359826a-ad75-41d7-a6c2-271392ca0b27
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3686382823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3686382823
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.230224000
Short name T64
Test name
Test status
Simulation time 9244579 ps
CPU time 0.38 seconds
Started Aug 10 05:23:21 PM PDT 24
Finished Aug 10 05:23:22 PM PDT 24
Peak memory 145596 kb
Host smart-7abd2276-5f57-4324-b674-6c327ae82d81
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=230224000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.230224000
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.136484245
Short name T63
Test name
Test status
Simulation time 10003874 ps
CPU time 0.39 seconds
Started Aug 10 05:23:21 PM PDT 24
Finished Aug 10 05:23:21 PM PDT 24
Peak memory 145520 kb
Host smart-edff797c-b15c-4c24-9814-6c3c49793525
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=136484245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.136484245
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4121462214
Short name T67
Test name
Test status
Simulation time 27758693 ps
CPU time 0.42 seconds
Started Aug 10 05:23:22 PM PDT 24
Finished Aug 10 05:23:22 PM PDT 24
Peak memory 145624 kb
Host smart-d06e01ff-3b50-48d3-858d-62fea2e56d75
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4121462214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4121462214
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.840085044
Short name T80
Test name
Test status
Simulation time 28016223 ps
CPU time 0.39 seconds
Started Aug 10 05:23:18 PM PDT 24
Finished Aug 10 05:23:19 PM PDT 24
Peak memory 145592 kb
Host smart-accdf907-78cb-4e07-933f-93fb2204f099
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=840085044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.840085044
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2729367535
Short name T28
Test name
Test status
Simulation time 28240156 ps
CPU time 0.4 seconds
Started Aug 10 05:23:22 PM PDT 24
Finished Aug 10 05:23:28 PM PDT 24
Peak memory 145592 kb
Host smart-56ec37f2-1d26-4c63-8fdf-72694d48fc8b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2729367535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2729367535
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2863508195
Short name T68
Test name
Test status
Simulation time 26513944 ps
CPU time 0.4 seconds
Started Aug 10 05:23:45 PM PDT 24
Finished Aug 10 05:23:46 PM PDT 24
Peak memory 145596 kb
Host smart-16f83510-017b-422d-abe3-d2570da8d275
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2863508195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2863508195
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.361949504
Short name T76
Test name
Test status
Simulation time 28210648 ps
CPU time 0.4 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 145532 kb
Host smart-cccdb74f-1e19-4645-8c49-a9bd9e91363b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=361949504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.361949504
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.810988996
Short name T75
Test name
Test status
Simulation time 28490571 ps
CPU time 0.39 seconds
Started Aug 10 05:23:28 PM PDT 24
Finished Aug 10 05:23:28 PM PDT 24
Peak memory 144332 kb
Host smart-d4992643-993a-4f51-80bb-aafa7aeb4242
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=810988996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.810988996
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2538074820
Short name T66
Test name
Test status
Simulation time 27188913 ps
CPU time 0.4 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:40 PM PDT 24
Peak memory 145624 kb
Host smart-686ae412-f1cd-457a-ac47-2fae21416b3a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2538074820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2538074820
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.937070319
Short name T4
Test name
Test status
Simulation time 29327888 ps
CPU time 0.4 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:34 PM PDT 24
Peak memory 145532 kb
Host smart-46faff96-a749-4f12-bc2f-ab202cb4c3b5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=937070319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.937070319
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2731069770
Short name T69
Test name
Test status
Simulation time 26543847 ps
CPU time 0.4 seconds
Started Aug 10 05:23:14 PM PDT 24
Finished Aug 10 05:23:15 PM PDT 24
Peak memory 145544 kb
Host smart-035b8311-a948-440e-a22c-eb6e08b859a7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2731069770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2731069770
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4244539596
Short name T70
Test name
Test status
Simulation time 27545870 ps
CPU time 0.41 seconds
Started Aug 10 05:23:32 PM PDT 24
Finished Aug 10 05:23:33 PM PDT 24
Peak memory 145608 kb
Host smart-d8dfe59f-5421-41e9-92be-3ce0b05c735d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4244539596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.4244539596
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1022838212
Short name T72
Test name
Test status
Simulation time 27323948 ps
CPU time 0.39 seconds
Started Aug 10 05:25:00 PM PDT 24
Finished Aug 10 05:25:01 PM PDT 24
Peak memory 145452 kb
Host smart-9dec36df-5218-4862-8930-195d218f51c6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1022838212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1022838212
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2936337243
Short name T29
Test name
Test status
Simulation time 27762242 ps
CPU time 0.42 seconds
Started Aug 10 05:23:29 PM PDT 24
Finished Aug 10 05:23:29 PM PDT 24
Peak memory 145460 kb
Host smart-20e04097-72fa-45f4-94c7-50c7af30852a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2936337243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2936337243
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3982819022
Short name T78
Test name
Test status
Simulation time 28390453 ps
CPU time 0.4 seconds
Started Aug 10 05:23:31 PM PDT 24
Finished Aug 10 05:23:32 PM PDT 24
Peak memory 145628 kb
Host smart-cd3acc6c-d63d-421a-9a88-3848471b3de4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3982819022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3982819022
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.531803836
Short name T74
Test name
Test status
Simulation time 28623931 ps
CPU time 0.42 seconds
Started Aug 10 05:23:32 PM PDT 24
Finished Aug 10 05:23:33 PM PDT 24
Peak memory 145544 kb
Host smart-04c38ca5-a586-4e13-82d2-7c5f967ff714
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=531803836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.531803836
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3434068504
Short name T71
Test name
Test status
Simulation time 29214402 ps
CPU time 0.39 seconds
Started Aug 10 05:23:25 PM PDT 24
Finished Aug 10 05:23:25 PM PDT 24
Peak memory 145460 kb
Host smart-98fb21f5-dfa4-41cf-b915-dbf94ac704db
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3434068504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3434068504
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3680501030
Short name T6
Test name
Test status
Simulation time 28278549 ps
CPU time 0.4 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 145432 kb
Host smart-f577a00a-fd78-4605-be6b-5f357c9a77c2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3680501030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3680501030
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4026928893
Short name T79
Test name
Test status
Simulation time 28403546 ps
CPU time 0.4 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 145432 kb
Host smart-6ffde448-51a3-4e7d-bd90-0574447d1a8d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4026928893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4026928893
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2546307721
Short name T77
Test name
Test status
Simulation time 27772430 ps
CPU time 0.41 seconds
Started Aug 10 05:23:28 PM PDT 24
Finished Aug 10 05:23:34 PM PDT 24
Peak memory 145624 kb
Host smart-5c40fd19-f2d3-48f0-b16a-916b533e529d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2546307721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2546307721
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.62801279
Short name T73
Test name
Test status
Simulation time 30031783 ps
CPU time 0.41 seconds
Started Aug 10 05:23:28 PM PDT 24
Finished Aug 10 05:23:29 PM PDT 24
Peak memory 145624 kb
Host smart-fbd4d7ec-cdbf-4923-bd4a-81efd01aa437
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=62801279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.62801279
Directory /workspace/9.prim_sync_fatal_alert/latest
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