| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.53 | 88.53 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/13.prim_async_alert.2299749417 |
| 91.66 | 3.13 | 100.00 | 0.00 | 91.67 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/4.prim_sync_alert.754096006 |
| 94.15 | 2.49 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 9.30 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3275572917 |
| 94.50 | 0.35 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/1.prim_async_alert.2500985761 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/17.prim_sync_alert.747894071 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2653280126 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.3691044086 |
| /workspace/coverage/default/10.prim_async_alert.1650056905 |
| /workspace/coverage/default/11.prim_async_alert.667469342 |
| /workspace/coverage/default/12.prim_async_alert.1761617392 |
| /workspace/coverage/default/14.prim_async_alert.3793783308 |
| /workspace/coverage/default/15.prim_async_alert.798229754 |
| /workspace/coverage/default/16.prim_async_alert.528793600 |
| /workspace/coverage/default/17.prim_async_alert.658630921 |
| /workspace/coverage/default/18.prim_async_alert.1005478175 |
| /workspace/coverage/default/19.prim_async_alert.4141144629 |
| /workspace/coverage/default/2.prim_async_alert.1066037314 |
| /workspace/coverage/default/3.prim_async_alert.2828806001 |
| /workspace/coverage/default/4.prim_async_alert.4160655316 |
| /workspace/coverage/default/5.prim_async_alert.1746913378 |
| /workspace/coverage/default/6.prim_async_alert.154564005 |
| /workspace/coverage/default/7.prim_async_alert.3721002285 |
| /workspace/coverage/default/8.prim_async_alert.2671373273 |
| /workspace/coverage/default/9.prim_async_alert.1859629433 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.657070514 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3185455285 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1450378321 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1757739838 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2077713315 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2105911137 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3718661006 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.357345206 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2291933690 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1615820372 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2761859654 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1232159256 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3498498107 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4043229678 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1972938600 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3600354472 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2375688501 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2504323760 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.4093436005 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.3867843754 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.2418336375 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.383025098 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2521554280 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.1024987464 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.2413313841 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.1966819586 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.700103359 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.3132026675 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.3966749547 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.1963560384 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3485552488 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.1004023255 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.1855247344 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.4015532489 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.2931497716 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1640856649 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2239294990 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.872584816 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.448318497 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.278877481 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2246631448 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2089153155 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2328042704 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3464804736 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1220372206 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3114127835 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1329285764 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1903712743 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2621392452 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3210079594 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.753591832 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1837299605 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.877683082 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.668927774 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2356082399 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_async_alert.1746913378 | Aug 11 04:41:29 PM PDT 24 | Aug 11 04:41:29 PM PDT 24 | 11048517 ps | ||
| T2 | /workspace/coverage/default/14.prim_async_alert.3793783308 | Aug 11 04:41:30 PM PDT 24 | Aug 11 04:41:31 PM PDT 24 | 11058339 ps | ||
| T3 | /workspace/coverage/default/6.prim_async_alert.154564005 | Aug 11 04:41:53 PM PDT 24 | Aug 11 04:41:53 PM PDT 24 | 11276897 ps | ||
| T7 | /workspace/coverage/default/10.prim_async_alert.1650056905 | Aug 11 04:41:30 PM PDT 24 | Aug 11 04:41:31 PM PDT 24 | 11132369 ps | ||
| T6 | /workspace/coverage/default/1.prim_async_alert.2500985761 | Aug 11 04:41:31 PM PDT 24 | Aug 11 04:41:31 PM PDT 24 | 11391477 ps | ||
| T10 | /workspace/coverage/default/8.prim_async_alert.2671373273 | Aug 11 04:41:31 PM PDT 24 | Aug 11 04:41:31 PM PDT 24 | 11551549 ps | ||
| T16 | /workspace/coverage/default/19.prim_async_alert.4141144629 | Aug 11 04:41:29 PM PDT 24 | Aug 11 04:41:30 PM PDT 24 | 10988120 ps | ||
| T11 | /workspace/coverage/default/9.prim_async_alert.1859629433 | Aug 11 04:41:37 PM PDT 24 | Aug 11 04:41:37 PM PDT 24 | 11587214 ps | ||
| T12 | /workspace/coverage/default/13.prim_async_alert.2299749417 | Aug 11 04:41:24 PM PDT 24 | Aug 11 04:41:24 PM PDT 24 | 11790009 ps | ||
| T19 | /workspace/coverage/default/12.prim_async_alert.1761617392 | Aug 11 04:41:44 PM PDT 24 | Aug 11 04:41:44 PM PDT 24 | 10965993 ps | ||
| T20 | /workspace/coverage/default/11.prim_async_alert.667469342 | Aug 11 04:41:24 PM PDT 24 | Aug 11 04:41:24 PM PDT 24 | 10844088 ps | ||
| T21 | /workspace/coverage/default/17.prim_async_alert.658630921 | Aug 11 04:41:28 PM PDT 24 | Aug 11 04:41:29 PM PDT 24 | 11860636 ps | ||
| T45 | /workspace/coverage/default/2.prim_async_alert.1066037314 | Aug 11 04:41:25 PM PDT 24 | Aug 11 04:41:25 PM PDT 24 | 10722312 ps | ||
| T17 | /workspace/coverage/default/15.prim_async_alert.798229754 | Aug 11 04:41:29 PM PDT 24 | Aug 11 04:41:29 PM PDT 24 | 11644742 ps | ||
| T15 | /workspace/coverage/default/18.prim_async_alert.1005478175 | Aug 11 04:41:36 PM PDT 24 | Aug 11 04:41:37 PM PDT 24 | 10991701 ps | ||
| T46 | /workspace/coverage/default/0.prim_async_alert.3691044086 | Aug 11 04:41:31 PM PDT 24 | Aug 11 04:41:32 PM PDT 24 | 12117781 ps | ||
| T18 | /workspace/coverage/default/7.prim_async_alert.3721002285 | Aug 11 04:41:32 PM PDT 24 | Aug 11 04:41:32 PM PDT 24 | 10920003 ps | ||
| T47 | /workspace/coverage/default/3.prim_async_alert.2828806001 | Aug 11 04:41:32 PM PDT 24 | Aug 11 04:41:32 PM PDT 24 | 10888359 ps | ||
| T48 | /workspace/coverage/default/4.prim_async_alert.4160655316 | Aug 11 04:41:35 PM PDT 24 | Aug 11 04:41:36 PM PDT 24 | 11761255 ps | ||
| T8 | /workspace/coverage/default/16.prim_async_alert.528793600 | Aug 11 04:41:37 PM PDT 24 | Aug 11 04:41:37 PM PDT 24 | 11030802 ps | ||
| T22 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1757739838 | Aug 11 06:38:55 PM PDT 24 | Aug 11 06:38:56 PM PDT 24 | 30605198 ps | ||
| T39 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1615820372 | Aug 11 06:39:01 PM PDT 24 | Aug 11 06:39:01 PM PDT 24 | 28343178 ps | ||
| T23 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3718661006 | Aug 11 06:39:03 PM PDT 24 | Aug 11 06:39:04 PM PDT 24 | 30938072 ps | ||
| T13 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3600354472 | Aug 11 06:38:51 PM PDT 24 | Aug 11 06:38:51 PM PDT 24 | 32626678 ps | ||
| T40 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1450378321 | Aug 11 06:39:02 PM PDT 24 | Aug 11 06:39:02 PM PDT 24 | 29445755 ps | ||
| T41 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1232159256 | Aug 11 06:38:53 PM PDT 24 | Aug 11 06:38:54 PM PDT 24 | 28162057 ps | ||
| T42 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2291933690 | Aug 11 06:39:01 PM PDT 24 | Aug 11 06:39:02 PM PDT 24 | 30187488 ps | ||
| T43 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2105911137 | Aug 11 06:38:53 PM PDT 24 | Aug 11 06:38:54 PM PDT 24 | 32238359 ps | ||
| T24 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3275572917 | Aug 11 06:39:01 PM PDT 24 | Aug 11 06:39:02 PM PDT 24 | 31094026 ps | ||
| T44 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3185455285 | Aug 11 06:38:49 PM PDT 24 | Aug 11 06:38:49 PM PDT 24 | 27778792 ps | ||
| T14 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2504323760 | Aug 11 06:39:03 PM PDT 24 | Aug 11 06:39:04 PM PDT 24 | 30677847 ps | ||
| T49 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2761859654 | Aug 11 06:38:50 PM PDT 24 | Aug 11 06:38:50 PM PDT 24 | 29244650 ps | ||
| T50 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.357345206 | Aug 11 06:39:03 PM PDT 24 | Aug 11 06:39:04 PM PDT 24 | 28114306 ps | ||
| T51 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2077713315 | Aug 11 06:38:53 PM PDT 24 | Aug 11 06:38:54 PM PDT 24 | 30340037 ps | ||
| T52 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2375688501 | Aug 11 06:38:49 PM PDT 24 | Aug 11 06:38:50 PM PDT 24 | 29815383 ps | ||
| T53 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4043229678 | Aug 11 06:38:58 PM PDT 24 | Aug 11 06:38:58 PM PDT 24 | 30716845 ps | ||
| T54 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.657070514 | Aug 11 06:39:01 PM PDT 24 | Aug 11 06:39:01 PM PDT 24 | 30141219 ps | ||
| T55 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1972938600 | Aug 11 06:38:56 PM PDT 24 | Aug 11 06:38:56 PM PDT 24 | 30469716 ps | ||
| T56 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3498498107 | Aug 11 06:39:03 PM PDT 24 | Aug 11 06:39:04 PM PDT 24 | 30139890 ps | ||
| T34 | /workspace/coverage/sync_alert/3.prim_sync_alert.3485552488 | Aug 11 04:41:29 PM PDT 24 | Aug 11 04:41:34 PM PDT 24 | 8052377 ps | ||
| T25 | /workspace/coverage/sync_alert/4.prim_sync_alert.754096006 | Aug 11 04:41:41 PM PDT 24 | Aug 11 04:41:41 PM PDT 24 | 10713122 ps | ||
| T26 | /workspace/coverage/sync_alert/8.prim_sync_alert.2931497716 | Aug 11 04:41:40 PM PDT 24 | Aug 11 04:41:41 PM PDT 24 | 8358782 ps | ||
| T27 | /workspace/coverage/sync_alert/12.prim_sync_alert.2521554280 | Aug 11 04:41:50 PM PDT 24 | Aug 11 04:41:50 PM PDT 24 | 8680651 ps | ||
| T35 | /workspace/coverage/sync_alert/13.prim_sync_alert.1024987464 | Aug 11 04:41:36 PM PDT 24 | Aug 11 04:41:36 PM PDT 24 | 8467973 ps | ||
| T36 | /workspace/coverage/sync_alert/15.prim_sync_alert.1966819586 | Aug 11 04:41:45 PM PDT 24 | Aug 11 04:41:46 PM PDT 24 | 8125218 ps | ||
| T9 | /workspace/coverage/sync_alert/17.prim_sync_alert.747894071 | Aug 11 04:41:41 PM PDT 24 | Aug 11 04:41:41 PM PDT 24 | 9457297 ps | ||
| T37 | /workspace/coverage/sync_alert/7.prim_sync_alert.4015532489 | Aug 11 04:41:45 PM PDT 24 | Aug 11 04:41:50 PM PDT 24 | 8733593 ps | ||
| T38 | /workspace/coverage/sync_alert/16.prim_sync_alert.700103359 | Aug 11 04:41:47 PM PDT 24 | Aug 11 04:41:48 PM PDT 24 | 9228942 ps | ||
| T28 | /workspace/coverage/sync_alert/2.prim_sync_alert.1963560384 | Aug 11 04:41:29 PM PDT 24 | Aug 11 04:41:30 PM PDT 24 | 9970172 ps | ||
| T29 | /workspace/coverage/sync_alert/0.prim_sync_alert.4093436005 | Aug 11 04:41:43 PM PDT 24 | Aug 11 04:41:43 PM PDT 24 | 9404608 ps | ||
| T30 | /workspace/coverage/sync_alert/19.prim_sync_alert.3966749547 | Aug 11 04:42:01 PM PDT 24 | Aug 11 04:42:01 PM PDT 24 | 9263504 ps | ||
| T57 | /workspace/coverage/sync_alert/11.prim_sync_alert.383025098 | Aug 11 04:41:38 PM PDT 24 | Aug 11 04:41:39 PM PDT 24 | 8797035 ps | ||
| T58 | /workspace/coverage/sync_alert/10.prim_sync_alert.2418336375 | Aug 11 04:41:28 PM PDT 24 | Aug 11 04:41:29 PM PDT 24 | 9319284 ps | ||
| T59 | /workspace/coverage/sync_alert/1.prim_sync_alert.3867843754 | Aug 11 04:41:37 PM PDT 24 | Aug 11 04:41:38 PM PDT 24 | 9691932 ps | ||
| T31 | /workspace/coverage/sync_alert/14.prim_sync_alert.2413313841 | Aug 11 04:41:43 PM PDT 24 | Aug 11 04:41:43 PM PDT 24 | 9524387 ps | ||
| T32 | /workspace/coverage/sync_alert/6.prim_sync_alert.1855247344 | Aug 11 04:41:37 PM PDT 24 | Aug 11 04:41:37 PM PDT 24 | 8001435 ps | ||
| T60 | /workspace/coverage/sync_alert/9.prim_sync_alert.1640856649 | Aug 11 04:42:08 PM PDT 24 | Aug 11 04:42:08 PM PDT 24 | 8461636 ps | ||
| T61 | /workspace/coverage/sync_alert/18.prim_sync_alert.3132026675 | Aug 11 04:41:31 PM PDT 24 | Aug 11 04:41:31 PM PDT 24 | 9296727 ps | ||
| T33 | /workspace/coverage/sync_alert/5.prim_sync_alert.1004023255 | Aug 11 04:41:38 PM PDT 24 | Aug 11 04:41:39 PM PDT 24 | 8497083 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.448318497 | Aug 11 06:40:01 PM PDT 24 | Aug 11 06:40:02 PM PDT 24 | 26497543 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1329285764 | Aug 11 06:40:00 PM PDT 24 | Aug 11 06:40:00 PM PDT 24 | 28930101 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.668927774 | Aug 11 06:39:55 PM PDT 24 | Aug 11 06:39:56 PM PDT 24 | 26926654 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1903712743 | Aug 11 06:39:56 PM PDT 24 | Aug 11 06:39:57 PM PDT 24 | 25588979 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3464804736 | Aug 11 06:39:52 PM PDT 24 | Aug 11 06:39:52 PM PDT 24 | 27989285 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.872584816 | Aug 11 06:39:54 PM PDT 24 | Aug 11 06:39:55 PM PDT 24 | 27009638 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.753591832 | Aug 11 06:39:57 PM PDT 24 | Aug 11 06:39:58 PM PDT 24 | 28963355 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.278877481 | Aug 11 06:40:04 PM PDT 24 | Aug 11 06:40:04 PM PDT 24 | 28629026 ps | ||
| T4 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2328042704 | Aug 11 06:39:54 PM PDT 24 | Aug 11 06:39:54 PM PDT 24 | 27762882 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3210079594 | Aug 11 06:39:56 PM PDT 24 | Aug 11 06:39:57 PM PDT 24 | 28336352 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1837299605 | Aug 11 06:39:57 PM PDT 24 | Aug 11 06:39:57 PM PDT 24 | 27526745 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2653280126 | Aug 11 06:39:56 PM PDT 24 | Aug 11 06:39:57 PM PDT 24 | 28805958 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2246631448 | Aug 11 06:39:56 PM PDT 24 | Aug 11 06:39:56 PM PDT 24 | 27318239 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2621392452 | Aug 11 06:39:56 PM PDT 24 | Aug 11 06:39:57 PM PDT 24 | 28930156 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2356082399 | Aug 11 06:39:54 PM PDT 24 | Aug 11 06:39:54 PM PDT 24 | 28578050 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2089153155 | Aug 11 06:39:59 PM PDT 24 | Aug 11 06:39:59 PM PDT 24 | 27258873 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3114127835 | Aug 11 06:39:54 PM PDT 24 | Aug 11 06:39:54 PM PDT 24 | 27093349 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2239294990 | Aug 11 06:39:56 PM PDT 24 | Aug 11 06:39:57 PM PDT 24 | 27110160 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1220372206 | Aug 11 06:39:48 PM PDT 24 | Aug 11 06:39:48 PM PDT 24 | 26322811 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.877683082 | Aug 11 06:39:56 PM PDT 24 | Aug 11 06:39:57 PM PDT 24 | 26028768 ps |
| Test location | /workspace/coverage/default/13.prim_async_alert.2299749417 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11790009 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:24 PM PDT 24 |
| Finished | Aug 11 04:41:24 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-0d5b0301-871f-4382-bc5f-74e975bda0d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299749417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2299749417 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.754096006 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10713122 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 04:41:41 PM PDT 24 |
| Finished | Aug 11 04:41:41 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-1b314101-817c-439f-9209-15612c19fb60 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=754096006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.754096006 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3275572917 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 31094026 ps |
| CPU time | 0.44 seconds |
| Started | Aug 11 06:39:01 PM PDT 24 |
| Finished | Aug 11 06:39:02 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-cd9a7895-5b1a-4e9e-86e7-4d46223fd2c9 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3275572917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3275572917 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.2500985761 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11391477 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:31 PM PDT 24 |
| Finished | Aug 11 04:41:31 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-6b23b8ce-5d0e-4ec3-9379-dc0ca4d5d9d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500985761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2500985761 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.747894071 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9457297 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:41 PM PDT 24 |
| Finished | Aug 11 04:41:41 PM PDT 24 |
| Peak memory | 145488 kb |
| Host | smart-e265c1f9-5508-408d-b060-c9f78a182157 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=747894071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.747894071 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2653280126 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 28805958 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:39:56 PM PDT 24 |
| Finished | Aug 11 06:39:57 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-ca1eaf29-54f0-4d2c-9a5d-53bfd8ab5fe4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2653280126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2653280126 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3691044086 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12117781 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:31 PM PDT 24 |
| Finished | Aug 11 04:41:32 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-520a6d3b-b8be-41cb-a730-91b9197878d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691044086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3691044086 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.1650056905 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11132369 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:30 PM PDT 24 |
| Finished | Aug 11 04:41:31 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-bd0abc67-7ac7-46d3-b1f2-c7b7c23118cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650056905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1650056905 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.667469342 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10844088 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 04:41:24 PM PDT 24 |
| Finished | Aug 11 04:41:24 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-4b22a163-c6e5-4507-ab66-9ea7136de314 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=667469342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.667469342 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.1761617392 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10965993 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:44 PM PDT 24 |
| Finished | Aug 11 04:41:44 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-cef307bb-ffce-4bcb-aa8c-ca11fb53d373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1761617392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1761617392 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.3793783308 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11058339 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:30 PM PDT 24 |
| Finished | Aug 11 04:41:31 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-8db56539-9220-4da5-9647-c94409ed5347 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3793783308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3793783308 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.798229754 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11644742 ps |
| CPU time | 0.37 seconds |
| Started | Aug 11 04:41:29 PM PDT 24 |
| Finished | Aug 11 04:41:29 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-09d9b28f-9865-43bd-89e3-5dd1921e171c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798229754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.798229754 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.528793600 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11030802 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:37 PM PDT 24 |
| Finished | Aug 11 04:41:37 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-6e49d0bb-6b69-4f2e-a98a-2ba5c677b87a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528793600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.528793600 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.658630921 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11860636 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:28 PM PDT 24 |
| Finished | Aug 11 04:41:29 PM PDT 24 |
| Peak memory | 145756 kb |
| Host | smart-7d80a1e1-8398-45e5-8f78-0d5e26240d0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=658630921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.658630921 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1005478175 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10991701 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:36 PM PDT 24 |
| Finished | Aug 11 04:41:37 PM PDT 24 |
| Peak memory | 145524 kb |
| Host | smart-916a6e4f-00ad-4bb3-a97d-6ec22a513c52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005478175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1005478175 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.4141144629 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10988120 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:29 PM PDT 24 |
| Finished | Aug 11 04:41:30 PM PDT 24 |
| Peak memory | 144760 kb |
| Host | smart-074e0b88-8b9d-4aa0-8e06-1f9d10ed9b9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141144629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.4141144629 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.1066037314 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10722312 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:25 PM PDT 24 |
| Finished | Aug 11 04:41:25 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-1e22b5bd-f1fb-4b63-b2ad-8e165f1f286b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066037314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1066037314 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.2828806001 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10888359 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:32 PM PDT 24 |
| Finished | Aug 11 04:41:32 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-469e828d-2e66-4dbc-8e01-763185bc6b8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828806001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2828806001 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.4160655316 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11761255 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:35 PM PDT 24 |
| Finished | Aug 11 04:41:36 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-3f251546-d403-4792-9eb6-b081382407f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160655316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.4160655316 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1746913378 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11048517 ps |
| CPU time | 0.37 seconds |
| Started | Aug 11 04:41:29 PM PDT 24 |
| Finished | Aug 11 04:41:29 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-273f3017-2096-4450-9ce4-0fc51d3ff48f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746913378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1746913378 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.154564005 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11276897 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:53 PM PDT 24 |
| Finished | Aug 11 04:41:53 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-277f1caf-d392-402b-a56e-a1a125828a8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154564005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.154564005 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3721002285 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10920003 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 04:41:32 PM PDT 24 |
| Finished | Aug 11 04:41:32 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-699e21e3-d48f-48c4-8a91-9d3b5c7576ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721002285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3721002285 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2671373273 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11551549 ps |
| CPU time | 0.41 seconds |
| Started | Aug 11 04:41:31 PM PDT 24 |
| Finished | Aug 11 04:41:31 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-6b270942-14f9-4949-a1c6-85a04dc32f71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671373273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2671373273 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1859629433 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11587214 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 04:41:37 PM PDT 24 |
| Finished | Aug 11 04:41:37 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-b04a90a0-4803-46d0-9f13-dbb43653e9d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859629433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1859629433 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.657070514 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30141219 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 06:39:01 PM PDT 24 |
| Finished | Aug 11 06:39:01 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-04f11cd6-fea3-4087-8043-e441ef37ec6d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=657070514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.657070514 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3185455285 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 27778792 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 06:38:49 PM PDT 24 |
| Finished | Aug 11 06:38:49 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-5b7865e3-7d37-4580-a529-6d0562613b3d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3185455285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3185455285 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1450378321 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29445755 ps |
| CPU time | 0.41 seconds |
| Started | Aug 11 06:39:02 PM PDT 24 |
| Finished | Aug 11 06:39:02 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-7d2eb0c4-0775-4a69-abf3-7f660bc0903f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1450378321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1450378321 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1757739838 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 30605198 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 06:38:55 PM PDT 24 |
| Finished | Aug 11 06:38:56 PM PDT 24 |
| Peak memory | 145360 kb |
| Host | smart-780e4093-25c2-4f5a-a001-7ceb04b504d5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1757739838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1757739838 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2077713315 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30340037 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 06:38:53 PM PDT 24 |
| Finished | Aug 11 06:38:54 PM PDT 24 |
| Peak memory | 145356 kb |
| Host | smart-2936f607-e108-4e8a-acf1-bb5c61a618d4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2077713315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2077713315 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2105911137 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 32238359 ps |
| CPU time | 0.41 seconds |
| Started | Aug 11 06:38:53 PM PDT 24 |
| Finished | Aug 11 06:38:54 PM PDT 24 |
| Peak memory | 145340 kb |
| Host | smart-e50b1cf9-9c42-4123-9163-ec7aaa21d2ab |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2105911137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2105911137 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3718661006 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 30938072 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 06:39:03 PM PDT 24 |
| Finished | Aug 11 06:39:04 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-b173cf7b-118f-4232-b86c-20e8c18c9923 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3718661006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3718661006 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.357345206 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 28114306 ps |
| CPU time | 0.41 seconds |
| Started | Aug 11 06:39:03 PM PDT 24 |
| Finished | Aug 11 06:39:04 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-07d41e8a-afb3-454e-a6e2-68a0ea5be57d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=357345206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.357345206 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2291933690 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30187488 ps |
| CPU time | 0.42 seconds |
| Started | Aug 11 06:39:01 PM PDT 24 |
| Finished | Aug 11 06:39:02 PM PDT 24 |
| Peak memory | 145328 kb |
| Host | smart-b1cc016c-c077-4633-9229-d0b6aeb16e03 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2291933690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2291933690 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1615820372 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 28343178 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:39:01 PM PDT 24 |
| Finished | Aug 11 06:39:01 PM PDT 24 |
| Peak memory | 145364 kb |
| Host | smart-55e0bd50-e238-40d7-b7b9-8bc6b4acf259 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1615820372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1615820372 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2761859654 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29244650 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:38:50 PM PDT 24 |
| Finished | Aug 11 06:38:50 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-408fd895-1ed3-43bf-8802-c2744ac63e45 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2761859654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2761859654 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1232159256 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 28162057 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:38:53 PM PDT 24 |
| Finished | Aug 11 06:38:54 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-9ce73997-7892-457f-ac14-c862e87dd0b0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1232159256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1232159256 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3498498107 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30139890 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 06:39:03 PM PDT 24 |
| Finished | Aug 11 06:39:04 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-c23692eb-abb4-4f4f-aed5-2f9120665631 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3498498107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3498498107 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4043229678 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30716845 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:38:58 PM PDT 24 |
| Finished | Aug 11 06:38:58 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-be32544f-86e2-4c3d-9285-0fe13dfe51d7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4043229678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.4043229678 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1972938600 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 30469716 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:38:56 PM PDT 24 |
| Finished | Aug 11 06:38:56 PM PDT 24 |
| Peak memory | 145324 kb |
| Host | smart-b1f94054-6bbf-4eaa-b8ab-aa93d91db175 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1972938600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1972938600 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3600354472 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 32626678 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:38:51 PM PDT 24 |
| Finished | Aug 11 06:38:51 PM PDT 24 |
| Peak memory | 145276 kb |
| Host | smart-43232593-d307-4c49-a75c-92e9baed2070 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3600354472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3600354472 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2375688501 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 29815383 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 06:38:49 PM PDT 24 |
| Finished | Aug 11 06:38:50 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-0003fa06-6dea-4c89-88bd-9d2f3068f280 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2375688501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2375688501 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2504323760 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 30677847 ps |
| CPU time | 0.41 seconds |
| Started | Aug 11 06:39:03 PM PDT 24 |
| Finished | Aug 11 06:39:04 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-417a1355-1842-4ea5-bddb-323f0ad5a897 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2504323760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2504323760 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.4093436005 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9404608 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:43 PM PDT 24 |
| Finished | Aug 11 04:41:43 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-44b0d709-51f3-44e7-a768-07e5c383cde4 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4093436005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4093436005 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.3867843754 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9691932 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 04:41:37 PM PDT 24 |
| Finished | Aug 11 04:41:38 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-55ced4a6-96c6-45f1-92a8-982cee9a399f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3867843754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3867843754 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.2418336375 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9319284 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:28 PM PDT 24 |
| Finished | Aug 11 04:41:29 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-abc79db9-7399-4066-b82a-ce1ff4bd6ef3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2418336375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2418336375 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.383025098 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8797035 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 04:41:38 PM PDT 24 |
| Finished | Aug 11 04:41:39 PM PDT 24 |
| Peak memory | 145476 kb |
| Host | smart-7b696a0e-92ee-464a-bfa0-9142efc55477 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=383025098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.383025098 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2521554280 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8680651 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:50 PM PDT 24 |
| Finished | Aug 11 04:41:50 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-6bffc917-1089-4d7b-aedb-8f8447fd3d13 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2521554280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2521554280 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.1024987464 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8467973 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:36 PM PDT 24 |
| Finished | Aug 11 04:41:36 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-dfac2a89-c270-48a7-a9bd-465f71bb59f6 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1024987464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1024987464 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.2413313841 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9524387 ps |
| CPU time | 0.41 seconds |
| Started | Aug 11 04:41:43 PM PDT 24 |
| Finished | Aug 11 04:41:43 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-19930ff9-5ae2-4650-a4c3-cb5b1bfe96a3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2413313841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2413313841 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.1966819586 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8125218 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:45 PM PDT 24 |
| Finished | Aug 11 04:41:46 PM PDT 24 |
| Peak memory | 145460 kb |
| Host | smart-d453c799-1980-4f32-96a9-1d4b6079b899 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1966819586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1966819586 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.700103359 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9228942 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:47 PM PDT 24 |
| Finished | Aug 11 04:41:48 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-c16ed7f7-35ff-43d1-8100-c1436953f9ef |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=700103359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.700103359 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3132026675 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9296727 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:41:31 PM PDT 24 |
| Finished | Aug 11 04:41:31 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-fb0eb946-2e48-411d-a9c3-9175f6fed9e2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3132026675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3132026675 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.3966749547 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9263504 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 04:42:01 PM PDT 24 |
| Finished | Aug 11 04:42:01 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-fc423b0c-d710-4d6d-89f0-f0cb233e2e8c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3966749547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3966749547 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.1963560384 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9970172 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:29 PM PDT 24 |
| Finished | Aug 11 04:41:30 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-5ad8066c-2aa9-4396-ac89-4b529c18d38a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1963560384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1963560384 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3485552488 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8052377 ps |
| CPU time | 0.37 seconds |
| Started | Aug 11 04:41:29 PM PDT 24 |
| Finished | Aug 11 04:41:34 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-7716e51d-50a8-498d-9485-998dff5c5588 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3485552488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3485552488 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.1004023255 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8497083 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:38 PM PDT 24 |
| Finished | Aug 11 04:41:39 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-31840a68-61b4-47a4-a6b3-131afb44c2fc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1004023255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1004023255 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.1855247344 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8001435 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 04:41:37 PM PDT 24 |
| Finished | Aug 11 04:41:37 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-1a038f87-2a6e-44a1-97d1-062fad1532ab |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1855247344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1855247344 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.4015532489 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8733593 ps |
| CPU time | 0.37 seconds |
| Started | Aug 11 04:41:45 PM PDT 24 |
| Finished | Aug 11 04:41:50 PM PDT 24 |
| Peak memory | 145468 kb |
| Host | smart-82c53e97-f67b-4ed5-a4c7-a0b245ac6cc0 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4015532489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.4015532489 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.2931497716 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8358782 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 04:41:40 PM PDT 24 |
| Finished | Aug 11 04:41:41 PM PDT 24 |
| Peak memory | 145472 kb |
| Host | smart-1ef4f2d0-f30b-4b84-a957-cc5a69883d7e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2931497716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2931497716 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1640856649 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8461636 ps |
| CPU time | 0.43 seconds |
| Started | Aug 11 04:42:08 PM PDT 24 |
| Finished | Aug 11 04:42:08 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-175ea4a2-01c1-44e8-9835-ef22a63e052d |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1640856649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1640856649 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2239294990 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27110160 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:39:56 PM PDT 24 |
| Finished | Aug 11 06:39:57 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-81ebcba9-44e2-4759-be5c-989012ca3569 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2239294990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2239294990 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.872584816 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27009638 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:39:54 PM PDT 24 |
| Finished | Aug 11 06:39:55 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-93c6d643-3eca-4c04-be34-295587060601 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=872584816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.872584816 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.448318497 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26497543 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 06:40:01 PM PDT 24 |
| Finished | Aug 11 06:40:02 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-a5492535-d0ce-4310-80c1-8a35a73d0efb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=448318497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.448318497 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.278877481 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28629026 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 06:40:04 PM PDT 24 |
| Finished | Aug 11 06:40:04 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-1a51fa1d-ebc3-4f68-9256-e7aab5d78413 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=278877481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.278877481 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2246631448 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27318239 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 06:39:56 PM PDT 24 |
| Finished | Aug 11 06:39:56 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-fa59d896-2f37-4742-9058-d4216a56827c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2246631448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2246631448 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2089153155 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27258873 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 06:39:59 PM PDT 24 |
| Finished | Aug 11 06:39:59 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-9748b697-7f5c-44a2-ba89-9a9633bdb522 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2089153155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2089153155 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2328042704 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 27762882 ps |
| CPU time | 0.38 seconds |
| Started | Aug 11 06:39:54 PM PDT 24 |
| Finished | Aug 11 06:39:54 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-4309b86d-6143-4f2f-9f94-6683226bdf55 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2328042704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2328042704 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3464804736 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27989285 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:39:52 PM PDT 24 |
| Finished | Aug 11 06:39:52 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-58fa5c70-47a6-40ef-8755-f6536527c9cd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3464804736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3464804736 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1220372206 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26322811 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 06:39:48 PM PDT 24 |
| Finished | Aug 11 06:39:48 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-50bafc01-f520-49de-926e-81c3539238ec |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1220372206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1220372206 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3114127835 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27093349 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:39:54 PM PDT 24 |
| Finished | Aug 11 06:39:54 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-082f9a33-91ed-49e1-bab3-e3a92d0745a1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3114127835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3114127835 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1329285764 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 28930101 ps |
| CPU time | 0.42 seconds |
| Started | Aug 11 06:40:00 PM PDT 24 |
| Finished | Aug 11 06:40:00 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-fd88007f-7ece-4f02-a609-15ba33b1bc56 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1329285764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1329285764 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1903712743 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 25588979 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:39:56 PM PDT 24 |
| Finished | Aug 11 06:39:57 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-03d72b49-8ef6-4e15-8a2c-cc314b1b70b2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1903712743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1903712743 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2621392452 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 28930156 ps |
| CPU time | 0.41 seconds |
| Started | Aug 11 06:39:56 PM PDT 24 |
| Finished | Aug 11 06:39:57 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-3035d254-f568-4c6c-8eb4-a02afd54a89a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2621392452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2621392452 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3210079594 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28336352 ps |
| CPU time | 0.42 seconds |
| Started | Aug 11 06:39:56 PM PDT 24 |
| Finished | Aug 11 06:39:57 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-3a526039-3c5b-4184-bfc9-5e07cd64f821 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3210079594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3210079594 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.753591832 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28963355 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:39:57 PM PDT 24 |
| Finished | Aug 11 06:39:58 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-88164657-3662-434e-b49c-db46103bd3b7 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=753591832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.753591832 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1837299605 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27526745 ps |
| CPU time | 0.47 seconds |
| Started | Aug 11 06:39:57 PM PDT 24 |
| Finished | Aug 11 06:39:57 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-b1c26719-45ad-4fbe-90c8-02da2f480057 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1837299605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1837299605 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.877683082 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26028768 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:39:56 PM PDT 24 |
| Finished | Aug 11 06:39:57 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-992ad30e-c31f-447b-9aa6-5f2b75ef5a09 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=877683082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.877683082 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.668927774 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26926654 ps |
| CPU time | 0.39 seconds |
| Started | Aug 11 06:39:55 PM PDT 24 |
| Finished | Aug 11 06:39:56 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-29d2460f-d685-4496-8e7d-20c3d1abdafd |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=668927774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.668927774 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2356082399 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28578050 ps |
| CPU time | 0.4 seconds |
| Started | Aug 11 06:39:54 PM PDT 24 |
| Finished | Aug 11 06:39:54 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-d300d8fb-876e-4e67-ab29-4c9e641ed240 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2356082399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2356082399 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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