Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.88 88.88 100.00 100.00 93.75 93.75 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/18.prim_async_alert.3314975076
92.01 3.13 100.00 0.00 93.75 0.00 100.00 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/14.prim_sync_alert.2389953305
94.50 2.49 100.00 0.00 95.83 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.605793527
95.19 0.69 100.00 0.00 100.00 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.125676327

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1000789810
/workspace/coverage/default/1.prim_async_alert.713072291
/workspace/coverage/default/10.prim_async_alert.2154697718
/workspace/coverage/default/11.prim_async_alert.477273413
/workspace/coverage/default/12.prim_async_alert.3189438384
/workspace/coverage/default/13.prim_async_alert.1457309524
/workspace/coverage/default/14.prim_async_alert.2380232154
/workspace/coverage/default/15.prim_async_alert.845057592
/workspace/coverage/default/16.prim_async_alert.3297630099
/workspace/coverage/default/17.prim_async_alert.1126522953
/workspace/coverage/default/19.prim_async_alert.4107136840
/workspace/coverage/default/2.prim_async_alert.2688520334
/workspace/coverage/default/3.prim_async_alert.684945334
/workspace/coverage/default/4.prim_async_alert.470403864
/workspace/coverage/default/5.prim_async_alert.2483399411
/workspace/coverage/default/6.prim_async_alert.4285213004
/workspace/coverage/default/7.prim_async_alert.1697888481
/workspace/coverage/default/8.prim_async_alert.1697221059
/workspace/coverage/default/9.prim_async_alert.2848954095
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.32866109
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3451654904
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1044926221
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1601487658
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1512529375
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1070659432
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.987888969
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3987939017
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3303728904
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1992296998
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1298750782
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2016693092
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2061249789
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3207964035
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3782518284
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3001775701
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3754189832
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1198003759
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.314042458
/workspace/coverage/sync_alert/0.prim_sync_alert.1157657445
/workspace/coverage/sync_alert/1.prim_sync_alert.1738680190
/workspace/coverage/sync_alert/10.prim_sync_alert.593614833
/workspace/coverage/sync_alert/11.prim_sync_alert.28193967
/workspace/coverage/sync_alert/12.prim_sync_alert.4220744521
/workspace/coverage/sync_alert/13.prim_sync_alert.3909933928
/workspace/coverage/sync_alert/15.prim_sync_alert.4043278396
/workspace/coverage/sync_alert/16.prim_sync_alert.1877606767
/workspace/coverage/sync_alert/17.prim_sync_alert.222704224
/workspace/coverage/sync_alert/18.prim_sync_alert.2289334952
/workspace/coverage/sync_alert/19.prim_sync_alert.3993363172
/workspace/coverage/sync_alert/2.prim_sync_alert.1472301656
/workspace/coverage/sync_alert/3.prim_sync_alert.1984382553
/workspace/coverage/sync_alert/4.prim_sync_alert.3444918175
/workspace/coverage/sync_alert/5.prim_sync_alert.2597768067
/workspace/coverage/sync_alert/6.prim_sync_alert.144703460
/workspace/coverage/sync_alert/7.prim_sync_alert.3009096439
/workspace/coverage/sync_alert/8.prim_sync_alert.759459708
/workspace/coverage/sync_alert/9.prim_sync_alert.999311508
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1632218583
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1405036065
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.492291771
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2300071486
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2755920202
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1278266218
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3350795946
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.942778567
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1657623518
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.299073624
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3774966511
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.530909700
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.251678646
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3167009402
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4260171727
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.502130163
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.742962017
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2522259633
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3690720579



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.prim_async_alert.2848954095 Aug 12 06:18:26 PM PDT 24 Aug 12 06:18:26 PM PDT 24 11078691 ps
T2 /workspace/coverage/default/18.prim_async_alert.3314975076 Aug 12 06:18:32 PM PDT 24 Aug 12 06:18:32 PM PDT 24 12312437 ps
T3 /workspace/coverage/default/5.prim_async_alert.2483399411 Aug 12 06:18:25 PM PDT 24 Aug 12 06:18:26 PM PDT 24 11647169 ps
T12 /workspace/coverage/default/0.prim_async_alert.1000789810 Aug 12 06:18:25 PM PDT 24 Aug 12 06:18:26 PM PDT 24 11375111 ps
T18 /workspace/coverage/default/2.prim_async_alert.2688520334 Aug 12 06:18:28 PM PDT 24 Aug 12 06:18:29 PM PDT 24 10625192 ps
T19 /workspace/coverage/default/7.prim_async_alert.1697888481 Aug 12 06:18:31 PM PDT 24 Aug 12 06:18:32 PM PDT 24 10835077 ps
T20 /workspace/coverage/default/6.prim_async_alert.4285213004 Aug 12 06:18:30 PM PDT 24 Aug 12 06:18:30 PM PDT 24 11799011 ps
T7 /workspace/coverage/default/14.prim_async_alert.2380232154 Aug 12 06:18:28 PM PDT 24 Aug 12 06:18:28 PM PDT 24 10533892 ps
T8 /workspace/coverage/default/4.prim_async_alert.470403864 Aug 12 06:18:26 PM PDT 24 Aug 12 06:18:26 PM PDT 24 10566647 ps
T21 /workspace/coverage/default/15.prim_async_alert.845057592 Aug 12 06:18:26 PM PDT 24 Aug 12 06:18:26 PM PDT 24 11920590 ps
T9 /workspace/coverage/default/16.prim_async_alert.3297630099 Aug 12 06:18:24 PM PDT 24 Aug 12 06:18:25 PM PDT 24 11273534 ps
T22 /workspace/coverage/default/19.prim_async_alert.4107136840 Aug 12 06:18:25 PM PDT 24 Aug 12 06:18:25 PM PDT 24 11598617 ps
T16 /workspace/coverage/default/12.prim_async_alert.3189438384 Aug 12 06:18:25 PM PDT 24 Aug 12 06:18:26 PM PDT 24 12349435 ps
T48 /workspace/coverage/default/17.prim_async_alert.1126522953 Aug 12 06:18:29 PM PDT 24 Aug 12 06:18:29 PM PDT 24 10177705 ps
T13 /workspace/coverage/default/10.prim_async_alert.2154697718 Aug 12 06:18:26 PM PDT 24 Aug 12 06:18:26 PM PDT 24 11265022 ps
T17 /workspace/coverage/default/8.prim_async_alert.1697221059 Aug 12 06:18:28 PM PDT 24 Aug 12 06:18:29 PM PDT 24 11143597 ps
T14 /workspace/coverage/default/3.prim_async_alert.684945334 Aug 12 06:18:26 PM PDT 24 Aug 12 06:18:27 PM PDT 24 11384611 ps
T40 /workspace/coverage/default/11.prim_async_alert.477273413 Aug 12 06:18:28 PM PDT 24 Aug 12 06:18:28 PM PDT 24 10437674 ps
T49 /workspace/coverage/default/13.prim_async_alert.1457309524 Aug 12 06:18:31 PM PDT 24 Aug 12 06:18:32 PM PDT 24 11375860 ps
T50 /workspace/coverage/default/1.prim_async_alert.713072291 Aug 12 06:18:27 PM PDT 24 Aug 12 06:18:27 PM PDT 24 10716959 ps
T23 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1512529375 Aug 12 04:21:53 PM PDT 24 Aug 12 04:21:53 PM PDT 24 28281191 ps
T24 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3754189832 Aug 12 04:22:20 PM PDT 24 Aug 12 04:22:21 PM PDT 24 30032336 ps
T41 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1070659432 Aug 12 04:21:54 PM PDT 24 Aug 12 04:21:54 PM PDT 24 31345392 ps
T42 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3303728904 Aug 12 04:26:56 PM PDT 24 Aug 12 04:26:57 PM PDT 24 30917899 ps
T43 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2016693092 Aug 12 04:22:31 PM PDT 24 Aug 12 04:22:31 PM PDT 24 29539214 ps
T15 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.605793527 Aug 12 04:21:19 PM PDT 24 Aug 12 04:21:20 PM PDT 24 30169702 ps
T44 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2061249789 Aug 12 04:23:04 PM PDT 24 Aug 12 04:23:05 PM PDT 24 30436898 ps
T45 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.987888969 Aug 12 04:26:28 PM PDT 24 Aug 12 04:26:29 PM PDT 24 29206564 ps
T46 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3782518284 Aug 12 04:22:46 PM PDT 24 Aug 12 04:22:47 PM PDT 24 31202555 ps
T47 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3001775701 Aug 12 04:26:31 PM PDT 24 Aug 12 04:26:32 PM PDT 24 31699709 ps
T51 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1992296998 Aug 12 04:22:18 PM PDT 24 Aug 12 04:22:19 PM PDT 24 30625884 ps
T52 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.32866109 Aug 12 04:22:55 PM PDT 24 Aug 12 04:22:55 PM PDT 24 29805073 ps
T53 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1298750782 Aug 12 04:27:50 PM PDT 24 Aug 12 04:27:50 PM PDT 24 29727321 ps
T54 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3207964035 Aug 12 04:22:19 PM PDT 24 Aug 12 04:22:19 PM PDT 24 29849997 ps
T55 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3987939017 Aug 12 04:22:17 PM PDT 24 Aug 12 04:22:18 PM PDT 24 29685523 ps
T56 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.314042458 Aug 12 04:26:25 PM PDT 24 Aug 12 04:26:26 PM PDT 24 28932056 ps
T57 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3451654904 Aug 12 04:22:16 PM PDT 24 Aug 12 04:22:17 PM PDT 24 32048512 ps
T58 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1198003759 Aug 12 04:22:16 PM PDT 24 Aug 12 04:22:17 PM PDT 24 29154721 ps
T59 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1044926221 Aug 12 04:22:17 PM PDT 24 Aug 12 04:22:18 PM PDT 24 29628463 ps
T60 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1601487658 Aug 12 04:22:47 PM PDT 24 Aug 12 04:22:48 PM PDT 24 30499021 ps
T25 /workspace/coverage/sync_alert/3.prim_sync_alert.1984382553 Aug 12 04:22:10 PM PDT 24 Aug 12 04:22:11 PM PDT 24 8971461 ps
T34 /workspace/coverage/sync_alert/18.prim_sync_alert.2289334952 Aug 12 04:21:48 PM PDT 24 Aug 12 04:21:49 PM PDT 24 9946746 ps
T26 /workspace/coverage/sync_alert/17.prim_sync_alert.222704224 Aug 12 04:26:56 PM PDT 24 Aug 12 04:26:57 PM PDT 24 10177346 ps
T35 /workspace/coverage/sync_alert/13.prim_sync_alert.3909933928 Aug 12 04:24:07 PM PDT 24 Aug 12 04:24:07 PM PDT 24 8724108 ps
T36 /workspace/coverage/sync_alert/6.prim_sync_alert.144703460 Aug 12 04:21:52 PM PDT 24 Aug 12 04:21:52 PM PDT 24 9301126 ps
T37 /workspace/coverage/sync_alert/8.prim_sync_alert.759459708 Aug 12 04:26:32 PM PDT 24 Aug 12 04:26:33 PM PDT 24 8615802 ps
T38 /workspace/coverage/sync_alert/16.prim_sync_alert.1877606767 Aug 12 04:26:53 PM PDT 24 Aug 12 04:26:54 PM PDT 24 8681170 ps
T27 /workspace/coverage/sync_alert/1.prim_sync_alert.1738680190 Aug 12 04:22:44 PM PDT 24 Aug 12 04:22:44 PM PDT 24 9134029 ps
T28 /workspace/coverage/sync_alert/19.prim_sync_alert.3993363172 Aug 12 04:26:24 PM PDT 24 Aug 12 04:26:25 PM PDT 24 9006356 ps
T39 /workspace/coverage/sync_alert/14.prim_sync_alert.2389953305 Aug 12 04:22:34 PM PDT 24 Aug 12 04:22:35 PM PDT 24 8897292 ps
T61 /workspace/coverage/sync_alert/9.prim_sync_alert.999311508 Aug 12 04:23:04 PM PDT 24 Aug 12 04:23:04 PM PDT 24 9257628 ps
T29 /workspace/coverage/sync_alert/15.prim_sync_alert.4043278396 Aug 12 04:22:21 PM PDT 24 Aug 12 04:22:21 PM PDT 24 9140269 ps
T10 /workspace/coverage/sync_alert/4.prim_sync_alert.3444918175 Aug 12 04:22:36 PM PDT 24 Aug 12 04:22:36 PM PDT 24 8895263 ps
T62 /workspace/coverage/sync_alert/12.prim_sync_alert.4220744521 Aug 12 04:26:24 PM PDT 24 Aug 12 04:26:25 PM PDT 24 8228390 ps
T63 /workspace/coverage/sync_alert/5.prim_sync_alert.2597768067 Aug 12 04:23:01 PM PDT 24 Aug 12 04:23:01 PM PDT 24 8531276 ps
T64 /workspace/coverage/sync_alert/0.prim_sync_alert.1157657445 Aug 12 04:26:56 PM PDT 24 Aug 12 04:26:57 PM PDT 24 9614276 ps
T65 /workspace/coverage/sync_alert/7.prim_sync_alert.3009096439 Aug 12 04:27:34 PM PDT 24 Aug 12 04:27:35 PM PDT 24 9539391 ps
T66 /workspace/coverage/sync_alert/11.prim_sync_alert.28193967 Aug 12 04:22:35 PM PDT 24 Aug 12 04:22:36 PM PDT 24 8344269 ps
T30 /workspace/coverage/sync_alert/10.prim_sync_alert.593614833 Aug 12 04:22:53 PM PDT 24 Aug 12 04:22:53 PM PDT 24 9697998 ps
T31 /workspace/coverage/sync_alert/2.prim_sync_alert.1472301656 Aug 12 04:21:29 PM PDT 24 Aug 12 04:21:30 PM PDT 24 8697781 ps
T67 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1657623518 Aug 12 06:18:33 PM PDT 24 Aug 12 06:18:33 PM PDT 24 28478529 ps
T32 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1405036065 Aug 12 06:18:26 PM PDT 24 Aug 12 06:18:27 PM PDT 24 28582123 ps
T11 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3690720579 Aug 12 06:18:35 PM PDT 24 Aug 12 06:18:36 PM PDT 24 27013477 ps
T33 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3774966511 Aug 12 06:18:33 PM PDT 24 Aug 12 06:18:33 PM PDT 24 28648086 ps
T68 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1278266218 Aug 12 06:18:36 PM PDT 24 Aug 12 06:18:36 PM PDT 24 26957372 ps
T69 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3350795946 Aug 12 06:18:32 PM PDT 24 Aug 12 06:18:32 PM PDT 24 28382490 ps
T70 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.942778567 Aug 12 06:18:33 PM PDT 24 Aug 12 06:18:33 PM PDT 24 26194600 ps
T71 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3167009402 Aug 12 06:18:33 PM PDT 24 Aug 12 06:18:34 PM PDT 24 27452354 ps
T4 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.530909700 Aug 12 06:18:25 PM PDT 24 Aug 12 06:18:26 PM PDT 24 27935902 ps
T72 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.299073624 Aug 12 06:18:31 PM PDT 24 Aug 12 06:18:32 PM PDT 24 25813749 ps
T73 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.251678646 Aug 12 06:18:36 PM PDT 24 Aug 12 06:18:36 PM PDT 24 26641273 ps
T74 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4260171727 Aug 12 06:18:32 PM PDT 24 Aug 12 06:18:32 PM PDT 24 28615937 ps
T5 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.125676327 Aug 12 06:18:32 PM PDT 24 Aug 12 06:18:33 PM PDT 24 30025613 ps
T6 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1632218583 Aug 12 06:18:27 PM PDT 24 Aug 12 06:18:27 PM PDT 24 25311278 ps
T75 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2755920202 Aug 12 06:18:33 PM PDT 24 Aug 12 06:18:34 PM PDT 24 26783456 ps
T76 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2300071486 Aug 12 06:18:34 PM PDT 24 Aug 12 06:18:34 PM PDT 24 29226038 ps
T77 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.492291771 Aug 12 06:18:36 PM PDT 24 Aug 12 06:18:36 PM PDT 24 26739776 ps
T78 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.502130163 Aug 12 06:18:33 PM PDT 24 Aug 12 06:18:33 PM PDT 24 26816604 ps
T79 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.742962017 Aug 12 06:18:32 PM PDT 24 Aug 12 06:18:32 PM PDT 24 28505121 ps
T80 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2522259633 Aug 12 06:18:31 PM PDT 24 Aug 12 06:18:32 PM PDT 24 29935057 ps

Test location /workspace/coverage/default/18.prim_async_alert.3314975076
Short name T2
Test name
Test status
Simulation time 12312437 ps
CPU time 0.4 seconds
Started Aug 12 06:18:32 PM PDT 24
Finished Aug 12 06:18:32 PM PDT 24
Peak memory 145760 kb
Host smart-cc000be3-6145-4d9c-ab30-3650a5e3fb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314975076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3314975076
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2389953305
Short name T39
Test name
Test status
Simulation time 8897292 ps
CPU time 0.39 seconds
Started Aug 12 04:22:34 PM PDT 24
Finished Aug 12 04:22:35 PM PDT 24
Peak memory 145500 kb
Host smart-74c83147-5891-4f36-b844-2594893331db
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2389953305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2389953305
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.605793527
Short name T15
Test name
Test status
Simulation time 30169702 ps
CPU time 0.4 seconds
Started Aug 12 04:21:19 PM PDT 24
Finished Aug 12 04:21:20 PM PDT 24
Peak memory 145212 kb
Host smart-20438033-ef67-4ee4-b99e-e79ea115e7b6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=605793527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.605793527
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.125676327
Short name T5
Test name
Test status
Simulation time 30025613 ps
CPU time 0.4 seconds
Started Aug 12 06:18:32 PM PDT 24
Finished Aug 12 06:18:33 PM PDT 24
Peak memory 145620 kb
Host smart-3191dbea-ba75-4bfd-82b9-e08b34a44fde
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=125676327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.125676327
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1000789810
Short name T12
Test name
Test status
Simulation time 11375111 ps
CPU time 0.39 seconds
Started Aug 12 06:18:25 PM PDT 24
Finished Aug 12 06:18:26 PM PDT 24
Peak memory 145696 kb
Host smart-13551ca9-0618-40c3-88d8-282155d7a12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000789810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1000789810
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.713072291
Short name T50
Test name
Test status
Simulation time 10716959 ps
CPU time 0.39 seconds
Started Aug 12 06:18:27 PM PDT 24
Finished Aug 12 06:18:27 PM PDT 24
Peak memory 145800 kb
Host smart-5c364951-d0d9-4982-bfce-ab93c284c4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713072291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.713072291
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2154697718
Short name T13
Test name
Test status
Simulation time 11265022 ps
CPU time 0.37 seconds
Started Aug 12 06:18:26 PM PDT 24
Finished Aug 12 06:18:26 PM PDT 24
Peak memory 145752 kb
Host smart-91ea5cd0-8054-4129-9f9d-c83d62ee170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154697718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2154697718
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.477273413
Short name T40
Test name
Test status
Simulation time 10437674 ps
CPU time 0.4 seconds
Started Aug 12 06:18:28 PM PDT 24
Finished Aug 12 06:18:28 PM PDT 24
Peak memory 145756 kb
Host smart-c50b0676-0e6f-43e3-8127-df106306d470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477273413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.477273413
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3189438384
Short name T16
Test name
Test status
Simulation time 12349435 ps
CPU time 0.37 seconds
Started Aug 12 06:18:25 PM PDT 24
Finished Aug 12 06:18:26 PM PDT 24
Peak memory 145764 kb
Host smart-9c342bc8-19fd-495d-aff9-9a863db96fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189438384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3189438384
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1457309524
Short name T49
Test name
Test status
Simulation time 11375860 ps
CPU time 0.39 seconds
Started Aug 12 06:18:31 PM PDT 24
Finished Aug 12 06:18:32 PM PDT 24
Peak memory 145760 kb
Host smart-a382c58d-67de-4aba-9f6b-e2c2649a34d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457309524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1457309524
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2380232154
Short name T7
Test name
Test status
Simulation time 10533892 ps
CPU time 0.4 seconds
Started Aug 12 06:18:28 PM PDT 24
Finished Aug 12 06:18:28 PM PDT 24
Peak memory 145756 kb
Host smart-1d69bf47-d027-4187-b879-b77275d99fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380232154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2380232154
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.845057592
Short name T21
Test name
Test status
Simulation time 11920590 ps
CPU time 0.38 seconds
Started Aug 12 06:18:26 PM PDT 24
Finished Aug 12 06:18:26 PM PDT 24
Peak memory 145796 kb
Host smart-3df7f73c-af6c-4d8b-87d9-6cdc6cb16b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845057592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.845057592
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3297630099
Short name T9
Test name
Test status
Simulation time 11273534 ps
CPU time 0.37 seconds
Started Aug 12 06:18:24 PM PDT 24
Finished Aug 12 06:18:25 PM PDT 24
Peak memory 145792 kb
Host smart-6271cd77-b381-42a1-9ab8-0453194d55b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297630099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3297630099
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1126522953
Short name T48
Test name
Test status
Simulation time 10177705 ps
CPU time 0.39 seconds
Started Aug 12 06:18:29 PM PDT 24
Finished Aug 12 06:18:29 PM PDT 24
Peak memory 145772 kb
Host smart-d77c10c2-00de-467a-9c97-0c934648090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126522953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1126522953
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.4107136840
Short name T22
Test name
Test status
Simulation time 11598617 ps
CPU time 0.37 seconds
Started Aug 12 06:18:25 PM PDT 24
Finished Aug 12 06:18:25 PM PDT 24
Peak memory 145776 kb
Host smart-c60c48ac-7fe2-406f-8419-05d92cc9b0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107136840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.4107136840
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2688520334
Short name T18
Test name
Test status
Simulation time 10625192 ps
CPU time 0.4 seconds
Started Aug 12 06:18:28 PM PDT 24
Finished Aug 12 06:18:29 PM PDT 24
Peak memory 145808 kb
Host smart-0468cb0d-9528-4d51-b1a1-2aaceb241ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688520334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2688520334
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.684945334
Short name T14
Test name
Test status
Simulation time 11384611 ps
CPU time 0.39 seconds
Started Aug 12 06:18:26 PM PDT 24
Finished Aug 12 06:18:27 PM PDT 24
Peak memory 145760 kb
Host smart-6fa4bb7a-3140-47f9-9d70-8341830c6d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684945334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.684945334
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.470403864
Short name T8
Test name
Test status
Simulation time 10566647 ps
CPU time 0.38 seconds
Started Aug 12 06:18:26 PM PDT 24
Finished Aug 12 06:18:26 PM PDT 24
Peak memory 145776 kb
Host smart-8ebf4014-e2b3-4e01-9d10-9fcf74902f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470403864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.470403864
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2483399411
Short name T3
Test name
Test status
Simulation time 11647169 ps
CPU time 0.42 seconds
Started Aug 12 06:18:25 PM PDT 24
Finished Aug 12 06:18:26 PM PDT 24
Peak memory 145784 kb
Host smart-0fbbd2b7-efb1-4c35-a187-fb6f9640ef41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483399411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2483399411
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.4285213004
Short name T20
Test name
Test status
Simulation time 11799011 ps
CPU time 0.4 seconds
Started Aug 12 06:18:30 PM PDT 24
Finished Aug 12 06:18:30 PM PDT 24
Peak memory 145808 kb
Host smart-2ddce840-39f1-498a-9752-f9dcb84ee258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285213004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.4285213004
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1697888481
Short name T19
Test name
Test status
Simulation time 10835077 ps
CPU time 0.39 seconds
Started Aug 12 06:18:31 PM PDT 24
Finished Aug 12 06:18:32 PM PDT 24
Peak memory 145808 kb
Host smart-1e88c811-df70-43ac-89d3-7e74d710918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697888481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1697888481
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1697221059
Short name T17
Test name
Test status
Simulation time 11143597 ps
CPU time 0.38 seconds
Started Aug 12 06:18:28 PM PDT 24
Finished Aug 12 06:18:29 PM PDT 24
Peak memory 145756 kb
Host smart-3fe58643-0eed-4f7d-854b-4da6be16385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697221059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1697221059
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2848954095
Short name T1
Test name
Test status
Simulation time 11078691 ps
CPU time 0.38 seconds
Started Aug 12 06:18:26 PM PDT 24
Finished Aug 12 06:18:26 PM PDT 24
Peak memory 145776 kb
Host smart-5cf405ce-93be-4ffd-ba8a-d183fc6742cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848954095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2848954095
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.32866109
Short name T52
Test name
Test status
Simulation time 29805073 ps
CPU time 0.4 seconds
Started Aug 12 04:22:55 PM PDT 24
Finished Aug 12 04:22:55 PM PDT 24
Peak memory 145144 kb
Host smart-589bd13b-8836-4c30-b9e2-0f1c27e69b52
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=32866109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.32866109
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3451654904
Short name T57
Test name
Test status
Simulation time 32048512 ps
CPU time 0.46 seconds
Started Aug 12 04:22:16 PM PDT 24
Finished Aug 12 04:22:17 PM PDT 24
Peak memory 143760 kb
Host smart-681fbc58-efb6-44a0-8434-b19fd95b7164
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3451654904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3451654904
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1044926221
Short name T59
Test name
Test status
Simulation time 29628463 ps
CPU time 0.44 seconds
Started Aug 12 04:22:17 PM PDT 24
Finished Aug 12 04:22:18 PM PDT 24
Peak memory 143144 kb
Host smart-c6bf439e-8a05-4dd5-9707-b9166454e2b6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1044926221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1044926221
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1601487658
Short name T60
Test name
Test status
Simulation time 30499021 ps
CPU time 0.41 seconds
Started Aug 12 04:22:47 PM PDT 24
Finished Aug 12 04:22:48 PM PDT 24
Peak memory 145092 kb
Host smart-215044a5-c7d4-4eef-bddd-fdd4d543234d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1601487658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1601487658
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1512529375
Short name T23
Test name
Test status
Simulation time 28281191 ps
CPU time 0.4 seconds
Started Aug 12 04:21:53 PM PDT 24
Finished Aug 12 04:21:53 PM PDT 24
Peak memory 145232 kb
Host smart-63bb3e50-1161-4970-ae72-cda3aa3f17ee
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1512529375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1512529375
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1070659432
Short name T41
Test name
Test status
Simulation time 31345392 ps
CPU time 0.42 seconds
Started Aug 12 04:21:54 PM PDT 24
Finished Aug 12 04:21:54 PM PDT 24
Peak memory 145368 kb
Host smart-95f50c17-2fc8-45a9-af53-34ced83aee15
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1070659432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1070659432
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.987888969
Short name T45
Test name
Test status
Simulation time 29206564 ps
CPU time 0.38 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:26:29 PM PDT 24
Peak memory 145444 kb
Host smart-24b2c8d0-e843-495e-9c31-250aebae9e03
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=987888969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.987888969
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3987939017
Short name T55
Test name
Test status
Simulation time 29685523 ps
CPU time 0.44 seconds
Started Aug 12 04:22:17 PM PDT 24
Finished Aug 12 04:22:18 PM PDT 24
Peak memory 144304 kb
Host smart-b6b9dd07-7dd4-44aa-bbea-3cf659189d46
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3987939017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3987939017
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3303728904
Short name T42
Test name
Test status
Simulation time 30917899 ps
CPU time 0.4 seconds
Started Aug 12 04:26:56 PM PDT 24
Finished Aug 12 04:26:57 PM PDT 24
Peak memory 145156 kb
Host smart-b2ec1dc2-8aea-4335-ab9f-8da2067998ca
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3303728904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3303728904
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1992296998
Short name T51
Test name
Test status
Simulation time 30625884 ps
CPU time 0.39 seconds
Started Aug 12 04:22:18 PM PDT 24
Finished Aug 12 04:22:19 PM PDT 24
Peak memory 144664 kb
Host smart-9a34d191-3817-4963-aa92-8bbdc99dfba7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1992296998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1992296998
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1298750782
Short name T53
Test name
Test status
Simulation time 29727321 ps
CPU time 0.4 seconds
Started Aug 12 04:27:50 PM PDT 24
Finished Aug 12 04:27:50 PM PDT 24
Peak memory 145160 kb
Host smart-05b3fcc6-7a4a-43d3-b90d-d545895149da
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1298750782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1298750782
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2016693092
Short name T43
Test name
Test status
Simulation time 29539214 ps
CPU time 0.41 seconds
Started Aug 12 04:22:31 PM PDT 24
Finished Aug 12 04:22:31 PM PDT 24
Peak memory 145036 kb
Host smart-f630ce07-f102-4612-85ac-edd7cf3932e7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2016693092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2016693092
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2061249789
Short name T44
Test name
Test status
Simulation time 30436898 ps
CPU time 0.42 seconds
Started Aug 12 04:23:04 PM PDT 24
Finished Aug 12 04:23:05 PM PDT 24
Peak memory 145172 kb
Host smart-0448d786-2e0d-4177-9a9f-3c17f7c6de61
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2061249789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2061249789
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3207964035
Short name T54
Test name
Test status
Simulation time 29849997 ps
CPU time 0.39 seconds
Started Aug 12 04:22:19 PM PDT 24
Finished Aug 12 04:22:19 PM PDT 24
Peak memory 145040 kb
Host smart-c7dc2fa7-c529-4dd2-8f89-5e81ad1d5c92
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3207964035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3207964035
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3782518284
Short name T46
Test name
Test status
Simulation time 31202555 ps
CPU time 0.43 seconds
Started Aug 12 04:22:46 PM PDT 24
Finished Aug 12 04:22:47 PM PDT 24
Peak memory 145152 kb
Host smart-8c54951b-228c-4534-897e-c835f413b7cb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3782518284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3782518284
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3001775701
Short name T47
Test name
Test status
Simulation time 31699709 ps
CPU time 0.44 seconds
Started Aug 12 04:26:31 PM PDT 24
Finished Aug 12 04:26:32 PM PDT 24
Peak memory 144400 kb
Host smart-22a82d59-79f9-41d4-971d-f707ab7af3a5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3001775701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3001775701
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3754189832
Short name T24
Test name
Test status
Simulation time 30032336 ps
CPU time 0.42 seconds
Started Aug 12 04:22:20 PM PDT 24
Finished Aug 12 04:22:21 PM PDT 24
Peak memory 145136 kb
Host smart-e99e92a3-c242-40c5-9192-75056c883485
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3754189832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3754189832
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1198003759
Short name T58
Test name
Test status
Simulation time 29154721 ps
CPU time 0.42 seconds
Started Aug 12 04:22:16 PM PDT 24
Finished Aug 12 04:22:17 PM PDT 24
Peak memory 144024 kb
Host smart-4daac45e-fe1d-4e7a-8a28-189ae4a735f9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1198003759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1198003759
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.314042458
Short name T56
Test name
Test status
Simulation time 28932056 ps
CPU time 0.42 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:26:26 PM PDT 24
Peak memory 145344 kb
Host smart-fa6b0524-84d5-4fad-aa5b-82d55eba1365
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=314042458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.314042458
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1157657445
Short name T64
Test name
Test status
Simulation time 9614276 ps
CPU time 0.38 seconds
Started Aug 12 04:26:56 PM PDT 24
Finished Aug 12 04:26:57 PM PDT 24
Peak memory 145416 kb
Host smart-d03512d9-8f32-4de8-9216-7752ee33910b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1157657445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1157657445
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1738680190
Short name T27
Test name
Test status
Simulation time 9134029 ps
CPU time 0.4 seconds
Started Aug 12 04:22:44 PM PDT 24
Finished Aug 12 04:22:44 PM PDT 24
Peak memory 145332 kb
Host smart-cb1b1f69-4064-4192-91d3-fe9b128589f3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1738680190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1738680190
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.593614833
Short name T30
Test name
Test status
Simulation time 9697998 ps
CPU time 0.4 seconds
Started Aug 12 04:22:53 PM PDT 24
Finished Aug 12 04:22:53 PM PDT 24
Peak memory 145460 kb
Host smart-77f0fa11-7ed6-4595-abbc-e9766903c8a3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=593614833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.593614833
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.28193967
Short name T66
Test name
Test status
Simulation time 8344269 ps
CPU time 0.41 seconds
Started Aug 12 04:22:35 PM PDT 24
Finished Aug 12 04:22:36 PM PDT 24
Peak memory 145640 kb
Host smart-48509313-d583-4cea-848f-8e966c24eae2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=28193967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.28193967
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.4220744521
Short name T62
Test name
Test status
Simulation time 8228390 ps
CPU time 0.46 seconds
Started Aug 12 04:26:24 PM PDT 24
Finished Aug 12 04:26:25 PM PDT 24
Peak memory 145680 kb
Host smart-aabcd727-3e74-4acb-bfac-661deff3ef49
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4220744521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4220744521
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3909933928
Short name T35
Test name
Test status
Simulation time 8724108 ps
CPU time 0.38 seconds
Started Aug 12 04:24:07 PM PDT 24
Finished Aug 12 04:24:07 PM PDT 24
Peak memory 145412 kb
Host smart-7aeb275c-f46b-4755-8092-4322c5f840b0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3909933928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3909933928
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.4043278396
Short name T29
Test name
Test status
Simulation time 9140269 ps
CPU time 0.38 seconds
Started Aug 12 04:22:21 PM PDT 24
Finished Aug 12 04:22:21 PM PDT 24
Peak memory 145492 kb
Host smart-c6cae73f-4d89-4c52-8c2e-ef450bbe5abe
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4043278396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.4043278396
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1877606767
Short name T38
Test name
Test status
Simulation time 8681170 ps
CPU time 0.41 seconds
Started Aug 12 04:26:53 PM PDT 24
Finished Aug 12 04:26:54 PM PDT 24
Peak memory 146332 kb
Host smart-58827614-4a6e-47ca-bfe1-800f7fa6b99c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1877606767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1877606767
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.222704224
Short name T26
Test name
Test status
Simulation time 10177346 ps
CPU time 0.44 seconds
Started Aug 12 04:26:56 PM PDT 24
Finished Aug 12 04:26:57 PM PDT 24
Peak memory 145296 kb
Host smart-08f9af7c-d3d9-411e-b649-084cf029ee74
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=222704224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.222704224
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2289334952
Short name T34
Test name
Test status
Simulation time 9946746 ps
CPU time 0.38 seconds
Started Aug 12 04:21:48 PM PDT 24
Finished Aug 12 04:21:49 PM PDT 24
Peak memory 145476 kb
Host smart-4d024ba2-8e49-403a-8552-66d453da8d46
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2289334952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2289334952
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3993363172
Short name T28
Test name
Test status
Simulation time 9006356 ps
CPU time 0.36 seconds
Started Aug 12 04:26:24 PM PDT 24
Finished Aug 12 04:26:25 PM PDT 24
Peak memory 145272 kb
Host smart-97b709a6-fb23-46ee-b484-738175de2c6a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3993363172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3993363172
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1472301656
Short name T31
Test name
Test status
Simulation time 8697781 ps
CPU time 0.4 seconds
Started Aug 12 04:21:29 PM PDT 24
Finished Aug 12 04:21:30 PM PDT 24
Peak memory 144304 kb
Host smart-c2d7b482-afb7-4991-b45f-2663a7adf6bc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1472301656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1472301656
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1984382553
Short name T25
Test name
Test status
Simulation time 8971461 ps
CPU time 0.39 seconds
Started Aug 12 04:22:10 PM PDT 24
Finished Aug 12 04:22:11 PM PDT 24
Peak memory 145460 kb
Host smart-1558a267-efbd-4083-9584-810c09086297
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1984382553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1984382553
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3444918175
Short name T10
Test name
Test status
Simulation time 8895263 ps
CPU time 0.4 seconds
Started Aug 12 04:22:36 PM PDT 24
Finished Aug 12 04:22:36 PM PDT 24
Peak memory 145508 kb
Host smart-c1285609-f2fd-40a7-b471-7fe1867ffd63
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3444918175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3444918175
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2597768067
Short name T63
Test name
Test status
Simulation time 8531276 ps
CPU time 0.39 seconds
Started Aug 12 04:23:01 PM PDT 24
Finished Aug 12 04:23:01 PM PDT 24
Peak memory 145468 kb
Host smart-234c67db-1722-4150-a7f6-312bffa376c3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2597768067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2597768067
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.144703460
Short name T36
Test name
Test status
Simulation time 9301126 ps
CPU time 0.38 seconds
Started Aug 12 04:21:52 PM PDT 24
Finished Aug 12 04:21:52 PM PDT 24
Peak memory 145516 kb
Host smart-7630e41f-b512-47b4-ad80-df144798c10a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=144703460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.144703460
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3009096439
Short name T65
Test name
Test status
Simulation time 9539391 ps
CPU time 0.43 seconds
Started Aug 12 04:27:34 PM PDT 24
Finished Aug 12 04:27:35 PM PDT 24
Peak memory 143856 kb
Host smart-b8f19783-fcd1-4f55-94f9-22c49424ad44
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3009096439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3009096439
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.759459708
Short name T37
Test name
Test status
Simulation time 8615802 ps
CPU time 0.38 seconds
Started Aug 12 04:26:32 PM PDT 24
Finished Aug 12 04:26:33 PM PDT 24
Peak memory 145280 kb
Host smart-4c57774d-d8b9-474a-85c1-d2e8b8295577
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=759459708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.759459708
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.999311508
Short name T61
Test name
Test status
Simulation time 9257628 ps
CPU time 0.39 seconds
Started Aug 12 04:23:04 PM PDT 24
Finished Aug 12 04:23:04 PM PDT 24
Peak memory 145424 kb
Host smart-4d6e17bc-711b-4d83-969a-c7791c3bd5fd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=999311508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.999311508
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1632218583
Short name T6
Test name
Test status
Simulation time 25311278 ps
CPU time 0.42 seconds
Started Aug 12 06:18:27 PM PDT 24
Finished Aug 12 06:18:27 PM PDT 24
Peak memory 145600 kb
Host smart-52e2c7c7-b728-4b2e-ac21-1839cf0cb107
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1632218583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1632218583
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1405036065
Short name T32
Test name
Test status
Simulation time 28582123 ps
CPU time 0.39 seconds
Started Aug 12 06:18:26 PM PDT 24
Finished Aug 12 06:18:27 PM PDT 24
Peak memory 145612 kb
Host smart-3feeb2fa-cf59-4e56-98b9-f734ea186d22
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1405036065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1405036065
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.492291771
Short name T77
Test name
Test status
Simulation time 26739776 ps
CPU time 0.4 seconds
Started Aug 12 06:18:36 PM PDT 24
Finished Aug 12 06:18:36 PM PDT 24
Peak memory 145588 kb
Host smart-8901dffa-467f-4f93-8143-5d55a5c5efab
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=492291771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.492291771
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2300071486
Short name T76
Test name
Test status
Simulation time 29226038 ps
CPU time 0.43 seconds
Started Aug 12 06:18:34 PM PDT 24
Finished Aug 12 06:18:34 PM PDT 24
Peak memory 145604 kb
Host smart-8704fe15-4cee-4b5c-b37c-0833fc5f8f41
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2300071486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2300071486
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2755920202
Short name T75
Test name
Test status
Simulation time 26783456 ps
CPU time 0.39 seconds
Started Aug 12 06:18:33 PM PDT 24
Finished Aug 12 06:18:34 PM PDT 24
Peak memory 145620 kb
Host smart-f238999f-7098-45f6-be69-8f7b4b3bcb84
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2755920202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2755920202
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1278266218
Short name T68
Test name
Test status
Simulation time 26957372 ps
CPU time 0.41 seconds
Started Aug 12 06:18:36 PM PDT 24
Finished Aug 12 06:18:36 PM PDT 24
Peak memory 145592 kb
Host smart-8cb5715c-b430-4b31-98ac-c9951c05818b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1278266218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1278266218
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3350795946
Short name T69
Test name
Test status
Simulation time 28382490 ps
CPU time 0.44 seconds
Started Aug 12 06:18:32 PM PDT 24
Finished Aug 12 06:18:32 PM PDT 24
Peak memory 145608 kb
Host smart-ad5dfe79-6298-41c5-914e-0032f7ef796c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3350795946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3350795946
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.942778567
Short name T70
Test name
Test status
Simulation time 26194600 ps
CPU time 0.4 seconds
Started Aug 12 06:18:33 PM PDT 24
Finished Aug 12 06:18:33 PM PDT 24
Peak memory 145592 kb
Host smart-95cdceb2-971e-42ae-a2a9-fe48e8a1325b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=942778567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.942778567
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1657623518
Short name T67
Test name
Test status
Simulation time 28478529 ps
CPU time 0.39 seconds
Started Aug 12 06:18:33 PM PDT 24
Finished Aug 12 06:18:33 PM PDT 24
Peak memory 145592 kb
Host smart-bfe8fa2b-6634-4477-8262-c48327f49dc9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1657623518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1657623518
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.299073624
Short name T72
Test name
Test status
Simulation time 25813749 ps
CPU time 0.41 seconds
Started Aug 12 06:18:31 PM PDT 24
Finished Aug 12 06:18:32 PM PDT 24
Peak memory 145584 kb
Host smart-af8e8034-0465-4cbc-aa9a-a5165b5e50dc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=299073624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.299073624
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3774966511
Short name T33
Test name
Test status
Simulation time 28648086 ps
CPU time 0.41 seconds
Started Aug 12 06:18:33 PM PDT 24
Finished Aug 12 06:18:33 PM PDT 24
Peak memory 145592 kb
Host smart-3c5f1b8b-f4c7-4f31-8a83-e0fc0f6eee56
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3774966511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3774966511
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.530909700
Short name T4
Test name
Test status
Simulation time 27935902 ps
CPU time 0.41 seconds
Started Aug 12 06:18:25 PM PDT 24
Finished Aug 12 06:18:26 PM PDT 24
Peak memory 145596 kb
Host smart-42031393-0889-4db3-b5b7-039b095e28dd
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=530909700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.530909700
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.251678646
Short name T73
Test name
Test status
Simulation time 26641273 ps
CPU time 0.4 seconds
Started Aug 12 06:18:36 PM PDT 24
Finished Aug 12 06:18:36 PM PDT 24
Peak memory 145588 kb
Host smart-7557d88b-b1af-47a2-9310-302ec6aa36be
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=251678646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.251678646
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3167009402
Short name T71
Test name
Test status
Simulation time 27452354 ps
CPU time 0.38 seconds
Started Aug 12 06:18:33 PM PDT 24
Finished Aug 12 06:18:34 PM PDT 24
Peak memory 145608 kb
Host smart-8a023e12-dea2-4ddb-a2f2-8a43c80ea04a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3167009402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3167009402
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.4260171727
Short name T74
Test name
Test status
Simulation time 28615937 ps
CPU time 0.4 seconds
Started Aug 12 06:18:32 PM PDT 24
Finished Aug 12 06:18:32 PM PDT 24
Peak memory 145620 kb
Host smart-eb0d88be-7989-4355-ad50-bc73e18ee920
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4260171727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.4260171727
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.502130163
Short name T78
Test name
Test status
Simulation time 26816604 ps
CPU time 0.39 seconds
Started Aug 12 06:18:33 PM PDT 24
Finished Aug 12 06:18:33 PM PDT 24
Peak memory 145628 kb
Host smart-1844da6c-dc6c-4d84-baff-9ee488da00a1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=502130163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.502130163
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.742962017
Short name T79
Test name
Test status
Simulation time 28505121 ps
CPU time 0.39 seconds
Started Aug 12 06:18:32 PM PDT 24
Finished Aug 12 06:18:32 PM PDT 24
Peak memory 145612 kb
Host smart-08caf839-dc2b-4237-af3a-41e483261d83
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=742962017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.742962017
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2522259633
Short name T80
Test name
Test status
Simulation time 29935057 ps
CPU time 0.38 seconds
Started Aug 12 06:18:31 PM PDT 24
Finished Aug 12 06:18:32 PM PDT 24
Peak memory 145524 kb
Host smart-df863e9d-403a-4fb9-8264-689c5e7eefe5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2522259633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2522259633
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3690720579
Short name T11
Test name
Test status
Simulation time 27013477 ps
CPU time 0.42 seconds
Started Aug 12 06:18:35 PM PDT 24
Finished Aug 12 06:18:36 PM PDT 24
Peak memory 145596 kb
Host smart-4f89519d-9d22-45e6-ac25-c8d13c19b397
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3690720579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3690720579
Directory /workspace/9.prim_sync_fatal_alert/latest
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