Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.02 89.02 100.00 100.00 95.83 95.83 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/1.prim_async_alert.1490750605
92.49 3.48 100.00 0.00 97.92 2.08 100.00 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/16.prim_sync_alert.3251965454
93.66 1.16 100.00 0.00 97.92 0.00 100.00 0.00 82.14 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.12339726
94.25 0.60 100.00 0.00 97.92 0.00 100.00 0.00 85.71 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/0.prim_async_alert.2874219553
94.85 0.60 100.00 0.00 97.92 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/19.prim_async_alert.1147881700
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2456353660

Tests that do not contribute to grading

Name
/workspace/coverage/default/10.prim_async_alert.1072707511
/workspace/coverage/default/11.prim_async_alert.2042279905
/workspace/coverage/default/12.prim_async_alert.3406131990
/workspace/coverage/default/13.prim_async_alert.3621989358
/workspace/coverage/default/14.prim_async_alert.2317563823
/workspace/coverage/default/15.prim_async_alert.1654387961
/workspace/coverage/default/16.prim_async_alert.3977680723
/workspace/coverage/default/17.prim_async_alert.130759145
/workspace/coverage/default/18.prim_async_alert.4262721916
/workspace/coverage/default/2.prim_async_alert.3286439968
/workspace/coverage/default/3.prim_async_alert.2857080457
/workspace/coverage/default/4.prim_async_alert.2002706128
/workspace/coverage/default/5.prim_async_alert.4067798554
/workspace/coverage/default/6.prim_async_alert.3207604614
/workspace/coverage/default/7.prim_async_alert.696348149
/workspace/coverage/default/8.prim_async_alert.259445706
/workspace/coverage/default/9.prim_async_alert.1134384353
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.650141420
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1104095045
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3128855537
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.102312669
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.329348920
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2886224932
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1296860417
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.779085700
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2833555043
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.408781247
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1700728079
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3238043465
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2454835576
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2196369088
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3860397609
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3531477349
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1893319723
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.512970360
/workspace/coverage/sync_alert/0.prim_sync_alert.908717535
/workspace/coverage/sync_alert/1.prim_sync_alert.157220354
/workspace/coverage/sync_alert/10.prim_sync_alert.1839560236
/workspace/coverage/sync_alert/11.prim_sync_alert.1131355085
/workspace/coverage/sync_alert/12.prim_sync_alert.1439495127
/workspace/coverage/sync_alert/13.prim_sync_alert.382886797
/workspace/coverage/sync_alert/14.prim_sync_alert.2769590921
/workspace/coverage/sync_alert/15.prim_sync_alert.2453290591
/workspace/coverage/sync_alert/17.prim_sync_alert.292600111
/workspace/coverage/sync_alert/18.prim_sync_alert.2315115987
/workspace/coverage/sync_alert/19.prim_sync_alert.2715075146
/workspace/coverage/sync_alert/2.prim_sync_alert.1655460247
/workspace/coverage/sync_alert/3.prim_sync_alert.269346120
/workspace/coverage/sync_alert/4.prim_sync_alert.4163799563
/workspace/coverage/sync_alert/5.prim_sync_alert.3301466316
/workspace/coverage/sync_alert/6.prim_sync_alert.3606828477
/workspace/coverage/sync_alert/7.prim_sync_alert.3552536043
/workspace/coverage/sync_alert/8.prim_sync_alert.2216064007
/workspace/coverage/sync_alert/9.prim_sync_alert.1156893594
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.817813180
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1399450616
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3820371937
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3728698965
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.246828027
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1344256246
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1550208697
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4208110153
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2272570077
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4286434564
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1843895597
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1834655040
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2226152596
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2956233548
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.559329698
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1400350895
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1923879110
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1777105948
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.176708833



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.prim_async_alert.1134384353 Aug 13 06:31:27 PM PDT 24 Aug 13 06:31:27 PM PDT 24 11213965 ps
T2 /workspace/coverage/default/17.prim_async_alert.130759145 Aug 13 06:31:32 PM PDT 24 Aug 13 06:31:33 PM PDT 24 11967227 ps
T3 /workspace/coverage/default/3.prim_async_alert.2857080457 Aug 13 06:31:30 PM PDT 24 Aug 13 06:31:30 PM PDT 24 10926503 ps
T6 /workspace/coverage/default/18.prim_async_alert.4262721916 Aug 13 06:31:27 PM PDT 24 Aug 13 06:31:27 PM PDT 24 11522102 ps
T8 /workspace/coverage/default/6.prim_async_alert.3207604614 Aug 13 06:31:30 PM PDT 24 Aug 13 06:31:30 PM PDT 24 11465584 ps
T7 /workspace/coverage/default/16.prim_async_alert.3977680723 Aug 13 06:31:25 PM PDT 24 Aug 13 06:31:25 PM PDT 24 12083139 ps
T14 /workspace/coverage/default/13.prim_async_alert.3621989358 Aug 13 06:31:29 PM PDT 24 Aug 13 06:31:30 PM PDT 24 11284295 ps
T15 /workspace/coverage/default/10.prim_async_alert.1072707511 Aug 13 06:31:47 PM PDT 24 Aug 13 06:31:48 PM PDT 24 10859494 ps
T11 /workspace/coverage/default/1.prim_async_alert.1490750605 Aug 13 06:31:20 PM PDT 24 Aug 13 06:31:20 PM PDT 24 12138584 ps
T16 /workspace/coverage/default/4.prim_async_alert.2002706128 Aug 13 06:31:29 PM PDT 24 Aug 13 06:31:30 PM PDT 24 12450006 ps
T19 /workspace/coverage/default/12.prim_async_alert.3406131990 Aug 13 06:31:44 PM PDT 24 Aug 13 06:31:44 PM PDT 24 11648615 ps
T17 /workspace/coverage/default/15.prim_async_alert.1654387961 Aug 13 06:31:38 PM PDT 24 Aug 13 06:31:38 PM PDT 24 10509833 ps
T18 /workspace/coverage/default/0.prim_async_alert.2874219553 Aug 13 06:31:28 PM PDT 24 Aug 13 06:31:29 PM PDT 24 11844850 ps
T12 /workspace/coverage/default/19.prim_async_alert.1147881700 Aug 13 06:31:29 PM PDT 24 Aug 13 06:31:30 PM PDT 24 12435122 ps
T20 /workspace/coverage/default/7.prim_async_alert.696348149 Aug 13 06:31:23 PM PDT 24 Aug 13 06:31:24 PM PDT 24 12111995 ps
T41 /workspace/coverage/default/5.prim_async_alert.4067798554 Aug 13 06:32:02 PM PDT 24 Aug 13 06:32:02 PM PDT 24 10712992 ps
T51 /workspace/coverage/default/14.prim_async_alert.2317563823 Aug 13 06:31:38 PM PDT 24 Aug 13 06:31:38 PM PDT 24 11065175 ps
T21 /workspace/coverage/default/8.prim_async_alert.259445706 Aug 13 06:31:33 PM PDT 24 Aug 13 06:31:34 PM PDT 24 10998959 ps
T22 /workspace/coverage/default/11.prim_async_alert.2042279905 Aug 13 06:31:26 PM PDT 24 Aug 13 06:31:26 PM PDT 24 10728357 ps
T23 /workspace/coverage/default/2.prim_async_alert.3286439968 Aug 13 06:31:29 PM PDT 24 Aug 13 06:31:29 PM PDT 24 10603403 ps
T42 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.512970360 Aug 13 06:32:40 PM PDT 24 Aug 13 06:32:41 PM PDT 24 31072721 ps
T43 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.779085700 Aug 13 06:32:55 PM PDT 24 Aug 13 06:32:56 PM PDT 24 29506879 ps
T13 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.12339726 Aug 13 06:32:50 PM PDT 24 Aug 13 06:32:51 PM PDT 24 28958691 ps
T44 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3860397609 Aug 13 06:32:41 PM PDT 24 Aug 13 06:32:41 PM PDT 24 29481394 ps
T45 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3531477349 Aug 13 06:32:42 PM PDT 24 Aug 13 06:32:43 PM PDT 24 28701622 ps
T46 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2454835576 Aug 13 06:32:41 PM PDT 24 Aug 13 06:32:41 PM PDT 24 31966128 ps
T47 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2886224932 Aug 13 06:32:45 PM PDT 24 Aug 13 06:32:46 PM PDT 24 30216299 ps
T48 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3238043465 Aug 13 06:32:41 PM PDT 24 Aug 13 06:32:41 PM PDT 24 29826869 ps
T49 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1700728079 Aug 13 06:32:42 PM PDT 24 Aug 13 06:32:43 PM PDT 24 30358676 ps
T50 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1893319723 Aug 13 06:32:46 PM PDT 24 Aug 13 06:32:47 PM PDT 24 30809647 ps
T52 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.650141420 Aug 13 06:32:44 PM PDT 24 Aug 13 06:32:44 PM PDT 24 33239468 ps
T53 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3128855537 Aug 13 06:32:41 PM PDT 24 Aug 13 06:32:41 PM PDT 24 27658681 ps
T54 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2196369088 Aug 13 06:32:51 PM PDT 24 Aug 13 06:32:52 PM PDT 24 30730280 ps
T55 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1104095045 Aug 13 06:32:41 PM PDT 24 Aug 13 06:32:41 PM PDT 24 29973279 ps
T56 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.102312669 Aug 13 06:32:41 PM PDT 24 Aug 13 06:32:41 PM PDT 24 31269815 ps
T57 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1296860417 Aug 13 06:32:41 PM PDT 24 Aug 13 06:32:42 PM PDT 24 30311407 ps
T58 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.408781247 Aug 13 06:32:50 PM PDT 24 Aug 13 06:32:50 PM PDT 24 30458612 ps
T59 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2833555043 Aug 13 06:32:48 PM PDT 24 Aug 13 06:32:48 PM PDT 24 32545374 ps
T60 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.329348920 Aug 13 06:32:51 PM PDT 24 Aug 13 06:32:52 PM PDT 24 30739440 ps
T24 /workspace/coverage/sync_alert/1.prim_sync_alert.157220354 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:25 PM PDT 24 8296698 ps
T34 /workspace/coverage/sync_alert/9.prim_sync_alert.1156893594 Aug 13 06:26:25 PM PDT 24 Aug 13 06:26:25 PM PDT 24 9950348 ps
T25 /workspace/coverage/sync_alert/14.prim_sync_alert.2769590921 Aug 13 06:26:26 PM PDT 24 Aug 13 06:26:26 PM PDT 24 8745639 ps
T35 /workspace/coverage/sync_alert/19.prim_sync_alert.2715075146 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:32 PM PDT 24 9998963 ps
T36 /workspace/coverage/sync_alert/3.prim_sync_alert.269346120 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:25 PM PDT 24 9685317 ps
T37 /workspace/coverage/sync_alert/11.prim_sync_alert.1131355085 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:24 PM PDT 24 9820087 ps
T38 /workspace/coverage/sync_alert/17.prim_sync_alert.292600111 Aug 13 06:26:27 PM PDT 24 Aug 13 06:26:27 PM PDT 24 8169838 ps
T39 /workspace/coverage/sync_alert/18.prim_sync_alert.2315115987 Aug 13 06:26:25 PM PDT 24 Aug 13 06:26:26 PM PDT 24 9255468 ps
T9 /workspace/coverage/sync_alert/16.prim_sync_alert.3251965454 Aug 13 06:26:25 PM PDT 24 Aug 13 06:26:26 PM PDT 24 9075240 ps
T40 /workspace/coverage/sync_alert/10.prim_sync_alert.1839560236 Aug 13 06:26:29 PM PDT 24 Aug 13 06:26:29 PM PDT 24 8928523 ps
T10 /workspace/coverage/sync_alert/6.prim_sync_alert.3606828477 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:24 PM PDT 24 9337487 ps
T26 /workspace/coverage/sync_alert/7.prim_sync_alert.3552536043 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:25 PM PDT 24 9782959 ps
T27 /workspace/coverage/sync_alert/12.prim_sync_alert.1439495127 Aug 13 06:26:22 PM PDT 24 Aug 13 06:26:23 PM PDT 24 9315457 ps
T61 /workspace/coverage/sync_alert/13.prim_sync_alert.382886797 Aug 13 06:26:27 PM PDT 24 Aug 13 06:26:28 PM PDT 24 8662551 ps
T62 /workspace/coverage/sync_alert/2.prim_sync_alert.1655460247 Aug 13 06:26:26 PM PDT 24 Aug 13 06:26:27 PM PDT 24 8504274 ps
T63 /workspace/coverage/sync_alert/4.prim_sync_alert.4163799563 Aug 13 06:26:26 PM PDT 24 Aug 13 06:26:27 PM PDT 24 8964479 ps
T28 /workspace/coverage/sync_alert/8.prim_sync_alert.2216064007 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:24 PM PDT 24 8811572 ps
T64 /workspace/coverage/sync_alert/0.prim_sync_alert.908717535 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:23 PM PDT 24 9606761 ps
T65 /workspace/coverage/sync_alert/15.prim_sync_alert.2453290591 Aug 13 06:26:26 PM PDT 24 Aug 13 06:26:27 PM PDT 24 8985570 ps
T66 /workspace/coverage/sync_alert/5.prim_sync_alert.3301466316 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:23 PM PDT 24 8282637 ps
T4 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1923879110 Aug 13 06:26:32 PM PDT 24 Aug 13 06:26:32 PM PDT 24 27545655 ps
T29 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2956233548 Aug 13 06:26:25 PM PDT 24 Aug 13 06:26:26 PM PDT 24 28261311 ps
T30 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2226152596 Aug 13 06:26:26 PM PDT 24 Aug 13 06:26:26 PM PDT 24 29101050 ps
T67 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4286434564 Aug 13 06:26:27 PM PDT 24 Aug 13 06:26:28 PM PDT 24 28754420 ps
T68 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3728698965 Aug 13 06:26:21 PM PDT 24 Aug 13 06:26:21 PM PDT 24 27681079 ps
T69 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1777105948 Aug 13 06:26:29 PM PDT 24 Aug 13 06:26:29 PM PDT 24 26323385 ps
T31 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3820371937 Aug 13 06:26:26 PM PDT 24 Aug 13 06:26:27 PM PDT 24 27196943 ps
T70 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1399450616 Aug 13 06:26:28 PM PDT 24 Aug 13 06:26:28 PM PDT 24 27085094 ps
T71 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1843895597 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:24 PM PDT 24 28614279 ps
T72 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.176708833 Aug 13 06:26:27 PM PDT 24 Aug 13 06:26:28 PM PDT 24 26672978 ps
T73 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1550208697 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:24 PM PDT 24 25332506 ps
T74 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1400350895 Aug 13 06:26:27 PM PDT 24 Aug 13 06:26:28 PM PDT 24 28547972 ps
T75 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1834655040 Aug 13 06:26:26 PM PDT 24 Aug 13 06:26:27 PM PDT 24 28527739 ps
T32 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.817813180 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:23 PM PDT 24 27132598 ps
T76 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4208110153 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:25 PM PDT 24 28431019 ps
T33 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.246828027 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:24 PM PDT 24 28193664 ps
T77 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1344256246 Aug 13 06:26:24 PM PDT 24 Aug 13 06:26:25 PM PDT 24 27691620 ps
T5 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2456353660 Aug 13 06:26:29 PM PDT 24 Aug 13 06:26:30 PM PDT 24 26878832 ps
T78 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.559329698 Aug 13 06:26:25 PM PDT 24 Aug 13 06:26:25 PM PDT 24 26773992 ps
T79 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2272570077 Aug 13 06:26:25 PM PDT 24 Aug 13 06:26:25 PM PDT 24 28096050 ps

Test location /workspace/coverage/default/1.prim_async_alert.1490750605
Short name T11
Test name
Test status
Simulation time 12138584 ps
CPU time 0.38 seconds
Started Aug 13 06:31:20 PM PDT 24
Finished Aug 13 06:31:20 PM PDT 24
Peak memory 145728 kb
Host smart-0e50b379-51f1-49d7-9624-268d2d41c8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490750605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1490750605
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3251965454
Short name T9
Test name
Test status
Simulation time 9075240 ps
CPU time 0.38 seconds
Started Aug 13 06:26:25 PM PDT 24
Finished Aug 13 06:26:26 PM PDT 24
Peak memory 145572 kb
Host smart-59276e34-8c60-4d7d-b548-1ae6bb7cd4a7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3251965454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3251965454
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.12339726
Short name T13
Test name
Test status
Simulation time 28958691 ps
CPU time 0.4 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:32:51 PM PDT 24
Peak memory 145344 kb
Host smart-af430aaf-dfc5-4c20-b387-f54d2d194e6e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=12339726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.12339726
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2874219553
Short name T18
Test name
Test status
Simulation time 11844850 ps
CPU time 0.39 seconds
Started Aug 13 06:31:28 PM PDT 24
Finished Aug 13 06:31:29 PM PDT 24
Peak memory 145852 kb
Host smart-be938bce-521e-45aa-bdc5-d117c8b3ee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874219553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2874219553
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1147881700
Short name T12
Test name
Test status
Simulation time 12435122 ps
CPU time 0.41 seconds
Started Aug 13 06:31:29 PM PDT 24
Finished Aug 13 06:31:30 PM PDT 24
Peak memory 145808 kb
Host smart-9fc60fff-f691-41b3-b802-9d89b03b21bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147881700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1147881700
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2456353660
Short name T5
Test name
Test status
Simulation time 26878832 ps
CPU time 0.39 seconds
Started Aug 13 06:26:29 PM PDT 24
Finished Aug 13 06:26:30 PM PDT 24
Peak memory 145624 kb
Host smart-d75b4cc8-95b0-4d69-8dfd-69794cedbb84
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2456353660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2456353660
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1072707511
Short name T15
Test name
Test status
Simulation time 10859494 ps
CPU time 0.4 seconds
Started Aug 13 06:31:47 PM PDT 24
Finished Aug 13 06:31:48 PM PDT 24
Peak memory 145820 kb
Host smart-73dd728a-6255-460e-9448-39165bddd45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072707511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1072707511
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2042279905
Short name T22
Test name
Test status
Simulation time 10728357 ps
CPU time 0.39 seconds
Started Aug 13 06:31:26 PM PDT 24
Finished Aug 13 06:31:26 PM PDT 24
Peak memory 145780 kb
Host smart-d0718a72-5bdc-4cdd-bf54-3b43d63ad1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042279905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2042279905
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3406131990
Short name T19
Test name
Test status
Simulation time 11648615 ps
CPU time 0.4 seconds
Started Aug 13 06:31:44 PM PDT 24
Finished Aug 13 06:31:44 PM PDT 24
Peak memory 145760 kb
Host smart-894a9c47-47fa-4e7b-b924-15be33e60473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406131990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3406131990
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3621989358
Short name T14
Test name
Test status
Simulation time 11284295 ps
CPU time 0.41 seconds
Started Aug 13 06:31:29 PM PDT 24
Finished Aug 13 06:31:30 PM PDT 24
Peak memory 145808 kb
Host smart-7fa93bd3-e893-42f0-87b4-5bb0b12c9367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621989358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3621989358
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2317563823
Short name T51
Test name
Test status
Simulation time 11065175 ps
CPU time 0.38 seconds
Started Aug 13 06:31:38 PM PDT 24
Finished Aug 13 06:31:38 PM PDT 24
Peak memory 145824 kb
Host smart-f9cfb46f-8a37-4207-ae5c-f64c0aaf43c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317563823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2317563823
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1654387961
Short name T17
Test name
Test status
Simulation time 10509833 ps
CPU time 0.44 seconds
Started Aug 13 06:31:38 PM PDT 24
Finished Aug 13 06:31:38 PM PDT 24
Peak memory 145816 kb
Host smart-5baf3e5a-5739-4073-bb11-3c14513ac080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654387961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1654387961
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3977680723
Short name T7
Test name
Test status
Simulation time 12083139 ps
CPU time 0.4 seconds
Started Aug 13 06:31:25 PM PDT 24
Finished Aug 13 06:31:25 PM PDT 24
Peak memory 145772 kb
Host smart-37271d01-6a88-4e6c-999d-d0b6abbec08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977680723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3977680723
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.130759145
Short name T2
Test name
Test status
Simulation time 11967227 ps
CPU time 0.38 seconds
Started Aug 13 06:31:32 PM PDT 24
Finished Aug 13 06:31:33 PM PDT 24
Peak memory 145812 kb
Host smart-1b021388-a34e-48d6-a79d-396b5b4e9254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130759145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.130759145
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.4262721916
Short name T6
Test name
Test status
Simulation time 11522102 ps
CPU time 0.39 seconds
Started Aug 13 06:31:27 PM PDT 24
Finished Aug 13 06:31:27 PM PDT 24
Peak memory 145700 kb
Host smart-e173d83e-be6e-43b6-b142-9787881454ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262721916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.4262721916
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3286439968
Short name T23
Test name
Test status
Simulation time 10603403 ps
CPU time 0.39 seconds
Started Aug 13 06:31:29 PM PDT 24
Finished Aug 13 06:31:29 PM PDT 24
Peak memory 145840 kb
Host smart-5b770feb-f252-49e1-92a6-466df6359b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286439968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3286439968
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2857080457
Short name T3
Test name
Test status
Simulation time 10926503 ps
CPU time 0.37 seconds
Started Aug 13 06:31:30 PM PDT 24
Finished Aug 13 06:31:30 PM PDT 24
Peak memory 145836 kb
Host smart-65de1c42-1f84-4ea3-be2e-d6b71f179cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857080457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2857080457
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2002706128
Short name T16
Test name
Test status
Simulation time 12450006 ps
CPU time 0.38 seconds
Started Aug 13 06:31:29 PM PDT 24
Finished Aug 13 06:31:30 PM PDT 24
Peak memory 145832 kb
Host smart-a4c8f74f-ea78-449d-92a3-bc8cd6741f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002706128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2002706128
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.4067798554
Short name T41
Test name
Test status
Simulation time 10712992 ps
CPU time 0.39 seconds
Started Aug 13 06:32:02 PM PDT 24
Finished Aug 13 06:32:02 PM PDT 24
Peak memory 145736 kb
Host smart-700062e1-ca84-4380-875c-4c1e7e4fe16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067798554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.4067798554
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3207604614
Short name T8
Test name
Test status
Simulation time 11465584 ps
CPU time 0.39 seconds
Started Aug 13 06:31:30 PM PDT 24
Finished Aug 13 06:31:30 PM PDT 24
Peak memory 145824 kb
Host smart-fb3184b0-2d01-4259-8ee4-12579537fc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207604614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3207604614
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.696348149
Short name T20
Test name
Test status
Simulation time 12111995 ps
CPU time 0.37 seconds
Started Aug 13 06:31:23 PM PDT 24
Finished Aug 13 06:31:24 PM PDT 24
Peak memory 145844 kb
Host smart-9b3c3fb4-9178-48f9-b550-84fad93b5cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696348149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.696348149
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.259445706
Short name T21
Test name
Test status
Simulation time 10998959 ps
CPU time 0.38 seconds
Started Aug 13 06:31:33 PM PDT 24
Finished Aug 13 06:31:34 PM PDT 24
Peak memory 145800 kb
Host smart-59e90c8b-8158-406f-af00-2f2d906169de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259445706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.259445706
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1134384353
Short name T1
Test name
Test status
Simulation time 11213965 ps
CPU time 0.39 seconds
Started Aug 13 06:31:27 PM PDT 24
Finished Aug 13 06:31:27 PM PDT 24
Peak memory 145740 kb
Host smart-b79c1791-6589-4d6d-8629-f8bf5a1a3da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134384353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1134384353
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.650141420
Short name T52
Test name
Test status
Simulation time 33239468 ps
CPU time 0.41 seconds
Started Aug 13 06:32:44 PM PDT 24
Finished Aug 13 06:32:44 PM PDT 24
Peak memory 145340 kb
Host smart-3c237f5e-e988-40b5-a93f-93af13edc7f7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=650141420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.650141420
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1104095045
Short name T55
Test name
Test status
Simulation time 29973279 ps
CPU time 0.41 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 145284 kb
Host smart-a48ebd8a-bb64-4505-8262-cab6a79159ce
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1104095045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1104095045
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3128855537
Short name T53
Test name
Test status
Simulation time 27658681 ps
CPU time 0.42 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 145320 kb
Host smart-9d645a9a-366d-4f4d-b7b9-87997c1cdbc7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3128855537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3128855537
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.102312669
Short name T56
Test name
Test status
Simulation time 31269815 ps
CPU time 0.43 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 145236 kb
Host smart-bb63adc2-71d3-47ea-848c-1ccbf5425108
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=102312669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.102312669
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.329348920
Short name T60
Test name
Test status
Simulation time 30739440 ps
CPU time 0.42 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:32:52 PM PDT 24
Peak memory 145304 kb
Host smart-435f4a30-e93c-44a1-8d5e-ae4ed5177224
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=329348920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.329348920
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2886224932
Short name T47
Test name
Test status
Simulation time 30216299 ps
CPU time 0.4 seconds
Started Aug 13 06:32:45 PM PDT 24
Finished Aug 13 06:32:46 PM PDT 24
Peak memory 145300 kb
Host smart-f3223394-6a51-44c6-8299-2d9a725417fd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2886224932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2886224932
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1296860417
Short name T57
Test name
Test status
Simulation time 30311407 ps
CPU time 0.43 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:32:42 PM PDT 24
Peak memory 145368 kb
Host smart-5e484ab3-8099-4be6-a2ab-59174a3346f0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1296860417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1296860417
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.779085700
Short name T43
Test name
Test status
Simulation time 29506879 ps
CPU time 0.41 seconds
Started Aug 13 06:32:55 PM PDT 24
Finished Aug 13 06:32:56 PM PDT 24
Peak memory 145328 kb
Host smart-899d5f26-0187-4ec0-8cd1-29d17c0daa03
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=779085700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.779085700
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2833555043
Short name T59
Test name
Test status
Simulation time 32545374 ps
CPU time 0.4 seconds
Started Aug 13 06:32:48 PM PDT 24
Finished Aug 13 06:32:48 PM PDT 24
Peak memory 145300 kb
Host smart-3656b398-9bc4-40c9-ac24-787a1b455b7c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2833555043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2833555043
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.408781247
Short name T58
Test name
Test status
Simulation time 30458612 ps
CPU time 0.41 seconds
Started Aug 13 06:32:50 PM PDT 24
Finished Aug 13 06:32:50 PM PDT 24
Peak memory 145312 kb
Host smart-47eda2b8-80c7-46ab-ac84-50fab675defa
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=408781247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.408781247
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1700728079
Short name T49
Test name
Test status
Simulation time 30358676 ps
CPU time 0.43 seconds
Started Aug 13 06:32:42 PM PDT 24
Finished Aug 13 06:32:43 PM PDT 24
Peak memory 145272 kb
Host smart-559ba714-dba6-4d68-be70-159f44563630
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1700728079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1700728079
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3238043465
Short name T48
Test name
Test status
Simulation time 29826869 ps
CPU time 0.41 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 145284 kb
Host smart-4e2f209b-b9c6-42ec-aa55-516206b51874
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3238043465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3238043465
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2454835576
Short name T46
Test name
Test status
Simulation time 31966128 ps
CPU time 0.42 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 145304 kb
Host smart-93f3fea7-2e49-469a-b4f0-261fb3d0f24c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2454835576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2454835576
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2196369088
Short name T54
Test name
Test status
Simulation time 30730280 ps
CPU time 0.41 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:32:52 PM PDT 24
Peak memory 145328 kb
Host smart-98ff54e7-b2ea-4ee3-8512-e33e190ff31a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2196369088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2196369088
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3860397609
Short name T44
Test name
Test status
Simulation time 29481394 ps
CPU time 0.42 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 145284 kb
Host smart-ea816765-3270-4574-94d5-c01897be3073
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3860397609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3860397609
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3531477349
Short name T45
Test name
Test status
Simulation time 28701622 ps
CPU time 0.41 seconds
Started Aug 13 06:32:42 PM PDT 24
Finished Aug 13 06:32:43 PM PDT 24
Peak memory 145284 kb
Host smart-bcf1e73d-97cb-4e69-afce-0bd4c0439e23
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3531477349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3531477349
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1893319723
Short name T50
Test name
Test status
Simulation time 30809647 ps
CPU time 0.4 seconds
Started Aug 13 06:32:46 PM PDT 24
Finished Aug 13 06:32:47 PM PDT 24
Peak memory 145304 kb
Host smart-5aaa05c5-57d5-402c-8540-ea63ccc742de
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1893319723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1893319723
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.512970360
Short name T42
Test name
Test status
Simulation time 31072721 ps
CPU time 0.42 seconds
Started Aug 13 06:32:40 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 145292 kb
Host smart-a7233d6b-a7f5-47c2-906b-91e44a45f80b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=512970360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.512970360
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.908717535
Short name T64
Test name
Test status
Simulation time 9606761 ps
CPU time 0.38 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:23 PM PDT 24
Peak memory 145624 kb
Host smart-83c43ec9-5793-432a-8b77-fda14c9f74fd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=908717535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.908717535
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.157220354
Short name T24
Test name
Test status
Simulation time 8296698 ps
CPU time 0.39 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:25 PM PDT 24
Peak memory 145584 kb
Host smart-612e66dd-4006-4ada-aa4b-2ae72a52cf9c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=157220354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.157220354
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1839560236
Short name T40
Test name
Test status
Simulation time 8928523 ps
CPU time 0.4 seconds
Started Aug 13 06:26:29 PM PDT 24
Finished Aug 13 06:26:29 PM PDT 24
Peak memory 145612 kb
Host smart-7ee1d711-89cf-4dd8-9873-d3ed1b9c7811
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1839560236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1839560236
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1131355085
Short name T37
Test name
Test status
Simulation time 9820087 ps
CPU time 0.38 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:24 PM PDT 24
Peak memory 145592 kb
Host smart-aded7bec-8056-45c8-ae96-8517dc223773
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1131355085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1131355085
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1439495127
Short name T27
Test name
Test status
Simulation time 9315457 ps
CPU time 0.37 seconds
Started Aug 13 06:26:22 PM PDT 24
Finished Aug 13 06:26:23 PM PDT 24
Peak memory 145628 kb
Host smart-2cd03ba4-28f9-4424-a339-6dc5cb0dd801
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1439495127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1439495127
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.382886797
Short name T61
Test name
Test status
Simulation time 8662551 ps
CPU time 0.39 seconds
Started Aug 13 06:26:27 PM PDT 24
Finished Aug 13 06:26:28 PM PDT 24
Peak memory 145556 kb
Host smart-3685d071-fb91-46ad-bfb4-6915f1ce45f7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=382886797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.382886797
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2769590921
Short name T25
Test name
Test status
Simulation time 8745639 ps
CPU time 0.39 seconds
Started Aug 13 06:26:26 PM PDT 24
Finished Aug 13 06:26:26 PM PDT 24
Peak memory 145576 kb
Host smart-96abb110-e999-47e0-86b7-b03855c73b32
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2769590921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2769590921
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2453290591
Short name T65
Test name
Test status
Simulation time 8985570 ps
CPU time 0.39 seconds
Started Aug 13 06:26:26 PM PDT 24
Finished Aug 13 06:26:27 PM PDT 24
Peak memory 145600 kb
Host smart-cb4e638f-12f6-4511-844f-4b2354a541bd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2453290591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2453290591
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.292600111
Short name T38
Test name
Test status
Simulation time 8169838 ps
CPU time 0.39 seconds
Started Aug 13 06:26:27 PM PDT 24
Finished Aug 13 06:26:27 PM PDT 24
Peak memory 145488 kb
Host smart-0387a50d-0a95-4eb3-a554-76aa8b82a826
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=292600111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.292600111
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2315115987
Short name T39
Test name
Test status
Simulation time 9255468 ps
CPU time 0.38 seconds
Started Aug 13 06:26:25 PM PDT 24
Finished Aug 13 06:26:26 PM PDT 24
Peak memory 145516 kb
Host smart-da07a10d-9cde-45ec-befa-f04c469622ad
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2315115987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2315115987
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2715075146
Short name T35
Test name
Test status
Simulation time 9998963 ps
CPU time 0.38 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:32 PM PDT 24
Peak memory 145612 kb
Host smart-d272d7be-fdd5-4bef-9255-322897217bf5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2715075146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2715075146
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1655460247
Short name T62
Test name
Test status
Simulation time 8504274 ps
CPU time 0.39 seconds
Started Aug 13 06:26:26 PM PDT 24
Finished Aug 13 06:26:27 PM PDT 24
Peak memory 145560 kb
Host smart-db769772-4868-4fa6-b651-1e3d466aa309
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1655460247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1655460247
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.269346120
Short name T36
Test name
Test status
Simulation time 9685317 ps
CPU time 0.38 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:25 PM PDT 24
Peak memory 145604 kb
Host smart-57b3e8ba-f202-4860-9ab2-a2cb5d215aea
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=269346120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.269346120
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.4163799563
Short name T63
Test name
Test status
Simulation time 8964479 ps
CPU time 0.38 seconds
Started Aug 13 06:26:26 PM PDT 24
Finished Aug 13 06:26:27 PM PDT 24
Peak memory 145600 kb
Host smart-d95f1de7-8a02-49f9-8d89-46043ec73084
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4163799563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.4163799563
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3301466316
Short name T66
Test name
Test status
Simulation time 8282637 ps
CPU time 0.43 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:23 PM PDT 24
Peak memory 145596 kb
Host smart-b441d14c-b29e-4f47-8f67-0f86c9687aca
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3301466316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3301466316
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3606828477
Short name T10
Test name
Test status
Simulation time 9337487 ps
CPU time 0.39 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:24 PM PDT 24
Peak memory 145604 kb
Host smart-2ed37690-a3c6-4380-8142-5d715f02da27
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3606828477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3606828477
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3552536043
Short name T26
Test name
Test status
Simulation time 9782959 ps
CPU time 0.38 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:25 PM PDT 24
Peak memory 145584 kb
Host smart-af9d5a12-73a1-472f-b883-a6e4fb826b55
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3552536043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3552536043
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2216064007
Short name T28
Test name
Test status
Simulation time 8811572 ps
CPU time 0.39 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:24 PM PDT 24
Peak memory 145600 kb
Host smart-36d9c20f-b558-4df1-a401-3cc03d84e44d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2216064007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2216064007
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1156893594
Short name T34
Test name
Test status
Simulation time 9950348 ps
CPU time 0.41 seconds
Started Aug 13 06:26:25 PM PDT 24
Finished Aug 13 06:26:25 PM PDT 24
Peak memory 145612 kb
Host smart-96862eac-84ac-4854-9596-e0dd5aafa710
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1156893594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1156893594
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.817813180
Short name T32
Test name
Test status
Simulation time 27132598 ps
CPU time 0.37 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:23 PM PDT 24
Peak memory 145628 kb
Host smart-9d905e90-6fec-4c5e-827c-c406d83e0ef7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=817813180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.817813180
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1399450616
Short name T70
Test name
Test status
Simulation time 27085094 ps
CPU time 0.4 seconds
Started Aug 13 06:26:28 PM PDT 24
Finished Aug 13 06:26:28 PM PDT 24
Peak memory 145632 kb
Host smart-b96cc98a-8469-45f3-9f89-78866d28a016
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1399450616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1399450616
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3820371937
Short name T31
Test name
Test status
Simulation time 27196943 ps
CPU time 0.41 seconds
Started Aug 13 06:26:26 PM PDT 24
Finished Aug 13 06:26:27 PM PDT 24
Peak memory 145596 kb
Host smart-c45a6b55-1647-4a19-a919-d8504e439796
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3820371937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3820371937
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3728698965
Short name T68
Test name
Test status
Simulation time 27681079 ps
CPU time 0.4 seconds
Started Aug 13 06:26:21 PM PDT 24
Finished Aug 13 06:26:21 PM PDT 24
Peak memory 145616 kb
Host smart-0d36a48f-5531-48cd-ad87-a590a4a74c77
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3728698965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3728698965
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.246828027
Short name T33
Test name
Test status
Simulation time 28193664 ps
CPU time 0.39 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:24 PM PDT 24
Peak memory 145600 kb
Host smart-12b37edf-2c9c-4b01-a8a2-e44ce71e3b9d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=246828027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.246828027
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1344256246
Short name T77
Test name
Test status
Simulation time 27691620 ps
CPU time 0.44 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:25 PM PDT 24
Peak memory 145532 kb
Host smart-20d99412-0965-4f62-8287-0daaebe95ae6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1344256246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1344256246
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1550208697
Short name T73
Test name
Test status
Simulation time 25332506 ps
CPU time 0.39 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:24 PM PDT 24
Peak memory 145628 kb
Host smart-bf8321fd-6296-4122-b5a4-989c8582f400
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1550208697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1550208697
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4208110153
Short name T76
Test name
Test status
Simulation time 28431019 ps
CPU time 0.43 seconds
Started Aug 13 06:26:24 PM PDT 24
Finished Aug 13 06:26:25 PM PDT 24
Peak memory 145616 kb
Host smart-f46d9e57-11f3-477f-a7e3-715c8844c311
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4208110153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.4208110153
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2272570077
Short name T79
Test name
Test status
Simulation time 28096050 ps
CPU time 0.39 seconds
Started Aug 13 06:26:25 PM PDT 24
Finished Aug 13 06:26:25 PM PDT 24
Peak memory 145588 kb
Host smart-4902d7d5-3219-4be2-8904-451f280ffd74
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2272570077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2272570077
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4286434564
Short name T67
Test name
Test status
Simulation time 28754420 ps
CPU time 0.41 seconds
Started Aug 13 06:26:27 PM PDT 24
Finished Aug 13 06:26:28 PM PDT 24
Peak memory 145632 kb
Host smart-0e425168-d5f2-4be0-a7a9-5f2fd86a2f73
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4286434564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.4286434564
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1843895597
Short name T71
Test name
Test status
Simulation time 28614279 ps
CPU time 0.4 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:24 PM PDT 24
Peak memory 145604 kb
Host smart-573e66c3-c9c5-43ad-b753-8f866c50e228
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1843895597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1843895597
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1834655040
Short name T75
Test name
Test status
Simulation time 28527739 ps
CPU time 0.4 seconds
Started Aug 13 06:26:26 PM PDT 24
Finished Aug 13 06:26:27 PM PDT 24
Peak memory 145492 kb
Host smart-59ad5069-f26f-4f66-bbdc-11cb399f0e34
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1834655040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1834655040
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2226152596
Short name T30
Test name
Test status
Simulation time 29101050 ps
CPU time 0.41 seconds
Started Aug 13 06:26:26 PM PDT 24
Finished Aug 13 06:26:26 PM PDT 24
Peak memory 145588 kb
Host smart-d0b7a540-c46a-49f7-8642-0975eaa35d98
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2226152596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2226152596
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2956233548
Short name T29
Test name
Test status
Simulation time 28261311 ps
CPU time 0.41 seconds
Started Aug 13 06:26:25 PM PDT 24
Finished Aug 13 06:26:26 PM PDT 24
Peak memory 145528 kb
Host smart-80b3bf43-cecf-4d7b-8625-f39593106231
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2956233548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2956233548
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.559329698
Short name T78
Test name
Test status
Simulation time 26773992 ps
CPU time 0.43 seconds
Started Aug 13 06:26:25 PM PDT 24
Finished Aug 13 06:26:25 PM PDT 24
Peak memory 145592 kb
Host smart-1937d665-c5ee-481b-9df4-154380436957
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=559329698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.559329698
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1400350895
Short name T74
Test name
Test status
Simulation time 28547972 ps
CPU time 0.41 seconds
Started Aug 13 06:26:27 PM PDT 24
Finished Aug 13 06:26:28 PM PDT 24
Peak memory 145636 kb
Host smart-fee17a4f-6755-4be9-8e92-1d8d4bf2207e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1400350895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1400350895
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1923879110
Short name T4
Test name
Test status
Simulation time 27545655 ps
CPU time 0.39 seconds
Started Aug 13 06:26:32 PM PDT 24
Finished Aug 13 06:26:32 PM PDT 24
Peak memory 145628 kb
Host smart-3f14b869-04cf-44b1-8e9d-38d6795a701a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1923879110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1923879110
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1777105948
Short name T69
Test name
Test status
Simulation time 26323385 ps
CPU time 0.42 seconds
Started Aug 13 06:26:29 PM PDT 24
Finished Aug 13 06:26:29 PM PDT 24
Peak memory 145632 kb
Host smart-63659163-e82b-47d1-8352-4b6ce5de7867
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1777105948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1777105948
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.176708833
Short name T72
Test name
Test status
Simulation time 26672978 ps
CPU time 0.4 seconds
Started Aug 13 06:26:27 PM PDT 24
Finished Aug 13 06:26:28 PM PDT 24
Peak memory 145616 kb
Host smart-23e319fb-b8e0-483c-b024-96e96cc51b0e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=176708833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.176708833
Directory /workspace/9.prim_sync_fatal_alert/latest
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