Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.08 88.08 100.00 100.00 93.75 93.75 96.43 96.43 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/15.prim_async_alert.667317550
91.20 3.13 100.00 0.00 93.75 0.00 96.43 0.00 82.14 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/14.prim_sync_alert.2806603700
93.31 2.11 100.00 0.00 95.83 2.08 100.00 3.57 82.14 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2587539142
93.90 0.60 100.00 0.00 95.83 0.00 100.00 0.00 85.71 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/0.prim_async_alert.3857155488
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2294252558
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.403741380
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/16.prim_sync_alert.1506622572

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_async_alert.828222727
/workspace/coverage/default/10.prim_async_alert.2341833477
/workspace/coverage/default/11.prim_async_alert.2660897673
/workspace/coverage/default/12.prim_async_alert.2568832843
/workspace/coverage/default/13.prim_async_alert.2583102687
/workspace/coverage/default/14.prim_async_alert.585908969
/workspace/coverage/default/16.prim_async_alert.2070991466
/workspace/coverage/default/17.prim_async_alert.92845001
/workspace/coverage/default/18.prim_async_alert.4134755207
/workspace/coverage/default/19.prim_async_alert.3073375721
/workspace/coverage/default/2.prim_async_alert.1558971879
/workspace/coverage/default/3.prim_async_alert.2026681321
/workspace/coverage/default/4.prim_async_alert.1582816344
/workspace/coverage/default/5.prim_async_alert.109428185
/workspace/coverage/default/6.prim_async_alert.2072715958
/workspace/coverage/default/7.prim_async_alert.2533264032
/workspace/coverage/default/8.prim_async_alert.3995235191
/workspace/coverage/default/9.prim_async_alert.2601402496
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1603605545
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2705927397
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.852799241
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3087609260
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.917080344
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3944520683
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3278378652
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.448144099
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3119853120
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4247459364
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2551663373
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2062378827
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1973330372
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2099193591
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.600964265
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2301231987
/workspace/coverage/sync_alert/0.prim_sync_alert.4096238842
/workspace/coverage/sync_alert/1.prim_sync_alert.1143425555
/workspace/coverage/sync_alert/10.prim_sync_alert.1913352463
/workspace/coverage/sync_alert/11.prim_sync_alert.3852127499
/workspace/coverage/sync_alert/12.prim_sync_alert.594939356
/workspace/coverage/sync_alert/13.prim_sync_alert.3140679596
/workspace/coverage/sync_alert/15.prim_sync_alert.3161108335
/workspace/coverage/sync_alert/17.prim_sync_alert.112918197
/workspace/coverage/sync_alert/18.prim_sync_alert.2071057073
/workspace/coverage/sync_alert/19.prim_sync_alert.4038558442
/workspace/coverage/sync_alert/2.prim_sync_alert.2590397729
/workspace/coverage/sync_alert/3.prim_sync_alert.2892068828
/workspace/coverage/sync_alert/4.prim_sync_alert.2893498939
/workspace/coverage/sync_alert/5.prim_sync_alert.2561640669
/workspace/coverage/sync_alert/6.prim_sync_alert.1312908854
/workspace/coverage/sync_alert/7.prim_sync_alert.1797490818
/workspace/coverage/sync_alert/8.prim_sync_alert.116543166
/workspace/coverage/sync_alert/9.prim_sync_alert.3871715514
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.265250972
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4032572097
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1988501128
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2183098087
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4233846687
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2207887930
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2563679381
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.33603829
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.520940668
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1686721034
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1305842973
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1899401331
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.436785238
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3453004542
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1448924218
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2795400258
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1832040906
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2368065751
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4277802575
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2300103532



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/15.prim_async_alert.667317550 Aug 14 04:19:45 PM PDT 24 Aug 14 04:19:46 PM PDT 24 10777855 ps
T2 /workspace/coverage/default/9.prim_async_alert.2601402496 Aug 14 04:19:41 PM PDT 24 Aug 14 04:19:41 PM PDT 24 10894018 ps
T3 /workspace/coverage/default/19.prim_async_alert.3073375721 Aug 14 04:19:43 PM PDT 24 Aug 14 04:19:44 PM PDT 24 11211145 ps
T7 /workspace/coverage/default/16.prim_async_alert.2070991466 Aug 14 04:25:05 PM PDT 24 Aug 14 04:25:05 PM PDT 24 11280141 ps
T14 /workspace/coverage/default/8.prim_async_alert.3995235191 Aug 14 04:20:49 PM PDT 24 Aug 14 04:20:50 PM PDT 24 11743776 ps
T6 /workspace/coverage/default/4.prim_async_alert.1582816344 Aug 14 04:20:49 PM PDT 24 Aug 14 04:20:50 PM PDT 24 11562017 ps
T16 /workspace/coverage/default/14.prim_async_alert.585908969 Aug 14 04:19:41 PM PDT 24 Aug 14 04:19:42 PM PDT 24 11047714 ps
T10 /workspace/coverage/default/0.prim_async_alert.3857155488 Aug 14 04:20:49 PM PDT 24 Aug 14 04:20:50 PM PDT 24 11723525 ps
T19 /workspace/coverage/default/17.prim_async_alert.92845001 Aug 14 04:19:37 PM PDT 24 Aug 14 04:19:37 PM PDT 24 11010903 ps
T20 /workspace/coverage/default/7.prim_async_alert.2533264032 Aug 14 04:19:40 PM PDT 24 Aug 14 04:19:40 PM PDT 24 11471589 ps
T11 /workspace/coverage/default/18.prim_async_alert.4134755207 Aug 14 04:19:43 PM PDT 24 Aug 14 04:19:44 PM PDT 24 11728651 ps
T21 /workspace/coverage/default/6.prim_async_alert.2072715958 Aug 14 04:19:41 PM PDT 24 Aug 14 04:19:41 PM PDT 24 11083572 ps
T22 /workspace/coverage/default/12.prim_async_alert.2568832843 Aug 14 04:19:41 PM PDT 24 Aug 14 04:19:41 PM PDT 24 10865536 ps
T12 /workspace/coverage/default/13.prim_async_alert.2583102687 Aug 14 04:19:41 PM PDT 24 Aug 14 04:19:42 PM PDT 24 11776430 ps
T17 /workspace/coverage/default/3.prim_async_alert.2026681321 Aug 14 04:19:33 PM PDT 24 Aug 14 04:19:34 PM PDT 24 10783816 ps
T49 /workspace/coverage/default/11.prim_async_alert.2660897673 Aug 14 04:19:43 PM PDT 24 Aug 14 04:19:44 PM PDT 24 11552908 ps
T50 /workspace/coverage/default/2.prim_async_alert.1558971879 Aug 14 04:20:49 PM PDT 24 Aug 14 04:20:50 PM PDT 24 11163948 ps
T23 /workspace/coverage/default/5.prim_async_alert.109428185 Aug 14 04:19:47 PM PDT 24 Aug 14 04:19:47 PM PDT 24 10584700 ps
T51 /workspace/coverage/default/10.prim_async_alert.2341833477 Aug 14 04:20:49 PM PDT 24 Aug 14 04:20:50 PM PDT 24 11194035 ps
T52 /workspace/coverage/default/1.prim_async_alert.828222727 Aug 14 04:23:07 PM PDT 24 Aug 14 04:23:08 PM PDT 24 11237203 ps
T44 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3944520683 Aug 14 04:28:39 PM PDT 24 Aug 14 04:28:45 PM PDT 24 29126330 ps
T45 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1973330372 Aug 14 04:27:23 PM PDT 24 Aug 14 04:27:23 PM PDT 24 29822942 ps
T18 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2062378827 Aug 14 04:27:25 PM PDT 24 Aug 14 04:27:26 PM PDT 24 28069221 ps
T15 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.600964265 Aug 14 04:27:32 PM PDT 24 Aug 14 04:27:33 PM PDT 24 31507075 ps
T24 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2551663373 Aug 14 04:28:40 PM PDT 24 Aug 14 04:28:41 PM PDT 24 30455470 ps
T25 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2301231987 Aug 14 04:27:32 PM PDT 24 Aug 14 04:27:32 PM PDT 24 32010614 ps
T46 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2587539142 Aug 14 04:27:44 PM PDT 24 Aug 14 04:27:50 PM PDT 24 30293354 ps
T47 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3119853120 Aug 14 04:27:43 PM PDT 24 Aug 14 04:27:44 PM PDT 24 30521491 ps
T13 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2294252558 Aug 14 04:27:36 PM PDT 24 Aug 14 04:27:36 PM PDT 24 30173612 ps
T48 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.852799241 Aug 14 04:27:22 PM PDT 24 Aug 14 04:27:23 PM PDT 24 29599651 ps
T53 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4247459364 Aug 14 04:27:43 PM PDT 24 Aug 14 04:27:43 PM PDT 24 30297779 ps
T26 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3087609260 Aug 14 04:27:29 PM PDT 24 Aug 14 04:27:30 PM PDT 24 29412414 ps
T54 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3278378652 Aug 14 04:28:35 PM PDT 24 Aug 14 04:28:35 PM PDT 24 27580243 ps
T55 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1603605545 Aug 14 04:28:32 PM PDT 24 Aug 14 04:28:33 PM PDT 24 31628978 ps
T27 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2099193591 Aug 14 04:28:14 PM PDT 24 Aug 14 04:28:15 PM PDT 24 28991932 ps
T56 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.917080344 Aug 14 04:27:26 PM PDT 24 Aug 14 04:27:26 PM PDT 24 29106976 ps
T28 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2705927397 Aug 14 04:27:30 PM PDT 24 Aug 14 04:27:31 PM PDT 24 29380558 ps
T4 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.403741380 Aug 14 04:27:20 PM PDT 24 Aug 14 04:27:21 PM PDT 24 31021038 ps
T57 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.448144099 Aug 14 04:27:35 PM PDT 24 Aug 14 04:27:35 PM PDT 24 30337254 ps
T29 /workspace/coverage/sync_alert/10.prim_sync_alert.1913352463 Aug 14 04:33:20 PM PDT 24 Aug 14 04:33:20 PM PDT 24 9309096 ps
T39 /workspace/coverage/sync_alert/8.prim_sync_alert.116543166 Aug 14 04:33:19 PM PDT 24 Aug 14 04:33:20 PM PDT 24 10005216 ps
T30 /workspace/coverage/sync_alert/14.prim_sync_alert.2806603700 Aug 14 04:33:28 PM PDT 24 Aug 14 04:33:29 PM PDT 24 10460777 ps
T31 /workspace/coverage/sync_alert/5.prim_sync_alert.2561640669 Aug 14 04:33:41 PM PDT 24 Aug 14 04:33:41 PM PDT 24 9970305 ps
T40 /workspace/coverage/sync_alert/2.prim_sync_alert.2590397729 Aug 14 04:33:26 PM PDT 24 Aug 14 04:33:26 PM PDT 24 9116761 ps
T41 /workspace/coverage/sync_alert/18.prim_sync_alert.2071057073 Aug 14 04:33:38 PM PDT 24 Aug 14 04:33:39 PM PDT 24 9315890 ps
T32 /workspace/coverage/sync_alert/6.prim_sync_alert.1312908854 Aug 14 04:33:53 PM PDT 24 Aug 14 04:33:53 PM PDT 24 8231905 ps
T33 /workspace/coverage/sync_alert/9.prim_sync_alert.3871715514 Aug 14 04:33:48 PM PDT 24 Aug 14 04:33:48 PM PDT 24 9789504 ps
T42 /workspace/coverage/sync_alert/15.prim_sync_alert.3161108335 Aug 14 04:33:23 PM PDT 24 Aug 14 04:33:23 PM PDT 24 8964798 ps
T43 /workspace/coverage/sync_alert/19.prim_sync_alert.4038558442 Aug 14 04:33:34 PM PDT 24 Aug 14 04:33:34 PM PDT 24 8394851 ps
T58 /workspace/coverage/sync_alert/3.prim_sync_alert.2892068828 Aug 14 04:33:37 PM PDT 24 Aug 14 04:33:38 PM PDT 24 8954391 ps
T59 /workspace/coverage/sync_alert/7.prim_sync_alert.1797490818 Aug 14 04:34:28 PM PDT 24 Aug 14 04:34:29 PM PDT 24 8541189 ps
T34 /workspace/coverage/sync_alert/12.prim_sync_alert.594939356 Aug 14 04:33:23 PM PDT 24 Aug 14 04:33:24 PM PDT 24 8635639 ps
T8 /workspace/coverage/sync_alert/16.prim_sync_alert.1506622572 Aug 14 04:33:58 PM PDT 24 Aug 14 04:33:58 PM PDT 24 8714777 ps
T9 /workspace/coverage/sync_alert/4.prim_sync_alert.2893498939 Aug 14 04:33:43 PM PDT 24 Aug 14 04:33:43 PM PDT 24 8112931 ps
T60 /workspace/coverage/sync_alert/1.prim_sync_alert.1143425555 Aug 14 04:33:19 PM PDT 24 Aug 14 04:33:19 PM PDT 24 8874222 ps
T35 /workspace/coverage/sync_alert/11.prim_sync_alert.3852127499 Aug 14 04:33:37 PM PDT 24 Aug 14 04:33:38 PM PDT 24 9622930 ps
T61 /workspace/coverage/sync_alert/0.prim_sync_alert.4096238842 Aug 14 04:34:28 PM PDT 24 Aug 14 04:34:29 PM PDT 24 9178668 ps
T36 /workspace/coverage/sync_alert/17.prim_sync_alert.112918197 Aug 14 04:34:01 PM PDT 24 Aug 14 04:34:01 PM PDT 24 8934389 ps
T37 /workspace/coverage/sync_alert/13.prim_sync_alert.3140679596 Aug 14 04:33:44 PM PDT 24 Aug 14 04:33:44 PM PDT 24 8394802 ps
T62 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4277802575 Aug 14 04:33:58 PM PDT 24 Aug 14 04:33:58 PM PDT 24 28694044 ps
T63 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.520940668 Aug 14 04:33:55 PM PDT 24 Aug 14 04:33:56 PM PDT 24 26783314 ps
T64 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1448924218 Aug 14 04:33:56 PM PDT 24 Aug 14 04:33:57 PM PDT 24 29285668 ps
T5 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4233846687 Aug 14 04:33:45 PM PDT 24 Aug 14 04:33:46 PM PDT 24 27505128 ps
T65 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2300103532 Aug 14 04:34:10 PM PDT 24 Aug 14 04:34:10 PM PDT 24 30137714 ps
T66 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1899401331 Aug 14 04:33:54 PM PDT 24 Aug 14 04:33:54 PM PDT 24 28011906 ps
T67 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2207887930 Aug 14 04:33:58 PM PDT 24 Aug 14 04:33:59 PM PDT 24 27777862 ps
T38 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1686721034 Aug 14 04:33:59 PM PDT 24 Aug 14 04:34:00 PM PDT 24 27859469 ps
T68 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3453004542 Aug 14 04:33:43 PM PDT 24 Aug 14 04:33:44 PM PDT 24 29110863 ps
T69 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2183098087 Aug 14 04:33:42 PM PDT 24 Aug 14 04:33:42 PM PDT 24 26082579 ps
T70 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2795400258 Aug 14 04:33:46 PM PDT 24 Aug 14 04:33:46 PM PDT 24 27655310 ps
T71 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.436785238 Aug 14 04:33:40 PM PDT 24 Aug 14 04:33:40 PM PDT 24 26479946 ps
T72 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1988501128 Aug 14 04:33:43 PM PDT 24 Aug 14 04:33:43 PM PDT 24 26836716 ps
T73 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.33603829 Aug 14 04:33:59 PM PDT 24 Aug 14 04:34:00 PM PDT 24 26471307 ps
T74 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1832040906 Aug 14 04:33:50 PM PDT 24 Aug 14 04:33:51 PM PDT 24 27294317 ps
T75 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2563679381 Aug 14 04:33:39 PM PDT 24 Aug 14 04:33:40 PM PDT 24 28000173 ps
T76 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.265250972 Aug 14 04:33:39 PM PDT 24 Aug 14 04:33:39 PM PDT 24 26853317 ps
T77 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1305842973 Aug 14 04:33:53 PM PDT 24 Aug 14 04:33:54 PM PDT 24 26858337 ps
T78 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2368065751 Aug 14 04:33:49 PM PDT 24 Aug 14 04:33:49 PM PDT 24 27341573 ps
T79 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4032572097 Aug 14 04:33:40 PM PDT 24 Aug 14 04:33:40 PM PDT 24 25976213 ps

Test location /workspace/coverage/default/15.prim_async_alert.667317550
Short name T1
Test name
Test status
Simulation time 10777855 ps
CPU time 0.42 seconds
Started Aug 14 04:19:45 PM PDT 24
Finished Aug 14 04:19:46 PM PDT 24
Peak memory 145648 kb
Host smart-1f09425d-c390-4a63-b6dd-78ee882d2683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667317550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.667317550
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2806603700
Short name T30
Test name
Test status
Simulation time 10460777 ps
CPU time 0.37 seconds
Started Aug 14 04:33:28 PM PDT 24
Finished Aug 14 04:33:29 PM PDT 24
Peak memory 145472 kb
Host smart-21c1e53c-180d-46f8-9c93-742509fb2450
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2806603700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2806603700
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2587539142
Short name T46
Test name
Test status
Simulation time 30293354 ps
CPU time 0.39 seconds
Started Aug 14 04:27:44 PM PDT 24
Finished Aug 14 04:27:50 PM PDT 24
Peak memory 145132 kb
Host smart-2b4f8b1e-ac2c-4cc4-8270-efdc2de1892e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2587539142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2587539142
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3857155488
Short name T10
Test name
Test status
Simulation time 11723525 ps
CPU time 0.39 seconds
Started Aug 14 04:20:49 PM PDT 24
Finished Aug 14 04:20:50 PM PDT 24
Peak memory 145368 kb
Host smart-c53fea9f-fd27-4113-917f-6bf9a0473575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857155488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3857155488
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2294252558
Short name T13
Test name
Test status
Simulation time 30173612 ps
CPU time 0.42 seconds
Started Aug 14 04:27:36 PM PDT 24
Finished Aug 14 04:27:36 PM PDT 24
Peak memory 145108 kb
Host smart-c72b0d1c-40b3-4ede-a2f1-f92dc31f75f3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2294252558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2294252558
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.403741380
Short name T4
Test name
Test status
Simulation time 31021038 ps
CPU time 0.39 seconds
Started Aug 14 04:27:20 PM PDT 24
Finished Aug 14 04:27:21 PM PDT 24
Peak memory 145176 kb
Host smart-282bcb82-4b5f-47e3-80fa-257ac7b8e68b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=403741380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.403741380
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1506622572
Short name T8
Test name
Test status
Simulation time 8714777 ps
CPU time 0.37 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:33:58 PM PDT 24
Peak memory 145496 kb
Host smart-026f2869-b66f-4d00-9065-a46c7cbe92e2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1506622572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1506622572
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.828222727
Short name T52
Test name
Test status
Simulation time 11237203 ps
CPU time 0.43 seconds
Started Aug 14 04:23:07 PM PDT 24
Finished Aug 14 04:23:08 PM PDT 24
Peak memory 145852 kb
Host smart-0924f58e-64e5-44e1-81ab-3fafc613535c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828222727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.828222727
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.2341833477
Short name T51
Test name
Test status
Simulation time 11194035 ps
CPU time 0.44 seconds
Started Aug 14 04:20:49 PM PDT 24
Finished Aug 14 04:20:50 PM PDT 24
Peak memory 143560 kb
Host smart-8bc731f8-a32b-40d0-979a-627dc7a2c82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341833477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2341833477
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2660897673
Short name T49
Test name
Test status
Simulation time 11552908 ps
CPU time 0.38 seconds
Started Aug 14 04:19:43 PM PDT 24
Finished Aug 14 04:19:44 PM PDT 24
Peak memory 145468 kb
Host smart-1b8ab8f9-4296-4eee-b488-54ee3f617b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660897673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2660897673
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2568832843
Short name T22
Test name
Test status
Simulation time 10865536 ps
CPU time 0.39 seconds
Started Aug 14 04:19:41 PM PDT 24
Finished Aug 14 04:19:41 PM PDT 24
Peak memory 145164 kb
Host smart-418c177e-b22a-4449-a159-47bed6dbaea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568832843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2568832843
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.2583102687
Short name T12
Test name
Test status
Simulation time 11776430 ps
CPU time 0.43 seconds
Started Aug 14 04:19:41 PM PDT 24
Finished Aug 14 04:19:42 PM PDT 24
Peak memory 145376 kb
Host smart-1b8f41e8-52d2-4e7c-9ef5-261c10c19bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583102687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2583102687
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.585908969
Short name T16
Test name
Test status
Simulation time 11047714 ps
CPU time 0.39 seconds
Started Aug 14 04:19:41 PM PDT 24
Finished Aug 14 04:19:42 PM PDT 24
Peak memory 145420 kb
Host smart-98628417-14e5-4905-8ab1-eda93b6dda6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585908969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.585908969
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2070991466
Short name T7
Test name
Test status
Simulation time 11280141 ps
CPU time 0.41 seconds
Started Aug 14 04:25:05 PM PDT 24
Finished Aug 14 04:25:05 PM PDT 24
Peak memory 145256 kb
Host smart-eeabed4a-28f8-4478-a9a0-67e11da9d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070991466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2070991466
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.92845001
Short name T19
Test name
Test status
Simulation time 11010903 ps
CPU time 0.4 seconds
Started Aug 14 04:19:37 PM PDT 24
Finished Aug 14 04:19:37 PM PDT 24
Peak memory 145276 kb
Host smart-d9f15cac-1b18-4525-ba51-63411ece8745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92845001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.92845001
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.4134755207
Short name T11
Test name
Test status
Simulation time 11728651 ps
CPU time 0.38 seconds
Started Aug 14 04:19:43 PM PDT 24
Finished Aug 14 04:19:44 PM PDT 24
Peak memory 145464 kb
Host smart-47689fce-1156-4c92-8fb9-d0e1526aa0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134755207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.4134755207
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3073375721
Short name T3
Test name
Test status
Simulation time 11211145 ps
CPU time 0.38 seconds
Started Aug 14 04:19:43 PM PDT 24
Finished Aug 14 04:19:44 PM PDT 24
Peak memory 145468 kb
Host smart-3280ebde-6779-4d06-87e6-60b7a0a32038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073375721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3073375721
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.1558971879
Short name T50
Test name
Test status
Simulation time 11163948 ps
CPU time 0.41 seconds
Started Aug 14 04:20:49 PM PDT 24
Finished Aug 14 04:20:50 PM PDT 24
Peak memory 144572 kb
Host smart-5ed13217-7d2c-4b97-b25d-a5a86eedd467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558971879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.1558971879
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.2026681321
Short name T17
Test name
Test status
Simulation time 10783816 ps
CPU time 0.49 seconds
Started Aug 14 04:19:33 PM PDT 24
Finished Aug 14 04:19:34 PM PDT 24
Peak memory 145144 kb
Host smart-2c6df627-8b33-48ef-9050-dd6186e5ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026681321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2026681321
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1582816344
Short name T6
Test name
Test status
Simulation time 11562017 ps
CPU time 0.38 seconds
Started Aug 14 04:20:49 PM PDT 24
Finished Aug 14 04:20:50 PM PDT 24
Peak memory 145196 kb
Host smart-3c997cd6-b7de-4951-af8f-587fb90321a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582816344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1582816344
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.109428185
Short name T23
Test name
Test status
Simulation time 10584700 ps
CPU time 0.37 seconds
Started Aug 14 04:19:47 PM PDT 24
Finished Aug 14 04:19:47 PM PDT 24
Peak memory 145648 kb
Host smart-3559fb11-fd4b-43d6-8cbf-af7f6dd58400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109428185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.109428185
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2072715958
Short name T21
Test name
Test status
Simulation time 11083572 ps
CPU time 0.39 seconds
Started Aug 14 04:19:41 PM PDT 24
Finished Aug 14 04:19:41 PM PDT 24
Peak memory 145164 kb
Host smart-72b14061-9bd0-4535-8a09-428d954ad994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072715958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2072715958
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2533264032
Short name T20
Test name
Test status
Simulation time 11471589 ps
CPU time 0.4 seconds
Started Aug 14 04:19:40 PM PDT 24
Finished Aug 14 04:19:40 PM PDT 24
Peak memory 145752 kb
Host smart-793fe51b-5f81-4551-9811-b05ef330686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533264032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2533264032
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3995235191
Short name T14
Test name
Test status
Simulation time 11743776 ps
CPU time 0.43 seconds
Started Aug 14 04:20:49 PM PDT 24
Finished Aug 14 04:20:50 PM PDT 24
Peak memory 143128 kb
Host smart-aca776b9-60dd-40ee-b70d-516780d9eb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995235191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3995235191
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2601402496
Short name T2
Test name
Test status
Simulation time 10894018 ps
CPU time 0.45 seconds
Started Aug 14 04:19:41 PM PDT 24
Finished Aug 14 04:19:41 PM PDT 24
Peak memory 145540 kb
Host smart-ca97f69b-8928-4763-8b33-b2beb6908ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601402496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2601402496
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1603605545
Short name T55
Test name
Test status
Simulation time 31628978 ps
CPU time 0.38 seconds
Started Aug 14 04:28:32 PM PDT 24
Finished Aug 14 04:28:33 PM PDT 24
Peak memory 145172 kb
Host smart-bd8d3779-f9e9-451d-b94f-e74b391459b2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1603605545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1603605545
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2705927397
Short name T28
Test name
Test status
Simulation time 29380558 ps
CPU time 0.39 seconds
Started Aug 14 04:27:30 PM PDT 24
Finished Aug 14 04:27:31 PM PDT 24
Peak memory 145180 kb
Host smart-2557706f-4e83-4f94-9301-53eea6017500
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2705927397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2705927397
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.852799241
Short name T48
Test name
Test status
Simulation time 29599651 ps
CPU time 0.38 seconds
Started Aug 14 04:27:22 PM PDT 24
Finished Aug 14 04:27:23 PM PDT 24
Peak memory 145192 kb
Host smart-b4848067-03ee-464f-8bf6-19b6545db620
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=852799241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.852799241
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3087609260
Short name T26
Test name
Test status
Simulation time 29412414 ps
CPU time 0.39 seconds
Started Aug 14 04:27:29 PM PDT 24
Finished Aug 14 04:27:30 PM PDT 24
Peak memory 145192 kb
Host smart-74596745-522f-4228-ad98-43c8c4bc2089
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3087609260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3087609260
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.917080344
Short name T56
Test name
Test status
Simulation time 29106976 ps
CPU time 0.4 seconds
Started Aug 14 04:27:26 PM PDT 24
Finished Aug 14 04:27:26 PM PDT 24
Peak memory 145164 kb
Host smart-994736df-e2cb-4543-8723-65e866c44776
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=917080344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.917080344
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3944520683
Short name T44
Test name
Test status
Simulation time 29126330 ps
CPU time 0.39 seconds
Started Aug 14 04:28:39 PM PDT 24
Finished Aug 14 04:28:45 PM PDT 24
Peak memory 145236 kb
Host smart-19f5bf7d-4198-45a8-91c8-c5922ac60f14
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3944520683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3944520683
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3278378652
Short name T54
Test name
Test status
Simulation time 27580243 ps
CPU time 0.4 seconds
Started Aug 14 04:28:35 PM PDT 24
Finished Aug 14 04:28:35 PM PDT 24
Peak memory 145228 kb
Host smart-17c43e4c-29c0-46f5-a441-040bf05f3a5d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3278378652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3278378652
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.448144099
Short name T57
Test name
Test status
Simulation time 30337254 ps
CPU time 0.39 seconds
Started Aug 14 04:27:35 PM PDT 24
Finished Aug 14 04:27:35 PM PDT 24
Peak memory 145200 kb
Host smart-7377b3e3-15ee-4046-8609-ff902e130d7c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=448144099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.448144099
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3119853120
Short name T47
Test name
Test status
Simulation time 30521491 ps
CPU time 0.41 seconds
Started Aug 14 04:27:43 PM PDT 24
Finished Aug 14 04:27:44 PM PDT 24
Peak memory 145180 kb
Host smart-fd640a15-7adb-4208-b6e1-8afb58f33157
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3119853120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3119853120
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4247459364
Short name T53
Test name
Test status
Simulation time 30297779 ps
CPU time 0.37 seconds
Started Aug 14 04:27:43 PM PDT 24
Finished Aug 14 04:27:43 PM PDT 24
Peak memory 145196 kb
Host smart-ea920039-c853-49a0-995a-9ad12b002065
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4247459364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.4247459364
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2551663373
Short name T24
Test name
Test status
Simulation time 30455470 ps
CPU time 0.39 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:41 PM PDT 24
Peak memory 145180 kb
Host smart-ac962b69-f8c5-4a97-88e7-5c2c49cf0491
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2551663373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2551663373
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2062378827
Short name T18
Test name
Test status
Simulation time 28069221 ps
CPU time 0.43 seconds
Started Aug 14 04:27:25 PM PDT 24
Finished Aug 14 04:27:26 PM PDT 24
Peak memory 145196 kb
Host smart-a22f50fd-27d7-49fa-8341-26fcae79a707
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2062378827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2062378827
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1973330372
Short name T45
Test name
Test status
Simulation time 29822942 ps
CPU time 0.39 seconds
Started Aug 14 04:27:23 PM PDT 24
Finished Aug 14 04:27:23 PM PDT 24
Peak memory 145196 kb
Host smart-907f55d3-7eeb-42f3-84a3-16a1018245ce
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1973330372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1973330372
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2099193591
Short name T27
Test name
Test status
Simulation time 28991932 ps
CPU time 0.43 seconds
Started Aug 14 04:28:14 PM PDT 24
Finished Aug 14 04:28:15 PM PDT 24
Peak memory 143964 kb
Host smart-bc3afd80-ef2d-443c-8b8f-bd2a00af2b95
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2099193591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2099193591
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.600964265
Short name T15
Test name
Test status
Simulation time 31507075 ps
CPU time 0.41 seconds
Started Aug 14 04:27:32 PM PDT 24
Finished Aug 14 04:27:33 PM PDT 24
Peak memory 145168 kb
Host smart-689dc40e-7664-42e8-99e3-2e6f95e4f469
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=600964265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.600964265
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2301231987
Short name T25
Test name
Test status
Simulation time 32010614 ps
CPU time 0.38 seconds
Started Aug 14 04:27:32 PM PDT 24
Finished Aug 14 04:27:32 PM PDT 24
Peak memory 145196 kb
Host smart-54b401c2-eb44-481a-883d-7592d13fc2d1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2301231987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2301231987
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.4096238842
Short name T61
Test name
Test status
Simulation time 9178668 ps
CPU time 0.46 seconds
Started Aug 14 04:34:28 PM PDT 24
Finished Aug 14 04:34:29 PM PDT 24
Peak memory 143128 kb
Host smart-3ba6f930-45f2-4869-ab61-0e79611d1f98
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4096238842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4096238842
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1143425555
Short name T60
Test name
Test status
Simulation time 8874222 ps
CPU time 0.39 seconds
Started Aug 14 04:33:19 PM PDT 24
Finished Aug 14 04:33:19 PM PDT 24
Peak memory 145588 kb
Host smart-4745d52a-020e-4175-b55b-779334d6b365
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1143425555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1143425555
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1913352463
Short name T29
Test name
Test status
Simulation time 9309096 ps
CPU time 0.37 seconds
Started Aug 14 04:33:20 PM PDT 24
Finished Aug 14 04:33:20 PM PDT 24
Peak memory 145476 kb
Host smart-eea13060-b7f9-47f3-809e-78ec97a5db62
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1913352463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1913352463
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3852127499
Short name T35
Test name
Test status
Simulation time 9622930 ps
CPU time 0.41 seconds
Started Aug 14 04:33:37 PM PDT 24
Finished Aug 14 04:33:38 PM PDT 24
Peak memory 145468 kb
Host smart-b3502931-e47e-4532-808d-31af2bd7466e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3852127499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3852127499
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.594939356
Short name T34
Test name
Test status
Simulation time 8635639 ps
CPU time 0.39 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 145480 kb
Host smart-842d6310-52c1-46d9-ae1c-f2129685be99
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=594939356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.594939356
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3140679596
Short name T37
Test name
Test status
Simulation time 8394802 ps
CPU time 0.37 seconds
Started Aug 14 04:33:44 PM PDT 24
Finished Aug 14 04:33:44 PM PDT 24
Peak memory 145496 kb
Host smart-8b8d52e9-8e3b-4f52-8d25-ff7a4d62f2d9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3140679596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3140679596
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3161108335
Short name T42
Test name
Test status
Simulation time 8964798 ps
CPU time 0.38 seconds
Started Aug 14 04:33:23 PM PDT 24
Finished Aug 14 04:33:23 PM PDT 24
Peak memory 145480 kb
Host smart-89358ac3-fc9a-4038-b6bd-17e1bd552c22
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3161108335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3161108335
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.112918197
Short name T36
Test name
Test status
Simulation time 8934389 ps
CPU time 0.4 seconds
Started Aug 14 04:34:01 PM PDT 24
Finished Aug 14 04:34:01 PM PDT 24
Peak memory 145408 kb
Host smart-e94affac-a45c-4576-8e93-0503282b651a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=112918197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.112918197
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2071057073
Short name T41
Test name
Test status
Simulation time 9315890 ps
CPU time 0.37 seconds
Started Aug 14 04:33:38 PM PDT 24
Finished Aug 14 04:33:39 PM PDT 24
Peak memory 145416 kb
Host smart-91b287fd-a826-494f-aad8-c7e2bf2d0264
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2071057073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2071057073
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.4038558442
Short name T43
Test name
Test status
Simulation time 8394851 ps
CPU time 0.37 seconds
Started Aug 14 04:33:34 PM PDT 24
Finished Aug 14 04:33:34 PM PDT 24
Peak memory 145480 kb
Host smart-a34be9e9-3648-4254-a4ec-9f81da765fae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4038558442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.4038558442
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2590397729
Short name T40
Test name
Test status
Simulation time 9116761 ps
CPU time 0.37 seconds
Started Aug 14 04:33:26 PM PDT 24
Finished Aug 14 04:33:26 PM PDT 24
Peak memory 145468 kb
Host smart-8cbb4130-6999-4154-8279-39983911ed7e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2590397729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2590397729
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2892068828
Short name T58
Test name
Test status
Simulation time 8954391 ps
CPU time 0.38 seconds
Started Aug 14 04:33:37 PM PDT 24
Finished Aug 14 04:33:38 PM PDT 24
Peak memory 145468 kb
Host smart-43ecc74a-bfa5-4e22-bca8-43461119fc65
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2892068828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2892068828
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2893498939
Short name T9
Test name
Test status
Simulation time 8112931 ps
CPU time 0.41 seconds
Started Aug 14 04:33:43 PM PDT 24
Finished Aug 14 04:33:43 PM PDT 24
Peak memory 145468 kb
Host smart-2e78f3ab-d09b-471e-8f62-0dad0658f268
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2893498939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2893498939
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2561640669
Short name T31
Test name
Test status
Simulation time 9970305 ps
CPU time 0.41 seconds
Started Aug 14 04:33:41 PM PDT 24
Finished Aug 14 04:33:41 PM PDT 24
Peak memory 145412 kb
Host smart-14ad2bc6-6723-4cf0-9781-0cdb49427b74
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2561640669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2561640669
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1312908854
Short name T32
Test name
Test status
Simulation time 8231905 ps
CPU time 0.38 seconds
Started Aug 14 04:33:53 PM PDT 24
Finished Aug 14 04:33:53 PM PDT 24
Peak memory 145468 kb
Host smart-6869f5c6-7033-4a11-8f82-dd3389e66083
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1312908854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1312908854
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1797490818
Short name T59
Test name
Test status
Simulation time 8541189 ps
CPU time 0.49 seconds
Started Aug 14 04:34:28 PM PDT 24
Finished Aug 14 04:34:29 PM PDT 24
Peak memory 143112 kb
Host smart-fb1db665-4a0e-4078-8f5c-462846ca01a8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1797490818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1797490818
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.116543166
Short name T39
Test name
Test status
Simulation time 10005216 ps
CPU time 0.37 seconds
Started Aug 14 04:33:19 PM PDT 24
Finished Aug 14 04:33:20 PM PDT 24
Peak memory 145492 kb
Host smart-529fee03-9b33-4d1e-ad32-d9611ff910cc
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=116543166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.116543166
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3871715514
Short name T33
Test name
Test status
Simulation time 9789504 ps
CPU time 0.39 seconds
Started Aug 14 04:33:48 PM PDT 24
Finished Aug 14 04:33:48 PM PDT 24
Peak memory 145448 kb
Host smart-45113fa9-0985-47c0-a443-22b46a548e1f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3871715514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3871715514
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.265250972
Short name T76
Test name
Test status
Simulation time 26853317 ps
CPU time 0.39 seconds
Started Aug 14 04:33:39 PM PDT 24
Finished Aug 14 04:33:39 PM PDT 24
Peak memory 145496 kb
Host smart-21365389-fab2-4969-b619-320d44ebed9e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=265250972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.265250972
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.4032572097
Short name T79
Test name
Test status
Simulation time 25976213 ps
CPU time 0.39 seconds
Started Aug 14 04:33:40 PM PDT 24
Finished Aug 14 04:33:40 PM PDT 24
Peak memory 145500 kb
Host smart-7411113f-3851-45e0-8c15-8a3c04ebdab7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4032572097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.4032572097
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1988501128
Short name T72
Test name
Test status
Simulation time 26836716 ps
CPU time 0.4 seconds
Started Aug 14 04:33:43 PM PDT 24
Finished Aug 14 04:33:43 PM PDT 24
Peak memory 145508 kb
Host smart-cf171bf3-f601-41e5-aecf-36c737f2bc0d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1988501128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1988501128
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2183098087
Short name T69
Test name
Test status
Simulation time 26082579 ps
CPU time 0.39 seconds
Started Aug 14 04:33:42 PM PDT 24
Finished Aug 14 04:33:42 PM PDT 24
Peak memory 145604 kb
Host smart-08b5f39c-7b12-4c13-9133-315798e4141b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2183098087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2183098087
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4233846687
Short name T5
Test name
Test status
Simulation time 27505128 ps
CPU time 0.4 seconds
Started Aug 14 04:33:45 PM PDT 24
Finished Aug 14 04:33:46 PM PDT 24
Peak memory 145584 kb
Host smart-1486685c-ba1f-4843-b827-5faba9049e81
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4233846687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4233846687
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2207887930
Short name T67
Test name
Test status
Simulation time 27777862 ps
CPU time 0.39 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:33:59 PM PDT 24
Peak memory 145604 kb
Host smart-f145f7b0-c2d4-4df3-96bc-bb642d03f687
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2207887930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2207887930
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2563679381
Short name T75
Test name
Test status
Simulation time 28000173 ps
CPU time 0.39 seconds
Started Aug 14 04:33:39 PM PDT 24
Finished Aug 14 04:33:40 PM PDT 24
Peak memory 145492 kb
Host smart-235187c0-02c7-4a05-94d0-3ee5bc878c3e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2563679381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2563679381
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.33603829
Short name T73
Test name
Test status
Simulation time 26471307 ps
CPU time 0.4 seconds
Started Aug 14 04:33:59 PM PDT 24
Finished Aug 14 04:34:00 PM PDT 24
Peak memory 145484 kb
Host smart-2d68a089-a349-4bea-99f8-145c8f2b8a1c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=33603829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.33603829
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.520940668
Short name T63
Test name
Test status
Simulation time 26783314 ps
CPU time 0.4 seconds
Started Aug 14 04:33:55 PM PDT 24
Finished Aug 14 04:33:56 PM PDT 24
Peak memory 145480 kb
Host smart-759fd99e-5a64-4eac-98f4-2258516c0f43
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=520940668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.520940668
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1686721034
Short name T38
Test name
Test status
Simulation time 27859469 ps
CPU time 0.39 seconds
Started Aug 14 04:33:59 PM PDT 24
Finished Aug 14 04:34:00 PM PDT 24
Peak memory 145508 kb
Host smart-732992e3-2098-4156-bc21-e54a94629aae
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1686721034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1686721034
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1305842973
Short name T77
Test name
Test status
Simulation time 26858337 ps
CPU time 0.39 seconds
Started Aug 14 04:33:53 PM PDT 24
Finished Aug 14 04:33:54 PM PDT 24
Peak memory 145604 kb
Host smart-2d584682-c922-4e34-a845-b9d74365aa69
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1305842973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1305842973
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1899401331
Short name T66
Test name
Test status
Simulation time 28011906 ps
CPU time 0.41 seconds
Started Aug 14 04:33:54 PM PDT 24
Finished Aug 14 04:33:54 PM PDT 24
Peak memory 145492 kb
Host smart-5ad6757a-3030-44dd-b660-06aa692e6231
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1899401331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1899401331
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.436785238
Short name T71
Test name
Test status
Simulation time 26479946 ps
CPU time 0.4 seconds
Started Aug 14 04:33:40 PM PDT 24
Finished Aug 14 04:33:40 PM PDT 24
Peak memory 145488 kb
Host smart-29e9ae21-45a7-4668-b58c-14a8b5601c14
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=436785238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.436785238
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3453004542
Short name T68
Test name
Test status
Simulation time 29110863 ps
CPU time 0.38 seconds
Started Aug 14 04:33:43 PM PDT 24
Finished Aug 14 04:33:44 PM PDT 24
Peak memory 145484 kb
Host smart-3639de6e-23fa-44a1-8e9a-23c1c5ef3b47
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3453004542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3453004542
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1448924218
Short name T64
Test name
Test status
Simulation time 29285668 ps
CPU time 0.41 seconds
Started Aug 14 04:33:56 PM PDT 24
Finished Aug 14 04:33:57 PM PDT 24
Peak memory 145500 kb
Host smart-ef469b50-166c-4fc6-8966-d238564670c7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1448924218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1448924218
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2795400258
Short name T70
Test name
Test status
Simulation time 27655310 ps
CPU time 0.38 seconds
Started Aug 14 04:33:46 PM PDT 24
Finished Aug 14 04:33:46 PM PDT 24
Peak memory 145516 kb
Host smart-16be252b-019a-48f9-ae22-3aadafb36912
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2795400258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2795400258
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1832040906
Short name T74
Test name
Test status
Simulation time 27294317 ps
CPU time 0.39 seconds
Started Aug 14 04:33:50 PM PDT 24
Finished Aug 14 04:33:51 PM PDT 24
Peak memory 145604 kb
Host smart-e9589467-469c-48cb-897e-1252e03e062f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1832040906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1832040906
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2368065751
Short name T78
Test name
Test status
Simulation time 27341573 ps
CPU time 0.4 seconds
Started Aug 14 04:33:49 PM PDT 24
Finished Aug 14 04:33:49 PM PDT 24
Peak memory 145556 kb
Host smart-62e307ff-2686-49ac-b1c3-57cd8108be66
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2368065751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2368065751
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4277802575
Short name T62
Test name
Test status
Simulation time 28694044 ps
CPU time 0.39 seconds
Started Aug 14 04:33:58 PM PDT 24
Finished Aug 14 04:33:58 PM PDT 24
Peak memory 145512 kb
Host smart-523e5e4a-6e48-4d06-a6d2-f48a7e974bb8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4277802575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.4277802575
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2300103532
Short name T65
Test name
Test status
Simulation time 30137714 ps
CPU time 0.39 seconds
Started Aug 14 04:34:10 PM PDT 24
Finished Aug 14 04:34:10 PM PDT 24
Peak memory 145500 kb
Host smart-bf0957f5-d01e-41ff-874e-623f318ff982
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2300103532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2300103532
Directory /workspace/9.prim_sync_fatal_alert/latest
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