Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.92 88.92 100.00 100.00 91.67 91.67 96.43 96.43 82.14 82.14 95.83 95.83 67.44 67.44 /workspace/coverage/default/11.prim_async_alert.1978620646
91.80 2.88 100.00 0.00 93.75 2.08 96.43 0.00 85.71 3.57 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/5.prim_sync_alert.2600240358
93.90 2.11 100.00 0.00 95.83 2.08 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3382873156
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/1.prim_sync_alert.3623097227
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/10.prim_sync_alert.1226294978
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2342235326

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2504946441
/workspace/coverage/default/1.prim_async_alert.1057987579
/workspace/coverage/default/10.prim_async_alert.1901475510
/workspace/coverage/default/12.prim_async_alert.3704669708
/workspace/coverage/default/13.prim_async_alert.523913752
/workspace/coverage/default/14.prim_async_alert.303328872
/workspace/coverage/default/15.prim_async_alert.1643475617
/workspace/coverage/default/16.prim_async_alert.54733366
/workspace/coverage/default/17.prim_async_alert.2128688402
/workspace/coverage/default/18.prim_async_alert.1838931023
/workspace/coverage/default/19.prim_async_alert.419563421
/workspace/coverage/default/2.prim_async_alert.3822147002
/workspace/coverage/default/3.prim_async_alert.4094017910
/workspace/coverage/default/4.prim_async_alert.3591076291
/workspace/coverage/default/5.prim_async_alert.1603926347
/workspace/coverage/default/6.prim_async_alert.1987118260
/workspace/coverage/default/7.prim_async_alert.660256127
/workspace/coverage/default/8.prim_async_alert.4126300808
/workspace/coverage/default/9.prim_async_alert.1930154500
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1657988201
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1257307057
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3441335607
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1729152453
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.171464537
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.644098757
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.548674647
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3906266411
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2131501738
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1419880734
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.761177625
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2043347481
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1497026067
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2172742441
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1043270937
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3382529090
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.104355021
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3201370403
/workspace/coverage/sync_alert/0.prim_sync_alert.3073019061
/workspace/coverage/sync_alert/11.prim_sync_alert.3368744345
/workspace/coverage/sync_alert/12.prim_sync_alert.3769640648
/workspace/coverage/sync_alert/13.prim_sync_alert.2906872443
/workspace/coverage/sync_alert/14.prim_sync_alert.673450528
/workspace/coverage/sync_alert/15.prim_sync_alert.177469659
/workspace/coverage/sync_alert/16.prim_sync_alert.2168932732
/workspace/coverage/sync_alert/17.prim_sync_alert.1807862191
/workspace/coverage/sync_alert/18.prim_sync_alert.3787792471
/workspace/coverage/sync_alert/19.prim_sync_alert.708623867
/workspace/coverage/sync_alert/2.prim_sync_alert.3883266355
/workspace/coverage/sync_alert/3.prim_sync_alert.921270776
/workspace/coverage/sync_alert/4.prim_sync_alert.2476857271
/workspace/coverage/sync_alert/6.prim_sync_alert.2151172711
/workspace/coverage/sync_alert/7.prim_sync_alert.722495102
/workspace/coverage/sync_alert/8.prim_sync_alert.3979498465
/workspace/coverage/sync_alert/9.prim_sync_alert.1038798106
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3521990308
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1789472963
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2985342293
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1058068603
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2232968174
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1678300620
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.687851508
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3336276624
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2144969592
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3755122260
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4085484422
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1221719954
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.289179530
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3213723450
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3003698856
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2004084778
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4194510646
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1192354269
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2360326097



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.prim_async_alert.4094017910 Aug 15 05:39:51 PM PDT 24 Aug 15 05:39:51 PM PDT 24 10939527 ps
T2 /workspace/coverage/default/6.prim_async_alert.1987118260 Aug 15 05:39:51 PM PDT 24 Aug 15 05:39:52 PM PDT 24 10867309 ps
T3 /workspace/coverage/default/14.prim_async_alert.303328872 Aug 15 05:39:32 PM PDT 24 Aug 15 05:39:33 PM PDT 24 11005900 ps
T9 /workspace/coverage/default/0.prim_async_alert.2504946441 Aug 15 05:39:56 PM PDT 24 Aug 15 05:39:56 PM PDT 24 11290052 ps
T7 /workspace/coverage/default/7.prim_async_alert.660256127 Aug 15 05:39:40 PM PDT 24 Aug 15 05:39:40 PM PDT 24 10857450 ps
T21 /workspace/coverage/default/16.prim_async_alert.54733366 Aug 15 05:39:49 PM PDT 24 Aug 15 05:39:50 PM PDT 24 11202077 ps
T14 /workspace/coverage/default/4.prim_async_alert.3591076291 Aug 15 05:39:49 PM PDT 24 Aug 15 05:39:50 PM PDT 24 12215941 ps
T23 /workspace/coverage/default/9.prim_async_alert.1930154500 Aug 15 05:39:55 PM PDT 24 Aug 15 05:39:55 PM PDT 24 11160596 ps
T24 /workspace/coverage/default/15.prim_async_alert.1643475617 Aug 15 05:39:47 PM PDT 24 Aug 15 05:39:47 PM PDT 24 11089034 ps
T18 /workspace/coverage/default/11.prim_async_alert.1978620646 Aug 15 05:39:55 PM PDT 24 Aug 15 05:39:55 PM PDT 24 10596959 ps
T8 /workspace/coverage/default/8.prim_async_alert.4126300808 Aug 15 05:39:34 PM PDT 24 Aug 15 05:39:34 PM PDT 24 11575296 ps
T25 /workspace/coverage/default/13.prim_async_alert.523913752 Aug 15 05:39:45 PM PDT 24 Aug 15 05:39:45 PM PDT 24 11622304 ps
T10 /workspace/coverage/default/18.prim_async_alert.1838931023 Aug 15 05:39:57 PM PDT 24 Aug 15 05:39:57 PM PDT 24 10750474 ps
T15 /workspace/coverage/default/10.prim_async_alert.1901475510 Aug 15 05:39:41 PM PDT 24 Aug 15 05:39:42 PM PDT 24 12001553 ps
T46 /workspace/coverage/default/17.prim_async_alert.2128688402 Aug 15 05:39:43 PM PDT 24 Aug 15 05:39:44 PM PDT 24 10996723 ps
T22 /workspace/coverage/default/19.prim_async_alert.419563421 Aug 15 05:39:46 PM PDT 24 Aug 15 05:39:46 PM PDT 24 11156149 ps
T47 /workspace/coverage/default/2.prim_async_alert.3822147002 Aug 15 05:39:52 PM PDT 24 Aug 15 05:39:53 PM PDT 24 11266523 ps
T16 /workspace/coverage/default/5.prim_async_alert.1603926347 Aug 15 05:39:49 PM PDT 24 Aug 15 05:39:50 PM PDT 24 12020711 ps
T48 /workspace/coverage/default/1.prim_async_alert.1057987579 Aug 15 05:39:51 PM PDT 24 Aug 15 05:39:52 PM PDT 24 11893274 ps
T49 /workspace/coverage/default/12.prim_async_alert.3704669708 Aug 15 05:39:48 PM PDT 24 Aug 15 05:39:48 PM PDT 24 11307878 ps
T39 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.171464537 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:51 PM PDT 24 30259762 ps
T40 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1497026067 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:51 PM PDT 24 28632171 ps
T41 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.548674647 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:06 PM PDT 24 30583674 ps
T42 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2172742441 Aug 15 05:50:00 PM PDT 24 Aug 15 05:50:01 PM PDT 24 29182488 ps
T43 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3441335607 Aug 15 05:50:04 PM PDT 24 Aug 15 05:50:04 PM PDT 24 28783661 ps
T19 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3382873156 Aug 15 05:50:00 PM PDT 24 Aug 15 05:50:01 PM PDT 24 32396236 ps
T44 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1729152453 Aug 15 05:49:48 PM PDT 24 Aug 15 05:49:48 PM PDT 24 30137321 ps
T45 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2131501738 Aug 15 05:50:00 PM PDT 24 Aug 15 05:50:00 PM PDT 24 30724091 ps
T37 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3201370403 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:06 PM PDT 24 29909027 ps
T20 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3382529090 Aug 15 05:49:48 PM PDT 24 Aug 15 05:49:49 PM PDT 24 29379896 ps
T38 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1257307057 Aug 15 05:49:49 PM PDT 24 Aug 15 05:49:50 PM PDT 24 30813938 ps
T50 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.104355021 Aug 15 05:49:49 PM PDT 24 Aug 15 05:49:50 PM PDT 24 31615418 ps
T51 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1419880734 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:51 PM PDT 24 28664858 ps
T52 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.644098757 Aug 15 05:49:48 PM PDT 24 Aug 15 05:49:49 PM PDT 24 29508834 ps
T53 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1043270937 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:06 PM PDT 24 30431249 ps
T54 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2043347481 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:50 PM PDT 24 30023525 ps
T55 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.761177625 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:50 PM PDT 24 27646011 ps
T56 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3906266411 Aug 15 05:49:51 PM PDT 24 Aug 15 05:49:51 PM PDT 24 29583039 ps
T57 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1657988201 Aug 15 05:49:47 PM PDT 24 Aug 15 05:49:48 PM PDT 24 30856348 ps
T26 /workspace/coverage/sync_alert/5.prim_sync_alert.2600240358 Aug 15 06:05:49 PM PDT 24 Aug 15 06:05:49 PM PDT 24 9579115 ps
T27 /workspace/coverage/sync_alert/8.prim_sync_alert.3979498465 Aug 15 06:05:47 PM PDT 24 Aug 15 06:05:52 PM PDT 24 10348994 ps
T28 /workspace/coverage/sync_alert/9.prim_sync_alert.1038798106 Aug 15 06:06:11 PM PDT 24 Aug 15 06:06:11 PM PDT 24 9320586 ps
T35 /workspace/coverage/sync_alert/11.prim_sync_alert.3368744345 Aug 15 06:05:56 PM PDT 24 Aug 15 06:05:57 PM PDT 24 8163026 ps
T29 /workspace/coverage/sync_alert/18.prim_sync_alert.3787792471 Aug 15 06:05:47 PM PDT 24 Aug 15 06:05:48 PM PDT 24 9528258 ps
T11 /workspace/coverage/sync_alert/15.prim_sync_alert.177469659 Aug 15 06:05:45 PM PDT 24 Aug 15 06:05:46 PM PDT 24 8839355 ps
T30 /workspace/coverage/sync_alert/4.prim_sync_alert.2476857271 Aug 15 06:05:51 PM PDT 24 Aug 15 06:05:51 PM PDT 24 9875757 ps
T36 /workspace/coverage/sync_alert/19.prim_sync_alert.708623867 Aug 15 06:05:56 PM PDT 24 Aug 15 06:05:57 PM PDT 24 9007687 ps
T17 /workspace/coverage/sync_alert/1.prim_sync_alert.3623097227 Aug 15 06:05:52 PM PDT 24 Aug 15 06:05:52 PM PDT 24 10048733 ps
T31 /workspace/coverage/sync_alert/13.prim_sync_alert.2906872443 Aug 15 06:06:03 PM PDT 24 Aug 15 06:06:03 PM PDT 24 9148872 ps
T58 /workspace/coverage/sync_alert/12.prim_sync_alert.3769640648 Aug 15 06:06:08 PM PDT 24 Aug 15 06:06:08 PM PDT 24 8291280 ps
T32 /workspace/coverage/sync_alert/17.prim_sync_alert.1807862191 Aug 15 06:05:51 PM PDT 24 Aug 15 06:05:52 PM PDT 24 8499363 ps
T12 /workspace/coverage/sync_alert/2.prim_sync_alert.3883266355 Aug 15 06:06:08 PM PDT 24 Aug 15 06:06:09 PM PDT 24 9650762 ps
T59 /workspace/coverage/sync_alert/7.prim_sync_alert.722495102 Aug 15 06:05:52 PM PDT 24 Aug 15 06:05:53 PM PDT 24 8677673 ps
T33 /workspace/coverage/sync_alert/6.prim_sync_alert.2151172711 Aug 15 06:06:07 PM PDT 24 Aug 15 06:06:07 PM PDT 24 8715324 ps
T60 /workspace/coverage/sync_alert/0.prim_sync_alert.3073019061 Aug 15 06:05:48 PM PDT 24 Aug 15 06:05:48 PM PDT 24 9866055 ps
T61 /workspace/coverage/sync_alert/16.prim_sync_alert.2168932732 Aug 15 06:05:57 PM PDT 24 Aug 15 06:05:58 PM PDT 24 10314828 ps
T62 /workspace/coverage/sync_alert/14.prim_sync_alert.673450528 Aug 15 06:05:51 PM PDT 24 Aug 15 06:05:51 PM PDT 24 8735992 ps
T13 /workspace/coverage/sync_alert/10.prim_sync_alert.1226294978 Aug 15 06:05:44 PM PDT 24 Aug 15 06:05:45 PM PDT 24 8725105 ps
T63 /workspace/coverage/sync_alert/3.prim_sync_alert.921270776 Aug 15 06:05:56 PM PDT 24 Aug 15 06:05:56 PM PDT 24 8212577 ps
T64 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1058068603 Aug 15 05:49:53 PM PDT 24 Aug 15 05:49:53 PM PDT 24 29734503 ps
T34 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3003698856 Aug 15 05:49:51 PM PDT 24 Aug 15 05:49:52 PM PDT 24 27345232 ps
T65 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1221719954 Aug 15 05:49:59 PM PDT 24 Aug 15 05:50:00 PM PDT 24 27715170 ps
T4 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3213723450 Aug 15 05:49:49 PM PDT 24 Aug 15 05:49:49 PM PDT 24 26543672 ps
T66 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.687851508 Aug 15 05:49:48 PM PDT 24 Aug 15 05:49:49 PM PDT 24 26984031 ps
T67 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2985342293 Aug 15 05:49:51 PM PDT 24 Aug 15 05:49:51 PM PDT 24 26663448 ps
T68 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4085484422 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:51 PM PDT 24 27672247 ps
T5 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2342235326 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:50 PM PDT 24 28926428 ps
T69 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1678300620 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:51 PM PDT 24 28240033 ps
T6 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2144969592 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:51 PM PDT 24 26078349 ps
T70 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4194510646 Aug 15 05:49:52 PM PDT 24 Aug 15 05:49:52 PM PDT 24 27675391 ps
T71 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.289179530 Aug 15 05:49:47 PM PDT 24 Aug 15 05:49:47 PM PDT 24 26119094 ps
T72 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1192354269 Aug 15 05:49:49 PM PDT 24 Aug 15 05:49:49 PM PDT 24 25421040 ps
T73 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1789472963 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:50 PM PDT 24 26438238 ps
T74 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3521990308 Aug 15 05:49:49 PM PDT 24 Aug 15 05:49:49 PM PDT 24 27139154 ps
T75 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2004084778 Aug 15 05:49:48 PM PDT 24 Aug 15 05:49:49 PM PDT 24 28395497 ps
T76 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3336276624 Aug 15 05:49:48 PM PDT 24 Aug 15 05:49:49 PM PDT 24 29641585 ps
T77 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2232968174 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:50 PM PDT 24 28153668 ps
T78 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2360326097 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:50 PM PDT 24 28247030 ps
T79 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3755122260 Aug 15 05:49:50 PM PDT 24 Aug 15 05:49:50 PM PDT 24 27875709 ps

Test location /workspace/coverage/default/11.prim_async_alert.1978620646
Short name T18
Test name
Test status
Simulation time 10596959 ps
CPU time 0.4 seconds
Started Aug 15 05:39:55 PM PDT 24
Finished Aug 15 05:39:55 PM PDT 24
Peak memory 145792 kb
Host smart-69426551-95e1-4ba9-a5bd-d633067d920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978620646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1978620646
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2600240358
Short name T26
Test name
Test status
Simulation time 9579115 ps
CPU time 0.43 seconds
Started Aug 15 06:05:49 PM PDT 24
Finished Aug 15 06:05:49 PM PDT 24
Peak memory 145580 kb
Host smart-f7cbe698-dc2d-4df7-b02e-bd32b2325aa7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2600240358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2600240358
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3382873156
Short name T19
Test name
Test status
Simulation time 32396236 ps
CPU time 0.41 seconds
Started Aug 15 05:50:00 PM PDT 24
Finished Aug 15 05:50:01 PM PDT 24
Peak memory 145324 kb
Host smart-ab05904c-0682-4742-9416-eda37a599326
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3382873156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3382873156
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3623097227
Short name T17
Test name
Test status
Simulation time 10048733 ps
CPU time 0.39 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:05:52 PM PDT 24
Peak memory 145584 kb
Host smart-ed16cf7a-ccf1-4845-ac88-6073cda98a9b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3623097227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3623097227
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1226294978
Short name T13
Test name
Test status
Simulation time 8725105 ps
CPU time 0.38 seconds
Started Aug 15 06:05:44 PM PDT 24
Finished Aug 15 06:05:45 PM PDT 24
Peak memory 145568 kb
Host smart-1905a2de-6436-4066-831d-b7655a59068a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1226294978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1226294978
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2342235326
Short name T5
Test name
Test status
Simulation time 28926428 ps
CPU time 0.41 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:50 PM PDT 24
Peak memory 145608 kb
Host smart-0c3d52cd-c233-40ec-b5af-674fa76d7cf0
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2342235326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2342235326
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2504946441
Short name T9
Test name
Test status
Simulation time 11290052 ps
CPU time 0.39 seconds
Started Aug 15 05:39:56 PM PDT 24
Finished Aug 15 05:39:56 PM PDT 24
Peak memory 145796 kb
Host smart-841655c5-2170-4572-911c-cf114a8f8068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504946441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2504946441
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1057987579
Short name T48
Test name
Test status
Simulation time 11893274 ps
CPU time 0.39 seconds
Started Aug 15 05:39:51 PM PDT 24
Finished Aug 15 05:39:52 PM PDT 24
Peak memory 145792 kb
Host smart-a773b3e0-790c-4f4f-a2c3-b4c622a2a2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057987579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1057987579
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1901475510
Short name T15
Test name
Test status
Simulation time 12001553 ps
CPU time 0.38 seconds
Started Aug 15 05:39:41 PM PDT 24
Finished Aug 15 05:39:42 PM PDT 24
Peak memory 145684 kb
Host smart-2e61fe5f-3746-422e-8016-1894f66a1830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901475510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1901475510
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3704669708
Short name T49
Test name
Test status
Simulation time 11307878 ps
CPU time 0.39 seconds
Started Aug 15 05:39:48 PM PDT 24
Finished Aug 15 05:39:48 PM PDT 24
Peak memory 145788 kb
Host smart-dff0bf00-b528-406f-b6c3-c9941230bfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704669708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3704669708
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.523913752
Short name T25
Test name
Test status
Simulation time 11622304 ps
CPU time 0.38 seconds
Started Aug 15 05:39:45 PM PDT 24
Finished Aug 15 05:39:45 PM PDT 24
Peak memory 145744 kb
Host smart-9d0f7101-a828-48ad-af81-f148b3387a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523913752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.523913752
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.303328872
Short name T3
Test name
Test status
Simulation time 11005900 ps
CPU time 0.39 seconds
Started Aug 15 05:39:32 PM PDT 24
Finished Aug 15 05:39:33 PM PDT 24
Peak memory 145668 kb
Host smart-32e9b408-df74-4072-9462-2f9866867fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303328872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.303328872
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.1643475617
Short name T24
Test name
Test status
Simulation time 11089034 ps
CPU time 0.4 seconds
Started Aug 15 05:39:47 PM PDT 24
Finished Aug 15 05:39:47 PM PDT 24
Peak memory 145908 kb
Host smart-84d7f6b7-198e-4d62-a82c-5b7bd9392bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643475617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1643475617
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.54733366
Short name T21
Test name
Test status
Simulation time 11202077 ps
CPU time 0.39 seconds
Started Aug 15 05:39:49 PM PDT 24
Finished Aug 15 05:39:50 PM PDT 24
Peak memory 145632 kb
Host smart-5629fefb-1c19-4b1f-b738-6a18935e72c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54733366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.54733366
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.2128688402
Short name T46
Test name
Test status
Simulation time 10996723 ps
CPU time 0.39 seconds
Started Aug 15 05:39:43 PM PDT 24
Finished Aug 15 05:39:44 PM PDT 24
Peak memory 145768 kb
Host smart-73f6b7b9-ad80-49c9-9412-65b490f1228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128688402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.2128688402
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1838931023
Short name T10
Test name
Test status
Simulation time 10750474 ps
CPU time 0.39 seconds
Started Aug 15 05:39:57 PM PDT 24
Finished Aug 15 05:39:57 PM PDT 24
Peak memory 145804 kb
Host smart-8ddddbf6-b12f-4380-8061-aa09d55f0d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838931023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1838931023
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.419563421
Short name T22
Test name
Test status
Simulation time 11156149 ps
CPU time 0.4 seconds
Started Aug 15 05:39:46 PM PDT 24
Finished Aug 15 05:39:46 PM PDT 24
Peak memory 145796 kb
Host smart-61de3e88-8444-4071-a20f-7807dc9fcec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419563421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.419563421
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3822147002
Short name T47
Test name
Test status
Simulation time 11266523 ps
CPU time 0.4 seconds
Started Aug 15 05:39:52 PM PDT 24
Finished Aug 15 05:39:53 PM PDT 24
Peak memory 145804 kb
Host smart-cf593e99-4bee-49bf-a824-35a9ed1633ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822147002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3822147002
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.4094017910
Short name T1
Test name
Test status
Simulation time 10939527 ps
CPU time 0.4 seconds
Started Aug 15 05:39:51 PM PDT 24
Finished Aug 15 05:39:51 PM PDT 24
Peak memory 145808 kb
Host smart-09b25a0a-7abd-4815-ad18-54d0763a8f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094017910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.4094017910
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3591076291
Short name T14
Test name
Test status
Simulation time 12215941 ps
CPU time 0.39 seconds
Started Aug 15 05:39:49 PM PDT 24
Finished Aug 15 05:39:50 PM PDT 24
Peak memory 145784 kb
Host smart-fc71d43c-843b-4003-a84f-6d621b2dbb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591076291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3591076291
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.1603926347
Short name T16
Test name
Test status
Simulation time 12020711 ps
CPU time 0.39 seconds
Started Aug 15 05:39:49 PM PDT 24
Finished Aug 15 05:39:50 PM PDT 24
Peak memory 145828 kb
Host smart-807cabd8-0f0f-4ee8-8eb1-5d5cea4582c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603926347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1603926347
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1987118260
Short name T2
Test name
Test status
Simulation time 10867309 ps
CPU time 0.38 seconds
Started Aug 15 05:39:51 PM PDT 24
Finished Aug 15 05:39:52 PM PDT 24
Peak memory 145776 kb
Host smart-355eb8a8-5116-4858-8c96-d636208588f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987118260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1987118260
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.660256127
Short name T7
Test name
Test status
Simulation time 10857450 ps
CPU time 0.37 seconds
Started Aug 15 05:39:40 PM PDT 24
Finished Aug 15 05:39:40 PM PDT 24
Peak memory 145784 kb
Host smart-b99fa44e-6cbd-4b02-9ac8-0a57e694bf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660256127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.660256127
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.4126300808
Short name T8
Test name
Test status
Simulation time 11575296 ps
CPU time 0.38 seconds
Started Aug 15 05:39:34 PM PDT 24
Finished Aug 15 05:39:34 PM PDT 24
Peak memory 145788 kb
Host smart-d1bfe4e3-897d-41df-809e-7bf3fd8292e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126300808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4126300808
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1930154500
Short name T23
Test name
Test status
Simulation time 11160596 ps
CPU time 0.39 seconds
Started Aug 15 05:39:55 PM PDT 24
Finished Aug 15 05:39:55 PM PDT 24
Peak memory 145784 kb
Host smart-66331aa7-ca5f-4ab5-9e23-b1541719f5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930154500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1930154500
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1657988201
Short name T57
Test name
Test status
Simulation time 30856348 ps
CPU time 0.39 seconds
Started Aug 15 05:49:47 PM PDT 24
Finished Aug 15 05:49:48 PM PDT 24
Peak memory 145316 kb
Host smart-546afa8a-4700-48ed-8957-47736a150cd1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1657988201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1657988201
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1257307057
Short name T38
Test name
Test status
Simulation time 30813938 ps
CPU time 0.41 seconds
Started Aug 15 05:49:49 PM PDT 24
Finished Aug 15 05:49:50 PM PDT 24
Peak memory 145300 kb
Host smart-e197807a-da3a-4bec-8a67-38489699b803
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1257307057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1257307057
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3441335607
Short name T43
Test name
Test status
Simulation time 28783661 ps
CPU time 0.39 seconds
Started Aug 15 05:50:04 PM PDT 24
Finished Aug 15 05:50:04 PM PDT 24
Peak memory 145324 kb
Host smart-874d07eb-da7d-40b8-81ba-523d7db31cd6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3441335607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3441335607
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1729152453
Short name T44
Test name
Test status
Simulation time 30137321 ps
CPU time 0.4 seconds
Started Aug 15 05:49:48 PM PDT 24
Finished Aug 15 05:49:48 PM PDT 24
Peak memory 145300 kb
Host smart-91bfda4a-d5cd-4ae7-ae6d-28d034034508
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1729152453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1729152453
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.171464537
Short name T39
Test name
Test status
Simulation time 30259762 ps
CPU time 0.45 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:51 PM PDT 24
Peak memory 145284 kb
Host smart-ba4dd18b-e96c-434c-9df9-23bee55ded13
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=171464537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.171464537
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.644098757
Short name T52
Test name
Test status
Simulation time 29508834 ps
CPU time 0.43 seconds
Started Aug 15 05:49:48 PM PDT 24
Finished Aug 15 05:49:49 PM PDT 24
Peak memory 145208 kb
Host smart-8f31b8a8-b891-4678-b24a-9c440bc1cb1b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=644098757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.644098757
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.548674647
Short name T41
Test name
Test status
Simulation time 30583674 ps
CPU time 0.39 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:06 PM PDT 24
Peak memory 145284 kb
Host smart-6d1fcfe2-7166-4e46-b60b-5f49cdfc7dfc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=548674647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.548674647
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3906266411
Short name T56
Test name
Test status
Simulation time 29583039 ps
CPU time 0.41 seconds
Started Aug 15 05:49:51 PM PDT 24
Finished Aug 15 05:49:51 PM PDT 24
Peak memory 145244 kb
Host smart-235e8bc5-dd4f-432a-acbd-9c791a7088af
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3906266411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3906266411
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2131501738
Short name T45
Test name
Test status
Simulation time 30724091 ps
CPU time 0.4 seconds
Started Aug 15 05:50:00 PM PDT 24
Finished Aug 15 05:50:00 PM PDT 24
Peak memory 145320 kb
Host smart-ee5599ba-d166-4bd4-807d-e8a594800c3b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2131501738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2131501738
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1419880734
Short name T51
Test name
Test status
Simulation time 28664858 ps
CPU time 0.43 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:51 PM PDT 24
Peak memory 145320 kb
Host smart-674dd540-68d3-4610-99ea-d663a61b4dae
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1419880734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1419880734
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.761177625
Short name T55
Test name
Test status
Simulation time 27646011 ps
CPU time 0.41 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:50 PM PDT 24
Peak memory 145296 kb
Host smart-b0b40790-8f95-46b2-8b24-93c2ffc2d2b8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=761177625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.761177625
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2043347481
Short name T54
Test name
Test status
Simulation time 30023525 ps
CPU time 0.4 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:50 PM PDT 24
Peak memory 145268 kb
Host smart-40b695f9-7525-41f5-a3ff-fc88c471d9b4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2043347481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2043347481
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1497026067
Short name T40
Test name
Test status
Simulation time 28632171 ps
CPU time 0.42 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:51 PM PDT 24
Peak memory 145284 kb
Host smart-37c2a512-63d5-4688-8720-626739fb7a74
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1497026067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1497026067
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2172742441
Short name T42
Test name
Test status
Simulation time 29182488 ps
CPU time 0.4 seconds
Started Aug 15 05:50:00 PM PDT 24
Finished Aug 15 05:50:01 PM PDT 24
Peak memory 145268 kb
Host smart-7ad02473-1d90-4cb0-86a7-32c5cfaf0965
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2172742441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2172742441
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1043270937
Short name T53
Test name
Test status
Simulation time 30431249 ps
CPU time 0.39 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:06 PM PDT 24
Peak memory 145268 kb
Host smart-8c49fcf2-3845-47f2-aafa-9d1cab9748e6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1043270937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1043270937
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3382529090
Short name T20
Test name
Test status
Simulation time 29379896 ps
CPU time 0.4 seconds
Started Aug 15 05:49:48 PM PDT 24
Finished Aug 15 05:49:49 PM PDT 24
Peak memory 145292 kb
Host smart-585267bf-cadf-4cec-acc0-4e452df9b650
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3382529090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3382529090
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.104355021
Short name T50
Test name
Test status
Simulation time 31615418 ps
CPU time 0.42 seconds
Started Aug 15 05:49:49 PM PDT 24
Finished Aug 15 05:49:50 PM PDT 24
Peak memory 145316 kb
Host smart-49c3acb7-1ab7-442a-815e-1c7d12209038
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=104355021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.104355021
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3201370403
Short name T37
Test name
Test status
Simulation time 29909027 ps
CPU time 0.38 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:06 PM PDT 24
Peak memory 145268 kb
Host smart-8bdb4df5-8f06-45cb-ba34-e88ff4f7c4ee
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3201370403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3201370403
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3073019061
Short name T60
Test name
Test status
Simulation time 9866055 ps
CPU time 0.4 seconds
Started Aug 15 06:05:48 PM PDT 24
Finished Aug 15 06:05:48 PM PDT 24
Peak memory 145540 kb
Host smart-619e4cb8-b671-4740-96c0-82a395249393
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3073019061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3073019061
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3368744345
Short name T35
Test name
Test status
Simulation time 8163026 ps
CPU time 0.37 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:05:57 PM PDT 24
Peak memory 145568 kb
Host smart-6278b067-c39d-41d1-9fe8-75b29917fad2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3368744345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3368744345
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3769640648
Short name T58
Test name
Test status
Simulation time 8291280 ps
CPU time 0.38 seconds
Started Aug 15 06:06:08 PM PDT 24
Finished Aug 15 06:06:08 PM PDT 24
Peak memory 145572 kb
Host smart-e66d78ca-66f3-4a45-bddf-15e89ef07986
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3769640648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3769640648
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2906872443
Short name T31
Test name
Test status
Simulation time 9148872 ps
CPU time 0.36 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:06:03 PM PDT 24
Peak memory 145576 kb
Host smart-b114ae7c-9ed3-4624-a1a1-9654b3568b61
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2906872443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2906872443
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.673450528
Short name T62
Test name
Test status
Simulation time 8735992 ps
CPU time 0.37 seconds
Started Aug 15 06:05:51 PM PDT 24
Finished Aug 15 06:05:51 PM PDT 24
Peak memory 145604 kb
Host smart-83b1a30a-c269-47c4-acc8-547f3ab571f4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=673450528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.673450528
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.177469659
Short name T11
Test name
Test status
Simulation time 8839355 ps
CPU time 0.39 seconds
Started Aug 15 06:05:45 PM PDT 24
Finished Aug 15 06:05:46 PM PDT 24
Peak memory 145584 kb
Host smart-d968da9b-ceb8-4679-a6ca-6d5f156d14a9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=177469659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.177469659
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2168932732
Short name T61
Test name
Test status
Simulation time 10314828 ps
CPU time 0.39 seconds
Started Aug 15 06:05:57 PM PDT 24
Finished Aug 15 06:05:58 PM PDT 24
Peak memory 145596 kb
Host smart-bafe0a3c-99bc-4f13-bc49-fda6c9db18f3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2168932732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2168932732
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1807862191
Short name T32
Test name
Test status
Simulation time 8499363 ps
CPU time 0.4 seconds
Started Aug 15 06:05:51 PM PDT 24
Finished Aug 15 06:05:52 PM PDT 24
Peak memory 145548 kb
Host smart-2b8b7702-6f38-405a-bb1e-7a28bca332e2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1807862191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1807862191
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.3787792471
Short name T29
Test name
Test status
Simulation time 9528258 ps
CPU time 0.38 seconds
Started Aug 15 06:05:47 PM PDT 24
Finished Aug 15 06:05:48 PM PDT 24
Peak memory 145596 kb
Host smart-8b93ed02-ac6c-4e26-9408-e0eea423ed0c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3787792471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3787792471
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.708623867
Short name T36
Test name
Test status
Simulation time 9007687 ps
CPU time 0.4 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:05:57 PM PDT 24
Peak memory 145532 kb
Host smart-778dd40f-b7a9-4c5f-93dd-f1e97594183a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=708623867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.708623867
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3883266355
Short name T12
Test name
Test status
Simulation time 9650762 ps
CPU time 0.44 seconds
Started Aug 15 06:06:08 PM PDT 24
Finished Aug 15 06:06:09 PM PDT 24
Peak memory 145576 kb
Host smart-266049f7-b3dc-4d97-bb23-f7435cebfbde
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3883266355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3883266355
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.921270776
Short name T63
Test name
Test status
Simulation time 8212577 ps
CPU time 0.37 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:05:56 PM PDT 24
Peak memory 145588 kb
Host smart-1486d56d-0123-47a7-85e5-3edf8bdb61c4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=921270776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.921270776
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2476857271
Short name T30
Test name
Test status
Simulation time 9875757 ps
CPU time 0.37 seconds
Started Aug 15 06:05:51 PM PDT 24
Finished Aug 15 06:05:51 PM PDT 24
Peak memory 145560 kb
Host smart-e6704c78-9e8d-4baa-aff7-ce0996c34663
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2476857271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2476857271
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2151172711
Short name T33
Test name
Test status
Simulation time 8715324 ps
CPU time 0.37 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:07 PM PDT 24
Peak memory 145604 kb
Host smart-3b324d1e-b490-4257-9406-1d41f2fd968c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2151172711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2151172711
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.722495102
Short name T59
Test name
Test status
Simulation time 8677673 ps
CPU time 0.39 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:05:53 PM PDT 24
Peak memory 145616 kb
Host smart-db00538e-cc3a-4d3d-ba4d-4428402c75ac
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=722495102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.722495102
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3979498465
Short name T27
Test name
Test status
Simulation time 10348994 ps
CPU time 0.39 seconds
Started Aug 15 06:05:47 PM PDT 24
Finished Aug 15 06:05:52 PM PDT 24
Peak memory 144348 kb
Host smart-2d179038-c2bd-47cd-9064-dfcedf372c47
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3979498465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3979498465
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1038798106
Short name T28
Test name
Test status
Simulation time 9320586 ps
CPU time 0.39 seconds
Started Aug 15 06:06:11 PM PDT 24
Finished Aug 15 06:06:11 PM PDT 24
Peak memory 145604 kb
Host smart-5870822b-dfd7-4518-abaf-9983f57341c1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1038798106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1038798106
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3521990308
Short name T74
Test name
Test status
Simulation time 27139154 ps
CPU time 0.4 seconds
Started Aug 15 05:49:49 PM PDT 24
Finished Aug 15 05:49:49 PM PDT 24
Peak memory 145584 kb
Host smart-b59b56dd-7bd0-49ad-9871-e372954b6212
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3521990308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3521990308
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1789472963
Short name T73
Test name
Test status
Simulation time 26438238 ps
CPU time 0.39 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:50 PM PDT 24
Peak memory 145612 kb
Host smart-17bacfad-7596-4679-9a8e-3682b4afc48d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1789472963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1789472963
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2985342293
Short name T67
Test name
Test status
Simulation time 26663448 ps
CPU time 0.4 seconds
Started Aug 15 05:49:51 PM PDT 24
Finished Aug 15 05:49:51 PM PDT 24
Peak memory 145592 kb
Host smart-56addbf3-6704-4c69-bb27-09cd8f4222c2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2985342293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2985342293
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1058068603
Short name T64
Test name
Test status
Simulation time 29734503 ps
CPU time 0.4 seconds
Started Aug 15 05:49:53 PM PDT 24
Finished Aug 15 05:49:53 PM PDT 24
Peak memory 145596 kb
Host smart-201f1b01-a916-42b6-a20f-e95c437d20ba
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1058068603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1058068603
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2232968174
Short name T77
Test name
Test status
Simulation time 28153668 ps
CPU time 0.41 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:50 PM PDT 24
Peak memory 145612 kb
Host smart-52f260c5-e809-47a0-bc64-d044b8574ef3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2232968174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2232968174
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1678300620
Short name T69
Test name
Test status
Simulation time 28240033 ps
CPU time 0.45 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:51 PM PDT 24
Peak memory 145576 kb
Host smart-df2d2c0b-9c56-4347-b402-4f9353879882
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1678300620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1678300620
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.687851508
Short name T66
Test name
Test status
Simulation time 26984031 ps
CPU time 0.4 seconds
Started Aug 15 05:49:48 PM PDT 24
Finished Aug 15 05:49:49 PM PDT 24
Peak memory 145596 kb
Host smart-dd47ded5-eed9-438e-b05a-3c383b049ba4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=687851508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.687851508
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3336276624
Short name T76
Test name
Test status
Simulation time 29641585 ps
CPU time 0.41 seconds
Started Aug 15 05:49:48 PM PDT 24
Finished Aug 15 05:49:49 PM PDT 24
Peak memory 145572 kb
Host smart-9ec62440-1907-458b-9d98-49af5f9618e6
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3336276624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3336276624
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2144969592
Short name T6
Test name
Test status
Simulation time 26078349 ps
CPU time 0.42 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:51 PM PDT 24
Peak memory 145608 kb
Host smart-a641d05f-5d89-41c0-be44-3e0a6fe6bf82
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2144969592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2144969592
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3755122260
Short name T79
Test name
Test status
Simulation time 27875709 ps
CPU time 0.42 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:50 PM PDT 24
Peak memory 145596 kb
Host smart-d0013f91-59b8-4805-9363-9f1e499d24d9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3755122260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3755122260
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4085484422
Short name T68
Test name
Test status
Simulation time 27672247 ps
CPU time 0.42 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:51 PM PDT 24
Peak memory 145592 kb
Host smart-f86ebb93-060c-455b-939d-2d7d964bceda
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4085484422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4085484422
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1221719954
Short name T65
Test name
Test status
Simulation time 27715170 ps
CPU time 0.41 seconds
Started Aug 15 05:49:59 PM PDT 24
Finished Aug 15 05:50:00 PM PDT 24
Peak memory 145588 kb
Host smart-c7617134-1906-423e-a036-3731fc456ad3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1221719954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1221719954
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.289179530
Short name T71
Test name
Test status
Simulation time 26119094 ps
CPU time 0.39 seconds
Started Aug 15 05:49:47 PM PDT 24
Finished Aug 15 05:49:47 PM PDT 24
Peak memory 145468 kb
Host smart-a353089b-2757-4529-ab9b-c55d270ec196
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=289179530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.289179530
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3213723450
Short name T4
Test name
Test status
Simulation time 26543672 ps
CPU time 0.41 seconds
Started Aug 15 05:49:49 PM PDT 24
Finished Aug 15 05:49:49 PM PDT 24
Peak memory 145468 kb
Host smart-534fcf00-a07a-45e5-9011-f4c120f233d4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3213723450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3213723450
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3003698856
Short name T34
Test name
Test status
Simulation time 27345232 ps
CPU time 0.41 seconds
Started Aug 15 05:49:51 PM PDT 24
Finished Aug 15 05:49:52 PM PDT 24
Peak memory 145620 kb
Host smart-c492de50-8d9e-456b-b480-0daa34c96489
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3003698856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3003698856
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2004084778
Short name T75
Test name
Test status
Simulation time 28395497 ps
CPU time 0.39 seconds
Started Aug 15 05:49:48 PM PDT 24
Finished Aug 15 05:49:49 PM PDT 24
Peak memory 145600 kb
Host smart-24d12ac7-1ce2-4d76-8cb6-ded1ac86571e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2004084778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2004084778
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4194510646
Short name T70
Test name
Test status
Simulation time 27675391 ps
CPU time 0.41 seconds
Started Aug 15 05:49:52 PM PDT 24
Finished Aug 15 05:49:52 PM PDT 24
Peak memory 145604 kb
Host smart-ebe6b3d3-c1d9-4f6d-8112-576de743259d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4194510646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4194510646
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1192354269
Short name T72
Test name
Test status
Simulation time 25421040 ps
CPU time 0.4 seconds
Started Aug 15 05:49:49 PM PDT 24
Finished Aug 15 05:49:49 PM PDT 24
Peak memory 145612 kb
Host smart-6d4324d1-8552-4bad-bab1-366027a3711b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1192354269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1192354269
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2360326097
Short name T78
Test name
Test status
Simulation time 28247030 ps
CPU time 0.41 seconds
Started Aug 15 05:49:50 PM PDT 24
Finished Aug 15 05:49:50 PM PDT 24
Peak memory 145600 kb
Host smart-e315dd9a-ec05-40a6-be6f-79c9a603e08f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2360326097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2360326097
Directory /workspace/9.prim_sync_fatal_alert/latest
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