| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.88 | 88.88 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/18.prim_async_alert.2095122892 |
| 92.01 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/10.prim_sync_alert.547363680 |
| 93.86 | 1.86 | 100.00 | 0.00 | 97.92 | 4.17 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 83.72 | 6.98 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.126197502 |
| 94.85 | 0.98 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/3.prim_async_alert.3779611468 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2186686097 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.2136970727 |
| /workspace/coverage/default/1.prim_async_alert.1064272407 |
| /workspace/coverage/default/10.prim_async_alert.53210413 |
| /workspace/coverage/default/11.prim_async_alert.3838814894 |
| /workspace/coverage/default/12.prim_async_alert.4113832767 |
| /workspace/coverage/default/13.prim_async_alert.3523794699 |
| /workspace/coverage/default/14.prim_async_alert.2207804664 |
| /workspace/coverage/default/15.prim_async_alert.102245293 |
| /workspace/coverage/default/16.prim_async_alert.3422013424 |
| /workspace/coverage/default/17.prim_async_alert.1623266739 |
| /workspace/coverage/default/19.prim_async_alert.2537284539 |
| /workspace/coverage/default/2.prim_async_alert.4041678225 |
| /workspace/coverage/default/4.prim_async_alert.1935410560 |
| /workspace/coverage/default/5.prim_async_alert.3365597729 |
| /workspace/coverage/default/6.prim_async_alert.2068574680 |
| /workspace/coverage/default/7.prim_async_alert.1056840427 |
| /workspace/coverage/default/8.prim_async_alert.553709563 |
| /workspace/coverage/default/9.prim_async_alert.2697421124 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1950306188 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3989745473 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.831145621 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1388724484 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1890539334 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1638793606 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1892601394 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2732555978 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1318533178 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3676696943 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1683400469 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4128713642 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.322758788 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4044212643 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2036662584 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2603858321 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4211515404 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.827079399 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.4062658383 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.3708293440 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.2579917420 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2088711120 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.52947774 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1490223017 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3879804908 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.4206544771 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.2318302979 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.2087294801 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2469933622 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2233867969 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.2908437367 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.3814366080 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.4087841822 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.2451488697 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.3239608600 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1820156149 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.1914124188 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1012648541 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3002130507 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1473054332 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2599295414 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2555818923 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.968740803 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3671242622 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2586745095 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.417933922 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3408121783 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.812792065 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4137270846 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2012321344 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3107079373 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.448080764 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2627171560 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2932512801 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1643764468 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.941608835 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_async_alert.2697421124 | Aug 16 06:23:11 PM PDT 24 | Aug 16 06:23:12 PM PDT 24 | 11183232 ps | ||
| T2 | /workspace/coverage/default/15.prim_async_alert.102245293 | Aug 16 06:23:43 PM PDT 24 | Aug 16 06:23:43 PM PDT 24 | 11772849 ps | ||
| T3 | /workspace/coverage/default/19.prim_async_alert.2537284539 | Aug 16 06:23:46 PM PDT 24 | Aug 16 06:23:46 PM PDT 24 | 10902705 ps | ||
| T19 | /workspace/coverage/default/2.prim_async_alert.4041678225 | Aug 16 06:23:36 PM PDT 24 | Aug 16 06:23:36 PM PDT 24 | 11637290 ps | ||
| T20 | /workspace/coverage/default/11.prim_async_alert.3838814894 | Aug 16 06:23:12 PM PDT 24 | Aug 16 06:23:12 PM PDT 24 | 10605238 ps | ||
| T6 | /workspace/coverage/default/7.prim_async_alert.1056840427 | Aug 16 06:23:08 PM PDT 24 | Aug 16 06:23:08 PM PDT 24 | 10807705 ps | ||
| T7 | /workspace/coverage/default/6.prim_async_alert.2068574680 | Aug 16 06:23:30 PM PDT 24 | Aug 16 06:23:31 PM PDT 24 | 11955811 ps | ||
| T10 | /workspace/coverage/default/18.prim_async_alert.2095122892 | Aug 16 06:23:21 PM PDT 24 | Aug 16 06:23:22 PM PDT 24 | 12876810 ps | ||
| T8 | /workspace/coverage/default/12.prim_async_alert.4113832767 | Aug 16 06:23:27 PM PDT 24 | Aug 16 06:23:27 PM PDT 24 | 11620482 ps | ||
| T17 | /workspace/coverage/default/16.prim_async_alert.3422013424 | Aug 16 06:23:13 PM PDT 24 | Aug 16 06:23:13 PM PDT 24 | 10829550 ps | ||
| T47 | /workspace/coverage/default/14.prim_async_alert.2207804664 | Aug 16 06:23:12 PM PDT 24 | Aug 16 06:23:12 PM PDT 24 | 10621396 ps | ||
| T15 | /workspace/coverage/default/1.prim_async_alert.1064272407 | Aug 16 06:23:20 PM PDT 24 | Aug 16 06:23:20 PM PDT 24 | 10846956 ps | ||
| T11 | /workspace/coverage/default/10.prim_async_alert.53210413 | Aug 16 06:23:18 PM PDT 24 | Aug 16 06:23:19 PM PDT 24 | 11794736 ps | ||
| T18 | /workspace/coverage/default/0.prim_async_alert.2136970727 | Aug 16 06:23:11 PM PDT 24 | Aug 16 06:23:12 PM PDT 24 | 11938373 ps | ||
| T12 | /workspace/coverage/default/3.prim_async_alert.3779611468 | Aug 16 06:23:12 PM PDT 24 | Aug 16 06:23:12 PM PDT 24 | 12528233 ps | ||
| T38 | /workspace/coverage/default/5.prim_async_alert.3365597729 | Aug 16 06:23:08 PM PDT 24 | Aug 16 06:23:09 PM PDT 24 | 12102802 ps | ||
| T13 | /workspace/coverage/default/13.prim_async_alert.3523794699 | Aug 16 06:23:09 PM PDT 24 | Aug 16 06:23:09 PM PDT 24 | 11856229 ps | ||
| T48 | /workspace/coverage/default/8.prim_async_alert.553709563 | Aug 16 06:23:35 PM PDT 24 | Aug 16 06:23:36 PM PDT 24 | 10769400 ps | ||
| T49 | /workspace/coverage/default/17.prim_async_alert.1623266739 | Aug 16 06:23:42 PM PDT 24 | Aug 16 06:23:43 PM PDT 24 | 11110152 ps | ||
| T50 | /workspace/coverage/default/4.prim_async_alert.1935410560 | Aug 16 06:23:13 PM PDT 24 | Aug 16 06:23:14 PM PDT 24 | 11696610 ps | ||
| T39 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4044212643 | Aug 16 06:23:10 PM PDT 24 | Aug 16 06:23:11 PM PDT 24 | 31335678 ps | ||
| T40 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2603858321 | Aug 16 06:23:10 PM PDT 24 | Aug 16 06:23:11 PM PDT 24 | 30391919 ps | ||
| T37 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4128713642 | Aug 16 06:23:10 PM PDT 24 | Aug 16 06:23:10 PM PDT 24 | 30837515 ps | ||
| T4 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.126197502 | Aug 16 06:23:13 PM PDT 24 | Aug 16 06:23:14 PM PDT 24 | 30924502 ps | ||
| T42 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4211515404 | Aug 16 06:23:11 PM PDT 24 | Aug 16 06:23:12 PM PDT 24 | 30805774 ps | ||
| T43 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.831145621 | Aug 16 06:23:10 PM PDT 24 | Aug 16 06:23:10 PM PDT 24 | 31195410 ps | ||
| T44 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.827079399 | Aug 16 06:23:38 PM PDT 24 | Aug 16 06:23:39 PM PDT 24 | 30799123 ps | ||
| T45 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.322758788 | Aug 16 06:23:34 PM PDT 24 | Aug 16 06:23:35 PM PDT 24 | 32297915 ps | ||
| T14 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1892601394 | Aug 16 06:23:24 PM PDT 24 | Aug 16 06:23:24 PM PDT 24 | 29193012 ps | ||
| T46 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3676696943 | Aug 16 06:23:50 PM PDT 24 | Aug 16 06:23:50 PM PDT 24 | 31503253 ps | ||
| T51 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1638793606 | Aug 16 06:23:10 PM PDT 24 | Aug 16 06:23:10 PM PDT 24 | 31810535 ps | ||
| T52 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1950306188 | Aug 16 06:23:25 PM PDT 24 | Aug 16 06:23:26 PM PDT 24 | 28587215 ps | ||
| T53 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2732555978 | Aug 16 06:23:10 PM PDT 24 | Aug 16 06:23:11 PM PDT 24 | 29142404 ps | ||
| T16 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1890539334 | Aug 16 06:23:13 PM PDT 24 | Aug 16 06:23:13 PM PDT 24 | 28845142 ps | ||
| T41 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1683400469 | Aug 16 06:23:32 PM PDT 24 | Aug 16 06:23:33 PM PDT 24 | 30992894 ps | ||
| T54 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2036662584 | Aug 16 06:23:11 PM PDT 24 | Aug 16 06:23:11 PM PDT 24 | 31870156 ps | ||
| T55 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3989745473 | Aug 16 06:23:35 PM PDT 24 | Aug 16 06:23:36 PM PDT 24 | 29933876 ps | ||
| T56 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1388724484 | Aug 16 06:23:09 PM PDT 24 | Aug 16 06:23:09 PM PDT 24 | 29443136 ps | ||
| T57 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1318533178 | Aug 16 06:23:43 PM PDT 24 | Aug 16 06:23:44 PM PDT 24 | 30135355 ps | ||
| T21 | /workspace/coverage/sync_alert/10.prim_sync_alert.547363680 | Aug 16 06:24:44 PM PDT 24 | Aug 16 06:24:44 PM PDT 24 | 9170425 ps | ||
| T30 | /workspace/coverage/sync_alert/14.prim_sync_alert.1490223017 | Aug 16 06:24:31 PM PDT 24 | Aug 16 06:24:32 PM PDT 24 | 8875674 ps | ||
| T31 | /workspace/coverage/sync_alert/6.prim_sync_alert.2451488697 | Aug 16 06:24:42 PM PDT 24 | Aug 16 06:24:43 PM PDT 24 | 10421956 ps | ||
| T22 | /workspace/coverage/sync_alert/1.prim_sync_alert.3708293440 | Aug 16 06:24:40 PM PDT 24 | Aug 16 06:24:41 PM PDT 24 | 10131822 ps | ||
| T32 | /workspace/coverage/sync_alert/3.prim_sync_alert.2908437367 | Aug 16 06:24:18 PM PDT 24 | Aug 16 06:24:19 PM PDT 24 | 8635042 ps | ||
| T23 | /workspace/coverage/sync_alert/17.prim_sync_alert.2318302979 | Aug 16 06:24:31 PM PDT 24 | Aug 16 06:24:32 PM PDT 24 | 9658904 ps | ||
| T33 | /workspace/coverage/sync_alert/8.prim_sync_alert.1820156149 | Aug 16 06:24:18 PM PDT 24 | Aug 16 06:24:18 PM PDT 24 | 9402730 ps | ||
| T34 | /workspace/coverage/sync_alert/11.prim_sync_alert.2579917420 | Aug 16 06:24:18 PM PDT 24 | Aug 16 06:24:19 PM PDT 24 | 9853439 ps | ||
| T35 | /workspace/coverage/sync_alert/5.prim_sync_alert.4087841822 | Aug 16 06:24:20 PM PDT 24 | Aug 16 06:24:21 PM PDT 24 | 10351938 ps | ||
| T36 | /workspace/coverage/sync_alert/12.prim_sync_alert.2088711120 | Aug 16 06:24:18 PM PDT 24 | Aug 16 06:24:18 PM PDT 24 | 9530860 ps | ||
| T58 | /workspace/coverage/sync_alert/0.prim_sync_alert.4062658383 | Aug 16 06:24:19 PM PDT 24 | Aug 16 06:24:20 PM PDT 24 | 9761772 ps | ||
| T59 | /workspace/coverage/sync_alert/4.prim_sync_alert.3814366080 | Aug 16 06:24:43 PM PDT 24 | Aug 16 06:24:43 PM PDT 24 | 9059462 ps | ||
| T24 | /workspace/coverage/sync_alert/18.prim_sync_alert.2087294801 | Aug 16 06:24:27 PM PDT 24 | Aug 16 06:24:28 PM PDT 24 | 10785817 ps | ||
| T60 | /workspace/coverage/sync_alert/13.prim_sync_alert.52947774 | Aug 16 06:24:20 PM PDT 24 | Aug 16 06:24:20 PM PDT 24 | 8592048 ps | ||
| T61 | /workspace/coverage/sync_alert/19.prim_sync_alert.2469933622 | Aug 16 06:24:29 PM PDT 24 | Aug 16 06:24:29 PM PDT 24 | 8631266 ps | ||
| T62 | /workspace/coverage/sync_alert/2.prim_sync_alert.2233867969 | Aug 16 06:24:39 PM PDT 24 | Aug 16 06:24:39 PM PDT 24 | 9583227 ps | ||
| T25 | /workspace/coverage/sync_alert/15.prim_sync_alert.3879804908 | Aug 16 06:24:50 PM PDT 24 | Aug 16 06:24:50 PM PDT 24 | 8764007 ps | ||
| T26 | /workspace/coverage/sync_alert/7.prim_sync_alert.3239608600 | Aug 16 06:24:42 PM PDT 24 | Aug 16 06:24:42 PM PDT 24 | 9850711 ps | ||
| T63 | /workspace/coverage/sync_alert/16.prim_sync_alert.4206544771 | Aug 16 06:24:41 PM PDT 24 | Aug 16 06:24:41 PM PDT 24 | 9738863 ps | ||
| T64 | /workspace/coverage/sync_alert/9.prim_sync_alert.1914124188 | Aug 16 06:24:20 PM PDT 24 | Aug 16 06:24:21 PM PDT 24 | 8868836 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1473054332 | Aug 16 04:31:45 PM PDT 24 | Aug 16 04:31:45 PM PDT 24 | 27849906 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1643764468 | Aug 16 04:32:13 PM PDT 24 | Aug 16 04:32:14 PM PDT 24 | 26485919 ps | ||
| T27 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.448080764 | Aug 16 04:32:01 PM PDT 24 | Aug 16 04:32:02 PM PDT 24 | 27547723 ps | ||
| T28 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3107079373 | Aug 16 04:31:45 PM PDT 24 | Aug 16 04:31:50 PM PDT 24 | 27736332 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2627171560 | Aug 16 04:31:32 PM PDT 24 | Aug 16 04:31:33 PM PDT 24 | 28090409 ps | ||
| T29 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3002130507 | Aug 16 04:31:43 PM PDT 24 | Aug 16 04:31:44 PM PDT 24 | 26652819 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2599295414 | Aug 16 04:32:11 PM PDT 24 | Aug 16 04:32:12 PM PDT 24 | 29234750 ps | ||
| T5 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2586745095 | Aug 16 04:32:03 PM PDT 24 | Aug 16 04:32:03 PM PDT 24 | 27466495 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.941608835 | Aug 16 04:32:16 PM PDT 24 | Aug 16 04:32:17 PM PDT 24 | 29673651 ps | ||
| T9 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2186686097 | Aug 16 04:31:34 PM PDT 24 | Aug 16 04:31:35 PM PDT 24 | 26778017 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.968740803 | Aug 16 04:31:37 PM PDT 24 | Aug 16 04:31:43 PM PDT 24 | 27262132 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2012321344 | Aug 16 04:32:00 PM PDT 24 | Aug 16 04:32:06 PM PDT 24 | 26445882 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2555818923 | Aug 16 04:32:05 PM PDT 24 | Aug 16 04:32:11 PM PDT 24 | 26665728 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2932512801 | Aug 16 04:31:48 PM PDT 24 | Aug 16 04:31:48 PM PDT 24 | 27147559 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1012648541 | Aug 16 04:31:35 PM PDT 24 | Aug 16 04:31:35 PM PDT 24 | 25503876 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3671242622 | Aug 16 04:31:33 PM PDT 24 | Aug 16 04:31:34 PM PDT 24 | 27802498 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.417933922 | Aug 16 04:31:32 PM PDT 24 | Aug 16 04:31:33 PM PDT 24 | 28878819 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4137270846 | Aug 16 04:32:07 PM PDT 24 | Aug 16 04:32:07 PM PDT 24 | 26420344 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.812792065 | Aug 16 04:31:41 PM PDT 24 | Aug 16 04:31:41 PM PDT 24 | 26735265 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3408121783 | Aug 16 04:31:31 PM PDT 24 | Aug 16 04:31:32 PM PDT 24 | 28670685 ps |
| Test location | /workspace/coverage/default/18.prim_async_alert.2095122892 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12876810 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:23:21 PM PDT 24 |
| Finished | Aug 16 06:23:22 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-4ae57d4d-9520-489c-a18b-d2d0ef4d82da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2095122892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2095122892 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.547363680 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9170425 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:24:44 PM PDT 24 |
| Finished | Aug 16 06:24:44 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-ec4032b6-c046-481a-8bd9-fec7b44b57b1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=547363680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.547363680 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.126197502 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30924502 ps |
| CPU time | 0.42 seconds |
| Started | Aug 16 06:23:13 PM PDT 24 |
| Finished | Aug 16 06:23:14 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-46f3cefc-e352-442e-96ea-93801f348be2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=126197502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.126197502 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.3779611468 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12528233 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:23:12 PM PDT 24 |
| Finished | Aug 16 06:23:12 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-bd78d044-cad1-4511-927f-aaa72f0f78d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779611468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3779611468 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2186686097 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 26778017 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 04:31:34 PM PDT 24 |
| Finished | Aug 16 04:31:35 PM PDT 24 |
| Peak memory | 145348 kb |
| Host | smart-0f95aefb-08ca-411e-beb2-27509fcee917 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2186686097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2186686097 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.2136970727 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11938373 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:11 PM PDT 24 |
| Finished | Aug 16 06:23:12 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-cb9f418a-91d6-4e6a-bb07-a5afbc983ebd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136970727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2136970727 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1064272407 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10846956 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:20 PM PDT 24 |
| Finished | Aug 16 06:23:20 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-2be73b4a-28e5-4a8c-8672-6eee864752cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064272407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1064272407 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.53210413 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11794736 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:23:18 PM PDT 24 |
| Finished | Aug 16 06:23:19 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-da888f76-141c-4690-bc49-9e3f56256fb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=53210413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.53210413 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3838814894 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10605238 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:23:12 PM PDT 24 |
| Finished | Aug 16 06:23:12 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-9fa4f369-5231-4480-b3ac-380ca3621bcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3838814894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3838814894 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.4113832767 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11620482 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:27 PM PDT 24 |
| Finished | Aug 16 06:23:27 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-8ba9c825-4cf9-49da-b801-87beaa353909 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113832767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.4113832767 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3523794699 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11856229 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:23:09 PM PDT 24 |
| Finished | Aug 16 06:23:09 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-098c479b-0493-43d7-98e6-7e7e65a8a809 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523794699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3523794699 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.2207804664 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10621396 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:23:12 PM PDT 24 |
| Finished | Aug 16 06:23:12 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-d8c5a642-a084-4360-a4ba-79b6117a2aed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2207804664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2207804664 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.102245293 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11772849 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:43 PM PDT 24 |
| Finished | Aug 16 06:23:43 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-e1a8787e-76a3-4513-9170-0600c7e4bedb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102245293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.102245293 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.3422013424 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10829550 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:13 PM PDT 24 |
| Finished | Aug 16 06:23:13 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-820c3880-c9b5-4aaf-9aae-cd1d949038d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422013424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3422013424 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1623266739 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11110152 ps |
| CPU time | 0.43 seconds |
| Started | Aug 16 06:23:42 PM PDT 24 |
| Finished | Aug 16 06:23:43 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-089546a7-9777-426d-acfb-f1f73546046c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623266739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1623266739 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.2537284539 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10902705 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:23:46 PM PDT 24 |
| Finished | Aug 16 06:23:46 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-ac455bbc-d2a3-47b7-9647-b145e9dd7b1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2537284539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.2537284539 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.4041678225 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11637290 ps |
| CPU time | 0.41 seconds |
| Started | Aug 16 06:23:36 PM PDT 24 |
| Finished | Aug 16 06:23:36 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-e0df2e74-2bf1-4c3e-8958-cb3a91131be2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4041678225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.4041678225 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.1935410560 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11696610 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:13 PM PDT 24 |
| Finished | Aug 16 06:23:14 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-ca27330d-e1fc-4382-b77b-d3f6cce11cd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935410560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1935410560 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3365597729 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12102802 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:08 PM PDT 24 |
| Finished | Aug 16 06:23:09 PM PDT 24 |
| Peak memory | 145792 kb |
| Host | smart-552d3feb-4a4c-48ee-9ea3-05ebf1e2335d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365597729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3365597729 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.2068574680 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11955811 ps |
| CPU time | 0.41 seconds |
| Started | Aug 16 06:23:30 PM PDT 24 |
| Finished | Aug 16 06:23:31 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-01384e89-368a-4464-99d4-03eee4826569 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068574680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2068574680 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.1056840427 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 10807705 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:23:08 PM PDT 24 |
| Finished | Aug 16 06:23:08 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-a29297c0-64bd-46f9-8a89-4fbd81ad9de8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056840427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1056840427 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.553709563 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10769400 ps |
| CPU time | 0.37 seconds |
| Started | Aug 16 06:23:35 PM PDT 24 |
| Finished | Aug 16 06:23:36 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-9789f691-1334-48be-b6b2-42125ad2f39e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553709563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.553709563 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.2697421124 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11183232 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:23:11 PM PDT 24 |
| Finished | Aug 16 06:23:12 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-7d238d35-d944-4bf3-a94e-a2e0e31a08e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697421124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2697421124 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.1950306188 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 28587215 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:25 PM PDT 24 |
| Finished | Aug 16 06:23:26 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-3c78befb-3e5b-404a-a06c-305a6b5b53dc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1950306188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.1950306188 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3989745473 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29933876 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:35 PM PDT 24 |
| Finished | Aug 16 06:23:36 PM PDT 24 |
| Peak memory | 145304 kb |
| Host | smart-db22b0af-43c2-47b7-ae5f-298456a32f60 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3989745473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3989745473 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.831145621 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31195410 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:23:10 PM PDT 24 |
| Finished | Aug 16 06:23:10 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-5a4e4a2d-93d9-4efd-8fd7-f56f8c19693a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=831145621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.831145621 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.1388724484 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 29443136 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:23:09 PM PDT 24 |
| Finished | Aug 16 06:23:09 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-5d0a6ca4-6426-44ce-93ca-d6b162c9428c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1388724484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.1388724484 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1890539334 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 28845142 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:23:13 PM PDT 24 |
| Finished | Aug 16 06:23:13 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-5a627a88-7079-4379-8dc8-3fbf2f9232d3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1890539334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1890539334 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1638793606 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31810535 ps |
| CPU time | 0.41 seconds |
| Started | Aug 16 06:23:10 PM PDT 24 |
| Finished | Aug 16 06:23:10 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-505220d1-b6d5-4fd5-b9cd-986833ca93c7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1638793606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1638793606 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1892601394 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 29193012 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:23:24 PM PDT 24 |
| Finished | Aug 16 06:23:24 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-1421b808-1760-4708-ade0-ad1bcf1d79bf |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1892601394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1892601394 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2732555978 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29142404 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:23:10 PM PDT 24 |
| Finished | Aug 16 06:23:11 PM PDT 24 |
| Peak memory | 145292 kb |
| Host | smart-cc38c724-f491-4a4e-8fdc-283c6fda6d5d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2732555978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2732555978 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1318533178 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 30135355 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:23:43 PM PDT 24 |
| Finished | Aug 16 06:23:44 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-7c5af841-619b-4cd5-ba81-903ef8255285 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1318533178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1318533178 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.3676696943 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 31503253 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:50 PM PDT 24 |
| Finished | Aug 16 06:23:50 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-977ac7a8-8734-408a-ae15-77f4c7aa971e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3676696943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.3676696943 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1683400469 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30992894 ps |
| CPU time | 0.42 seconds |
| Started | Aug 16 06:23:32 PM PDT 24 |
| Finished | Aug 16 06:23:33 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-0ea35d16-6d2e-47b8-b5d2-cda2a6507c66 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1683400469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1683400469 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4128713642 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 30837515 ps |
| CPU time | 0.41 seconds |
| Started | Aug 16 06:23:10 PM PDT 24 |
| Finished | Aug 16 06:23:10 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-f46ac180-e904-4a78-922b-25920b0a4994 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4128713642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4128713642 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.322758788 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 32297915 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:23:34 PM PDT 24 |
| Finished | Aug 16 06:23:35 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-e81efad8-c6d0-4dbb-8cfd-db13c47853a2 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=322758788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.322758788 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.4044212643 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 31335678 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:10 PM PDT 24 |
| Finished | Aug 16 06:23:11 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-84f97876-bf14-4813-a943-b8b8daf71d09 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4044212643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.4044212643 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2036662584 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 31870156 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:23:11 PM PDT 24 |
| Finished | Aug 16 06:23:11 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-6857d156-6b15-4fc9-8a02-c0290c0bb3be |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2036662584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2036662584 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2603858321 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 30391919 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:23:10 PM PDT 24 |
| Finished | Aug 16 06:23:11 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-fa3d802e-aa3e-4a8a-9f4e-12356c7d568b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2603858321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2603858321 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4211515404 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30805774 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:23:11 PM PDT 24 |
| Finished | Aug 16 06:23:12 PM PDT 24 |
| Peak memory | 145272 kb |
| Host | smart-a7ff31ea-82b7-49ab-9593-56802f01ba52 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4211515404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.4211515404 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.827079399 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30799123 ps |
| CPU time | 0.43 seconds |
| Started | Aug 16 06:23:38 PM PDT 24 |
| Finished | Aug 16 06:23:39 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-09d78b71-200f-423c-a4ca-2478f32c6624 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=827079399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.827079399 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.4062658383 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9761772 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:24:19 PM PDT 24 |
| Finished | Aug 16 06:24:20 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-c1e05393-8116-4ca6-a18a-c86a284a421a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4062658383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.4062658383 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.3708293440 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10131822 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:24:40 PM PDT 24 |
| Finished | Aug 16 06:24:41 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-ed695f28-535f-471b-9ce1-aee032c3456c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3708293440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3708293440 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.2579917420 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9853439 ps |
| CPU time | 0.41 seconds |
| Started | Aug 16 06:24:18 PM PDT 24 |
| Finished | Aug 16 06:24:19 PM PDT 24 |
| Peak memory | 145592 kb |
| Host | smart-d996f0d2-5d83-4f3d-9ecd-5b85fba16ba9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2579917420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2579917420 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2088711120 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9530860 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:24:18 PM PDT 24 |
| Finished | Aug 16 06:24:18 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-7703dc0f-9cfc-4370-91dc-e2f8ea15dde3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2088711120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2088711120 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.52947774 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8592048 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:24:20 PM PDT 24 |
| Finished | Aug 16 06:24:20 PM PDT 24 |
| Peak memory | 145520 kb |
| Host | smart-d5ddfafa-3b5b-453f-b6f4-fc7e72ebcccc |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=52947774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.52947774 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1490223017 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8875674 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:24:31 PM PDT 24 |
| Finished | Aug 16 06:24:32 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-e397107c-6ba0-400e-8bbf-32bcaf329fc8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1490223017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1490223017 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3879804908 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8764007 ps |
| CPU time | 0.36 seconds |
| Started | Aug 16 06:24:50 PM PDT 24 |
| Finished | Aug 16 06:24:50 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-81f2297c-c796-491b-a653-27b5dcb65532 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3879804908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3879804908 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.4206544771 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 9738863 ps |
| CPU time | 0.37 seconds |
| Started | Aug 16 06:24:41 PM PDT 24 |
| Finished | Aug 16 06:24:41 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-356e0fd5-d1fc-4916-b6e9-6e538b1f6e23 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4206544771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.4206544771 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.2318302979 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9658904 ps |
| CPU time | 0.41 seconds |
| Started | Aug 16 06:24:31 PM PDT 24 |
| Finished | Aug 16 06:24:32 PM PDT 24 |
| Peak memory | 145596 kb |
| Host | smart-66736eb7-6edb-4ee5-ad61-588f61f2c248 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2318302979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2318302979 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.2087294801 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10785817 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:24:27 PM PDT 24 |
| Finished | Aug 16 06:24:28 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-bdc47751-b3d5-4943-9bcc-b381b0840c89 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2087294801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2087294801 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2469933622 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8631266 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:24:29 PM PDT 24 |
| Finished | Aug 16 06:24:29 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-6580159e-51a8-422a-a692-684b319873da |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2469933622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2469933622 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2233867969 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 9583227 ps |
| CPU time | 0.44 seconds |
| Started | Aug 16 06:24:39 PM PDT 24 |
| Finished | Aug 16 06:24:39 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-bbf4e271-3103-4ec5-97d9-4509b731559f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2233867969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2233867969 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.2908437367 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8635042 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 06:24:18 PM PDT 24 |
| Finished | Aug 16 06:24:19 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-3f7c0c14-cda0-496c-b026-f555f093f86b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2908437367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2908437367 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.3814366080 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9059462 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:24:43 PM PDT 24 |
| Finished | Aug 16 06:24:43 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-28930695-72c0-48b8-b041-a4a8609e5e2f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3814366080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3814366080 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.4087841822 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10351938 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:24:20 PM PDT 24 |
| Finished | Aug 16 06:24:21 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-93379565-6b9d-4a11-b3b5-39aadd687cdd |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4087841822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.4087841822 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.2451488697 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10421956 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:24:42 PM PDT 24 |
| Finished | Aug 16 06:24:43 PM PDT 24 |
| Peak memory | 145560 kb |
| Host | smart-63da464d-fc74-46df-9dc8-5b7c9fdc8d91 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2451488697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2451488697 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.3239608600 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9850711 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 06:24:42 PM PDT 24 |
| Finished | Aug 16 06:24:42 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-8c041aa8-93e7-48e8-9c19-a3ddbbb76508 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3239608600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3239608600 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1820156149 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9402730 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:24:18 PM PDT 24 |
| Finished | Aug 16 06:24:18 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-f1a8634b-ec35-4256-928d-86d47417a08a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1820156149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1820156149 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.1914124188 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 8868836 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 06:24:20 PM PDT 24 |
| Finished | Aug 16 06:24:21 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-74d75093-4567-493c-9913-42bd74c1e634 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1914124188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1914124188 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1012648541 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 25503876 ps |
| CPU time | 0.41 seconds |
| Started | Aug 16 04:31:35 PM PDT 24 |
| Finished | Aug 16 04:31:35 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-63f1b136-1a22-40e7-80c0-de9ee6e4ca94 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1012648541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1012648541 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3002130507 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 26652819 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 04:31:43 PM PDT 24 |
| Finished | Aug 16 04:31:44 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-ea68e478-cd62-4497-b569-117b30150566 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3002130507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3002130507 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1473054332 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27849906 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 04:31:45 PM PDT 24 |
| Finished | Aug 16 04:31:45 PM PDT 24 |
| Peak memory | 145392 kb |
| Host | smart-4ba0a5a5-69fe-4f97-b12c-b5485a3e70a8 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1473054332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1473054332 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2599295414 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 29234750 ps |
| CPU time | 0.41 seconds |
| Started | Aug 16 04:32:11 PM PDT 24 |
| Finished | Aug 16 04:32:12 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-e6f30b78-e97e-46f0-8a0d-45dce16a25d1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2599295414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2599295414 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2555818923 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26665728 ps |
| CPU time | 0.41 seconds |
| Started | Aug 16 04:32:05 PM PDT 24 |
| Finished | Aug 16 04:32:11 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-2d3a4fc0-afa4-4c67-82e0-70b0fc989a71 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2555818923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2555818923 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.968740803 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27262132 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:31:37 PM PDT 24 |
| Finished | Aug 16 04:31:43 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-cda0870d-b247-4e05-a5d9-b743442f77c9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=968740803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.968740803 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3671242622 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27802498 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:31:33 PM PDT 24 |
| Finished | Aug 16 04:31:34 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-779f622f-ed4b-4911-a821-d94f178fb067 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3671242622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3671242622 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2586745095 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27466495 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 04:32:03 PM PDT 24 |
| Finished | Aug 16 04:32:03 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-75512574-7b47-46b1-8592-95e43f59bc03 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2586745095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2586745095 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.417933922 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28878819 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:31:32 PM PDT 24 |
| Finished | Aug 16 04:31:33 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-b7b7ec80-6561-4639-83e2-d59ad0627d20 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=417933922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.417933922 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3408121783 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 28670685 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 04:31:31 PM PDT 24 |
| Finished | Aug 16 04:31:32 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-be5e5c92-2156-4340-a6a7-ab618db29114 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3408121783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3408121783 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.812792065 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26735265 ps |
| CPU time | 0.41 seconds |
| Started | Aug 16 04:31:41 PM PDT 24 |
| Finished | Aug 16 04:31:41 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-a3dfc512-51f2-4141-88d4-08baecfc4722 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=812792065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.812792065 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4137270846 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26420344 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:32:07 PM PDT 24 |
| Finished | Aug 16 04:32:07 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-c21520b1-408f-4248-b5ae-43c1ac073401 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4137270846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4137270846 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2012321344 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26445882 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:32:00 PM PDT 24 |
| Finished | Aug 16 04:32:06 PM PDT 24 |
| Peak memory | 145428 kb |
| Host | smart-edcf02fd-5359-4a9e-9dd2-fd3849849132 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2012321344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2012321344 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3107079373 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 27736332 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 04:31:45 PM PDT 24 |
| Finished | Aug 16 04:31:50 PM PDT 24 |
| Peak memory | 145288 kb |
| Host | smart-8265dd5b-d43d-4d6c-86ed-b5b2764a0be4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3107079373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3107079373 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.448080764 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 27547723 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 04:32:01 PM PDT 24 |
| Finished | Aug 16 04:32:02 PM PDT 24 |
| Peak memory | 145360 kb |
| Host | smart-74cd3626-7e52-4236-93cf-d301535f01d3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=448080764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.448080764 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2627171560 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28090409 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:31:32 PM PDT 24 |
| Finished | Aug 16 04:31:33 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-e9c99850-5fd1-493f-a17c-c45d16fa0f57 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2627171560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2627171560 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2932512801 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27147559 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:31:48 PM PDT 24 |
| Finished | Aug 16 04:31:48 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-946b9a90-9d0a-4fca-82c5-baa0723a79a6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2932512801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2932512801 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1643764468 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26485919 ps |
| CPU time | 0.42 seconds |
| Started | Aug 16 04:32:13 PM PDT 24 |
| Finished | Aug 16 04:32:14 PM PDT 24 |
| Peak memory | 144316 kb |
| Host | smart-94b56d62-e1d4-44cc-849d-a9a766eea5f5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1643764468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1643764468 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.941608835 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 29673651 ps |
| CPU time | 0.42 seconds |
| Started | Aug 16 04:32:16 PM PDT 24 |
| Finished | Aug 16 04:32:17 PM PDT 24 |
| Peak memory | 145424 kb |
| Host | smart-b76447a6-56bc-4686-8da7-4dd8f92a1be2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=941608835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.941608835 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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