| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.92 | 88.92 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/7.prim_async_alert.2855759396 |
| 92.05 | 3.13 | 100.00 | 0.00 | 91.67 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/15.prim_sync_alert.2546395549 |
| 94.15 | 2.11 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2153907481 |
| 94.50 | 0.35 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/default/1.prim_async_alert.680274998 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3203904276 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/17.prim_sync_alert.252394767 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.4121757192 |
| /workspace/coverage/default/10.prim_async_alert.927418730 |
| /workspace/coverage/default/11.prim_async_alert.3908976051 |
| /workspace/coverage/default/12.prim_async_alert.126287244 |
| /workspace/coverage/default/13.prim_async_alert.2755937818 |
| /workspace/coverage/default/14.prim_async_alert.2755976225 |
| /workspace/coverage/default/15.prim_async_alert.2870110285 |
| /workspace/coverage/default/16.prim_async_alert.3615284951 |
| /workspace/coverage/default/17.prim_async_alert.3652722467 |
| /workspace/coverage/default/18.prim_async_alert.1286410779 |
| /workspace/coverage/default/19.prim_async_alert.1567148070 |
| /workspace/coverage/default/2.prim_async_alert.3317797595 |
| /workspace/coverage/default/3.prim_async_alert.2600314908 |
| /workspace/coverage/default/4.prim_async_alert.4112989420 |
| /workspace/coverage/default/5.prim_async_alert.3733161537 |
| /workspace/coverage/default/6.prim_async_alert.4189910734 |
| /workspace/coverage/default/8.prim_async_alert.4136441907 |
| /workspace/coverage/default/9.prim_async_alert.2912227531 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3363246599 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3878799892 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3356947265 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.780247852 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.906770027 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1387070804 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2603802438 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1075824812 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1518678649 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.415855586 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3507618765 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.235981619 |
| /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1555605466 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3871608377 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2005834406 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1458650602 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4085466445 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.81582256 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.2059364327 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.59020759 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.3456003572 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.1882096965 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.72766068 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.874640535 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.1114905846 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.3395009455 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.2112479206 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.28292487 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2290974729 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.122384610 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.203102580 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.3839293873 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.477569219 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.3080748246 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.3006619802 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.894379915 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.963250415 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2519138926 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2049812391 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4183970214 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3638471062 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3041476838 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.902522324 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1785868702 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.507604026 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.805416340 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2923292232 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1579574011 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.485916834 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3674001440 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3054195908 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1865753144 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3432829063 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.384772219 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3723545861 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3565607083 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_async_alert.126287244 | Aug 17 06:20:28 PM PDT 24 | Aug 17 06:20:28 PM PDT 24 | 10724491 ps | ||
| T2 | /workspace/coverage/default/4.prim_async_alert.4112989420 | Aug 17 06:20:16 PM PDT 24 | Aug 17 06:20:17 PM PDT 24 | 10489404 ps | ||
| T3 | /workspace/coverage/default/14.prim_async_alert.2755976225 | Aug 17 06:20:19 PM PDT 24 | Aug 17 06:20:19 PM PDT 24 | 11114364 ps | ||
| T18 | /workspace/coverage/default/17.prim_async_alert.3652722467 | Aug 17 06:20:31 PM PDT 24 | Aug 17 06:20:31 PM PDT 24 | 11123798 ps | ||
| T12 | /workspace/coverage/default/1.prim_async_alert.680274998 | Aug 17 06:20:20 PM PDT 24 | Aug 17 06:20:21 PM PDT 24 | 12059363 ps | ||
| T19 | /workspace/coverage/default/16.prim_async_alert.3615284951 | Aug 17 06:20:20 PM PDT 24 | Aug 17 06:20:21 PM PDT 24 | 11460678 ps | ||
| T20 | /workspace/coverage/default/9.prim_async_alert.2912227531 | Aug 17 06:20:05 PM PDT 24 | Aug 17 06:20:05 PM PDT 24 | 11314179 ps | ||
| T21 | /workspace/coverage/default/11.prim_async_alert.3908976051 | Aug 17 06:20:06 PM PDT 24 | Aug 17 06:20:06 PM PDT 24 | 10436387 ps | ||
| T7 | /workspace/coverage/default/19.prim_async_alert.1567148070 | Aug 17 06:20:02 PM PDT 24 | Aug 17 06:20:03 PM PDT 24 | 11315369 ps | ||
| T13 | /workspace/coverage/default/7.prim_async_alert.2855759396 | Aug 17 06:20:04 PM PDT 24 | Aug 17 06:20:05 PM PDT 24 | 12369564 ps | ||
| T14 | /workspace/coverage/default/6.prim_async_alert.4189910734 | Aug 17 06:19:59 PM PDT 24 | Aug 17 06:20:00 PM PDT 24 | 11041979 ps | ||
| T8 | /workspace/coverage/default/15.prim_async_alert.2870110285 | Aug 17 06:20:23 PM PDT 24 | Aug 17 06:20:24 PM PDT 24 | 10718962 ps | ||
| T46 | /workspace/coverage/default/2.prim_async_alert.3317797595 | Aug 17 06:20:12 PM PDT 24 | Aug 17 06:20:13 PM PDT 24 | 10312479 ps | ||
| T39 | /workspace/coverage/default/13.prim_async_alert.2755937818 | Aug 17 06:20:03 PM PDT 24 | Aug 17 06:20:04 PM PDT 24 | 11684867 ps | ||
| T22 | /workspace/coverage/default/5.prim_async_alert.3733161537 | Aug 17 06:20:21 PM PDT 24 | Aug 17 06:20:22 PM PDT 24 | 11965077 ps | ||
| T16 | /workspace/coverage/default/10.prim_async_alert.927418730 | Aug 17 06:20:04 PM PDT 24 | Aug 17 06:20:05 PM PDT 24 | 11087590 ps | ||
| T23 | /workspace/coverage/default/8.prim_async_alert.4136441907 | Aug 17 06:20:32 PM PDT 24 | Aug 17 06:20:33 PM PDT 24 | 11644102 ps | ||
| T47 | /workspace/coverage/default/3.prim_async_alert.2600314908 | Aug 17 06:20:18 PM PDT 24 | Aug 17 06:20:19 PM PDT 24 | 11457040 ps | ||
| T48 | /workspace/coverage/default/18.prim_async_alert.1286410779 | Aug 17 06:20:29 PM PDT 24 | Aug 17 06:20:30 PM PDT 24 | 11093353 ps | ||
| T24 | /workspace/coverage/default/0.prim_async_alert.4121757192 | Aug 17 06:19:56 PM PDT 24 | Aug 17 06:19:57 PM PDT 24 | 11536561 ps | ||
| T40 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3356947265 | Aug 17 04:21:29 PM PDT 24 | Aug 17 04:21:29 PM PDT 24 | 28438208 ps | ||
| T4 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2603802438 | Aug 17 04:24:54 PM PDT 24 | Aug 17 04:24:55 PM PDT 24 | 28623290 ps | ||
| T17 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1458650602 | Aug 17 04:21:34 PM PDT 24 | Aug 17 04:21:35 PM PDT 24 | 30550662 ps | ||
| T41 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2005834406 | Aug 17 04:20:27 PM PDT 24 | Aug 17 04:20:28 PM PDT 24 | 28071912 ps | ||
| T42 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4085466445 | Aug 17 04:21:29 PM PDT 24 | Aug 17 04:21:30 PM PDT 24 | 29791560 ps | ||
| T15 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2153907481 | Aug 17 04:21:28 PM PDT 24 | Aug 17 04:21:29 PM PDT 24 | 30568307 ps | ||
| T43 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3878799892 | Aug 17 04:21:28 PM PDT 24 | Aug 17 04:21:29 PM PDT 24 | 28541529 ps | ||
| T44 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1518678649 | Aug 17 04:21:28 PM PDT 24 | Aug 17 04:21:29 PM PDT 24 | 30381472 ps | ||
| T45 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.780247852 | Aug 17 04:25:07 PM PDT 24 | Aug 17 04:25:07 PM PDT 24 | 29568480 ps | ||
| T5 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3203904276 | Aug 17 04:21:28 PM PDT 24 | Aug 17 04:21:29 PM PDT 24 | 30508253 ps | ||
| T49 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.81582256 | Aug 17 04:21:28 PM PDT 24 | Aug 17 04:21:29 PM PDT 24 | 28678065 ps | ||
| T50 | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1555605466 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:20:26 PM PDT 24 | 29600412 ps | ||
| T51 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1075824812 | Aug 17 04:24:57 PM PDT 24 | Aug 17 04:24:57 PM PDT 24 | 31349989 ps | ||
| T52 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.906770027 | Aug 17 04:25:10 PM PDT 24 | Aug 17 04:25:11 PM PDT 24 | 30560825 ps | ||
| T53 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3871608377 | Aug 17 04:21:34 PM PDT 24 | Aug 17 04:21:34 PM PDT 24 | 29057215 ps | ||
| T54 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.415855586 | Aug 17 04:25:10 PM PDT 24 | Aug 17 04:25:11 PM PDT 24 | 29567502 ps | ||
| T55 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3507618765 | Aug 17 04:22:02 PM PDT 24 | Aug 17 04:22:02 PM PDT 24 | 31474978 ps | ||
| T56 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1387070804 | Aug 17 04:22:33 PM PDT 24 | Aug 17 04:22:34 PM PDT 24 | 30854780 ps | ||
| T57 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.235981619 | Aug 17 04:21:27 PM PDT 24 | Aug 17 04:21:28 PM PDT 24 | 29557423 ps | ||
| T58 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3363246599 | Aug 17 04:20:27 PM PDT 24 | Aug 17 04:20:28 PM PDT 24 | 31534001 ps | ||
| T25 | /workspace/coverage/sync_alert/14.prim_sync_alert.1114905846 | Aug 17 04:30:14 PM PDT 24 | Aug 17 04:30:15 PM PDT 24 | 8420813 ps | ||
| T34 | /workspace/coverage/sync_alert/15.prim_sync_alert.2546395549 | Aug 17 04:22:22 PM PDT 24 | Aug 17 04:22:23 PM PDT 24 | 8873060 ps | ||
| T35 | /workspace/coverage/sync_alert/4.prim_sync_alert.203102580 | Aug 17 04:22:34 PM PDT 24 | Aug 17 04:22:34 PM PDT 24 | 9429697 ps | ||
| T36 | /workspace/coverage/sync_alert/2.prim_sync_alert.2290974729 | Aug 17 04:21:15 PM PDT 24 | Aug 17 04:21:16 PM PDT 24 | 9382203 ps | ||
| T26 | /workspace/coverage/sync_alert/9.prim_sync_alert.894379915 | Aug 17 04:22:48 PM PDT 24 | Aug 17 04:22:48 PM PDT 24 | 8892025 ps | ||
| T27 | /workspace/coverage/sync_alert/12.prim_sync_alert.72766068 | Aug 17 04:25:12 PM PDT 24 | Aug 17 04:25:13 PM PDT 24 | 8063697 ps | ||
| T37 | /workspace/coverage/sync_alert/5.prim_sync_alert.3839293873 | Aug 17 04:24:54 PM PDT 24 | Aug 17 04:24:55 PM PDT 24 | 9541480 ps | ||
| T28 | /workspace/coverage/sync_alert/3.prim_sync_alert.122384610 | Aug 17 04:25:10 PM PDT 24 | Aug 17 04:25:11 PM PDT 24 | 10320958 ps | ||
| T38 | /workspace/coverage/sync_alert/16.prim_sync_alert.3395009455 | Aug 17 04:23:17 PM PDT 24 | Aug 17 04:23:18 PM PDT 24 | 8254011 ps | ||
| T29 | /workspace/coverage/sync_alert/13.prim_sync_alert.874640535 | Aug 17 04:23:28 PM PDT 24 | Aug 17 04:23:28 PM PDT 24 | 8733518 ps | ||
| T59 | /workspace/coverage/sync_alert/1.prim_sync_alert.59020759 | Aug 17 04:24:57 PM PDT 24 | Aug 17 04:24:57 PM PDT 24 | 9695856 ps | ||
| T60 | /workspace/coverage/sync_alert/11.prim_sync_alert.1882096965 | Aug 17 04:22:55 PM PDT 24 | Aug 17 04:22:56 PM PDT 24 | 8565924 ps | ||
| T61 | /workspace/coverage/sync_alert/0.prim_sync_alert.2059364327 | Aug 17 04:24:57 PM PDT 24 | Aug 17 04:24:57 PM PDT 24 | 9764734 ps | ||
| T62 | /workspace/coverage/sync_alert/7.prim_sync_alert.3080748246 | Aug 17 04:21:12 PM PDT 24 | Aug 17 04:21:12 PM PDT 24 | 9241729 ps | ||
| T9 | /workspace/coverage/sync_alert/6.prim_sync_alert.477569219 | Aug 17 04:23:45 PM PDT 24 | Aug 17 04:23:45 PM PDT 24 | 8806869 ps | ||
| T63 | /workspace/coverage/sync_alert/18.prim_sync_alert.2112479206 | Aug 17 04:30:19 PM PDT 24 | Aug 17 04:30:19 PM PDT 24 | 9207098 ps | ||
| T10 | /workspace/coverage/sync_alert/17.prim_sync_alert.252394767 | Aug 17 04:30:20 PM PDT 24 | Aug 17 04:30:20 PM PDT 24 | 10202263 ps | ||
| T30 | /workspace/coverage/sync_alert/19.prim_sync_alert.28292487 | Aug 17 04:30:11 PM PDT 24 | Aug 17 04:30:12 PM PDT 24 | 9158584 ps | ||
| T31 | /workspace/coverage/sync_alert/8.prim_sync_alert.3006619802 | Aug 17 04:21:11 PM PDT 24 | Aug 17 04:21:12 PM PDT 24 | 9538457 ps | ||
| T32 | /workspace/coverage/sync_alert/10.prim_sync_alert.3456003572 | Aug 17 04:23:16 PM PDT 24 | Aug 17 04:23:16 PM PDT 24 | 9739019 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3723545861 | Aug 17 04:21:43 PM PDT 24 | Aug 17 04:21:44 PM PDT 24 | 29509174 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3638471062 | Aug 17 04:31:07 PM PDT 24 | Aug 17 04:31:08 PM PDT 24 | 28023880 ps | ||
| T33 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3674001440 | Aug 17 04:22:23 PM PDT 24 | Aug 17 04:22:24 PM PDT 24 | 27682659 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2519138926 | Aug 17 04:25:40 PM PDT 24 | Aug 17 04:25:40 PM PDT 24 | 27958220 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1579574011 | Aug 17 04:31:14 PM PDT 24 | Aug 17 04:31:14 PM PDT 24 | 28004278 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.384772219 | Aug 17 04:25:32 PM PDT 24 | Aug 17 04:25:34 PM PDT 24 | 26857119 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.507604026 | Aug 17 04:30:59 PM PDT 24 | Aug 17 04:30:59 PM PDT 24 | 29265488 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.902522324 | Aug 17 04:30:45 PM PDT 24 | Aug 17 04:30:46 PM PDT 24 | 29214481 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4183970214 | Aug 17 04:31:00 PM PDT 24 | Aug 17 04:31:01 PM PDT 24 | 27086891 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3041476838 | Aug 17 04:30:59 PM PDT 24 | Aug 17 04:31:00 PM PDT 24 | 27851143 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3432829063 | Aug 17 04:25:33 PM PDT 24 | Aug 17 04:25:34 PM PDT 24 | 28473938 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3565607083 | Aug 17 04:25:46 PM PDT 24 | Aug 17 04:25:46 PM PDT 24 | 27705511 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3054195908 | Aug 17 04:25:14 PM PDT 24 | Aug 17 04:25:15 PM PDT 24 | 28374009 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2923292232 | Aug 17 04:31:08 PM PDT 24 | Aug 17 04:31:08 PM PDT 24 | 25982889 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.485916834 | Aug 17 04:21:06 PM PDT 24 | Aug 17 04:21:07 PM PDT 24 | 27508854 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2049812391 | Aug 17 04:31:10 PM PDT 24 | Aug 17 04:31:11 PM PDT 24 | 27483266 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.963250415 | Aug 17 04:25:04 PM PDT 24 | Aug 17 04:25:05 PM PDT 24 | 27861585 ps | ||
| T78 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1865753144 | Aug 17 04:21:02 PM PDT 24 | Aug 17 04:21:02 PM PDT 24 | 26444613 ps | ||
| T79 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1785868702 | Aug 17 04:31:27 PM PDT 24 | Aug 17 04:31:27 PM PDT 24 | 27213662 ps | ||
| T80 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.805416340 | Aug 17 04:31:12 PM PDT 24 | Aug 17 04:31:13 PM PDT 24 | 29336691 ps |
| Test location | /workspace/coverage/default/7.prim_async_alert.2855759396 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12369564 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 06:20:04 PM PDT 24 |
| Finished | Aug 17 06:20:05 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-f590da91-defe-4c58-9459-a1475baf85fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2855759396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2855759396 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.2546395549 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8873060 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:22:22 PM PDT 24 |
| Finished | Aug 17 04:22:23 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-f7d3a5eb-9218-46a8-b4b3-3d7bf2525d6f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2546395549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2546395549 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2153907481 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 30568307 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:21:28 PM PDT 24 |
| Finished | Aug 17 04:21:29 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-e85c6764-21ac-45e2-9f49-3b03346aaaee |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2153907481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2153907481 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.680274998 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12059363 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 06:20:20 PM PDT 24 |
| Finished | Aug 17 06:20:21 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-a68874e5-7be9-4504-9cdf-57b09470f717 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680274998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.680274998 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3203904276 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30508253 ps |
| CPU time | 0.44 seconds |
| Started | Aug 17 04:21:28 PM PDT 24 |
| Finished | Aug 17 04:21:29 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-057f69da-9346-4edb-9b30-d3b374e2b173 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3203904276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3203904276 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.252394767 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10202263 ps |
| CPU time | 0.36 seconds |
| Started | Aug 17 04:30:20 PM PDT 24 |
| Finished | Aug 17 04:30:20 PM PDT 24 |
| Peak memory | 145244 kb |
| Host | smart-05fb975e-fa3f-4010-9307-720f50b81054 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=252394767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.252394767 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.4121757192 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11536561 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 06:19:56 PM PDT 24 |
| Finished | Aug 17 06:19:57 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-6a47e7c2-a2fd-44f3-9f6b-ae06b6401192 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121757192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.4121757192 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.927418730 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11087590 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 06:20:04 PM PDT 24 |
| Finished | Aug 17 06:20:05 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-0f4a7295-da3b-47cb-8c4a-3e85b1db4903 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927418730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.927418730 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.3908976051 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10436387 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 06:20:06 PM PDT 24 |
| Finished | Aug 17 06:20:06 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-30ff3902-8345-45e8-8137-c2e822b968e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908976051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3908976051 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.126287244 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10724491 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 06:20:28 PM PDT 24 |
| Finished | Aug 17 06:20:28 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-af06a47e-0ce7-4d27-8b11-c16bba631c74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126287244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.126287244 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.2755937818 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11684867 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 06:20:03 PM PDT 24 |
| Finished | Aug 17 06:20:04 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-01197c38-d1c0-48ce-aee9-d2fda67f319d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755937818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.2755937818 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.2755976225 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11114364 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 06:20:19 PM PDT 24 |
| Finished | Aug 17 06:20:19 PM PDT 24 |
| Peak memory | 145756 kb |
| Host | smart-1f7a72a6-7b98-4793-b9d0-140c13372e92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755976225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2755976225 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.2870110285 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10718962 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 06:20:23 PM PDT 24 |
| Finished | Aug 17 06:20:24 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-7c96182b-a721-42f2-b6a2-daa747fd7587 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870110285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2870110285 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.3615284951 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11460678 ps |
| CPU time | 0.43 seconds |
| Started | Aug 17 06:20:20 PM PDT 24 |
| Finished | Aug 17 06:20:21 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-863789f9-d379-4829-b6d2-eb1031aa349b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615284951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3615284951 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.3652722467 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11123798 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 06:20:31 PM PDT 24 |
| Finished | Aug 17 06:20:31 PM PDT 24 |
| Peak memory | 145788 kb |
| Host | smart-026bbfa5-5267-45e3-9143-94a2e36f8ba8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652722467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3652722467 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1286410779 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11093353 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 06:20:29 PM PDT 24 |
| Finished | Aug 17 06:20:30 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-98bc76e2-93fe-4be3-9a61-faf0aeece17a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286410779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1286410779 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.1567148070 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11315369 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 06:20:02 PM PDT 24 |
| Finished | Aug 17 06:20:03 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-b253cf4c-16ec-4438-8a84-dde511bd1540 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1567148070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1567148070 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3317797595 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10312479 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 06:20:12 PM PDT 24 |
| Finished | Aug 17 06:20:13 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-d1876ee3-dd45-4540-a1d0-32b5784a7466 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317797595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3317797595 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.2600314908 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11457040 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 06:20:18 PM PDT 24 |
| Finished | Aug 17 06:20:19 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-a90f967b-552d-4a28-a8ad-a56eaa9649eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600314908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2600314908 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.4112989420 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10489404 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 06:20:16 PM PDT 24 |
| Finished | Aug 17 06:20:17 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-822c8d77-7033-4eb9-9d12-7d57bf6c643e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112989420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.4112989420 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.3733161537 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11965077 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 06:20:21 PM PDT 24 |
| Finished | Aug 17 06:20:22 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-653baaf6-46a8-497e-8a09-4a5b00a88233 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733161537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3733161537 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.4189910734 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11041979 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 06:19:59 PM PDT 24 |
| Finished | Aug 17 06:20:00 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-385189e5-7d7f-4d57-8da3-92ee2a981354 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4189910734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.4189910734 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.4136441907 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11644102 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 06:20:32 PM PDT 24 |
| Finished | Aug 17 06:20:33 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-9557e6e2-5e45-4e56-aeb5-9f3f703b53ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136441907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4136441907 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.2912227531 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11314179 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 06:20:05 PM PDT 24 |
| Finished | Aug 17 06:20:05 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-9d10f1c7-e1e7-4d2a-a39d-783b91c6e92c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912227531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2912227531 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3363246599 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 31534001 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:20:27 PM PDT 24 |
| Finished | Aug 17 04:20:28 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-0990493e-4efe-480f-a1e6-f02291a2fc46 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3363246599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3363246599 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3878799892 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 28541529 ps |
| CPU time | 0.46 seconds |
| Started | Aug 17 04:21:28 PM PDT 24 |
| Finished | Aug 17 04:21:29 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-9ed1746c-98bf-455b-aa37-d0c3d8e60c6c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3878799892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3878799892 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3356947265 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 28438208 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:21:29 PM PDT 24 |
| Finished | Aug 17 04:21:29 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-634f7e14-3853-4cd3-9c4c-535dc1509185 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3356947265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3356947265 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.780247852 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29568480 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:25:07 PM PDT 24 |
| Finished | Aug 17 04:25:07 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-c027ab36-8faf-469a-9034-81d82bfd4951 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=780247852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.780247852 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.906770027 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30560825 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:25:10 PM PDT 24 |
| Finished | Aug 17 04:25:11 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-8a2529cc-19b7-4aad-bbd6-9d5b90ef6541 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=906770027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.906770027 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.1387070804 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30854780 ps |
| CPU time | 0.45 seconds |
| Started | Aug 17 04:22:33 PM PDT 24 |
| Finished | Aug 17 04:22:34 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-70058030-c5a1-4255-9b1a-d4b91624d910 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1387070804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.1387070804 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2603802438 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28623290 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:24:54 PM PDT 24 |
| Finished | Aug 17 04:24:55 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-65f1fc6d-125c-4bb0-9ac4-8ffa60bacf64 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2603802438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2603802438 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1075824812 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31349989 ps |
| CPU time | 0.43 seconds |
| Started | Aug 17 04:24:57 PM PDT 24 |
| Finished | Aug 17 04:24:57 PM PDT 24 |
| Peak memory | 144748 kb |
| Host | smart-3f1aad2c-901d-480c-b641-b3e83bab7386 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1075824812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1075824812 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1518678649 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30381472 ps |
| CPU time | 0.43 seconds |
| Started | Aug 17 04:21:28 PM PDT 24 |
| Finished | Aug 17 04:21:29 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-b98180f7-8d64-4409-bdb5-6e50f15718ee |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1518678649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1518678649 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.415855586 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 29567502 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:25:10 PM PDT 24 |
| Finished | Aug 17 04:25:11 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-8f291b34-83cf-4f38-a4bc-30db795a0b19 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=415855586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.415855586 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3507618765 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 31474978 ps |
| CPU time | 0.43 seconds |
| Started | Aug 17 04:22:02 PM PDT 24 |
| Finished | Aug 17 04:22:02 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-9e8ce941-052e-4a3b-b05b-65f57abbc95d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3507618765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3507618765 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.235981619 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 29557423 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:21:27 PM PDT 24 |
| Finished | Aug 17 04:21:28 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-6c647863-b16f-4609-a072-c49504ace1fc |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=235981619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.235981619 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1555605466 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 29600412 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:20:26 PM PDT 24 |
| Finished | Aug 17 04:20:26 PM PDT 24 |
| Peak memory | 146200 kb |
| Host | smart-9a676a60-5ee8-43dc-9913-f93c8d077deb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1555605466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1555605466 |
| Directory | /workspace/3.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3871608377 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29057215 ps |
| CPU time | 0.41 seconds |
| Started | Aug 17 04:21:34 PM PDT 24 |
| Finished | Aug 17 04:21:34 PM PDT 24 |
| Peak memory | 144548 kb |
| Host | smart-f8b183b7-2073-4bd8-bb7d-939353e2930f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3871608377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3871608377 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2005834406 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 28071912 ps |
| CPU time | 0.44 seconds |
| Started | Aug 17 04:20:27 PM PDT 24 |
| Finished | Aug 17 04:20:28 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-b678e9f1-be8b-4c7f-ad9e-c547cae17030 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2005834406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2005834406 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1458650602 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 30550662 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:21:34 PM PDT 24 |
| Finished | Aug 17 04:21:35 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-6d3539a1-4047-44b9-8e59-5d70da0ca6cf |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1458650602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1458650602 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4085466445 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29791560 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:21:29 PM PDT 24 |
| Finished | Aug 17 04:21:30 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-0866677c-7015-4ed9-baaa-4bdfa460b6ec |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4085466445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.4085466445 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.81582256 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 28678065 ps |
| CPU time | 0.44 seconds |
| Started | Aug 17 04:21:28 PM PDT 24 |
| Finished | Aug 17 04:21:29 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-592e16a6-8d63-41fe-9b26-94bd4b95e833 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=81582256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.81582256 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2059364327 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9764734 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:24:57 PM PDT 24 |
| Finished | Aug 17 04:24:57 PM PDT 24 |
| Peak memory | 144300 kb |
| Host | smart-56eef1be-bbef-48ba-a4eb-07b0673d7343 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2059364327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2059364327 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.59020759 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9695856 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:24:57 PM PDT 24 |
| Finished | Aug 17 04:24:57 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-261f5216-c040-420a-9c1c-4a31fdb3841f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=59020759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.59020759 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.3456003572 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9739019 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:23:16 PM PDT 24 |
| Finished | Aug 17 04:23:16 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-7335212a-d403-462d-9c45-1c26fa302f04 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3456003572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3456003572 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.1882096965 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8565924 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:22:55 PM PDT 24 |
| Finished | Aug 17 04:22:56 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-bfb6ecdc-fe2b-42ed-9dce-20e9cbdf1930 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1882096965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1882096965 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.72766068 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8063697 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:25:12 PM PDT 24 |
| Finished | Aug 17 04:25:13 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-1b38b0d9-d275-4fb5-b35b-6cf584816336 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=72766068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.72766068 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.874640535 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8733518 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:23:28 PM PDT 24 |
| Finished | Aug 17 04:23:28 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-a8bfb64d-6fdc-4fb9-82a6-1d32d01ec846 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=874640535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.874640535 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.1114905846 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8420813 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:30:14 PM PDT 24 |
| Finished | Aug 17 04:30:15 PM PDT 24 |
| Peak memory | 145324 kb |
| Host | smart-1580094e-db94-469c-af97-ca887d8a91af |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1114905846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1114905846 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.3395009455 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8254011 ps |
| CPU time | 0.41 seconds |
| Started | Aug 17 04:23:17 PM PDT 24 |
| Finished | Aug 17 04:23:18 PM PDT 24 |
| Peak memory | 145420 kb |
| Host | smart-b7194e91-338e-4196-a361-840f149e3f7b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3395009455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3395009455 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.2112479206 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 9207098 ps |
| CPU time | 0.37 seconds |
| Started | Aug 17 04:30:19 PM PDT 24 |
| Finished | Aug 17 04:30:19 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-aefb9aeb-0b44-4dc3-8b49-a762ee4cff15 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2112479206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2112479206 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.28292487 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9158584 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:30:11 PM PDT 24 |
| Finished | Aug 17 04:30:12 PM PDT 24 |
| Peak memory | 145840 kb |
| Host | smart-63c2d394-0048-49d2-bdfb-8d786e18caa1 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=28292487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.28292487 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2290974729 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9382203 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:21:15 PM PDT 24 |
| Finished | Aug 17 04:21:16 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-f0315fc0-3804-4b32-b53f-0919f4994345 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2290974729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2290974729 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.122384610 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10320958 ps |
| CPU time | 0.37 seconds |
| Started | Aug 17 04:25:10 PM PDT 24 |
| Finished | Aug 17 04:25:11 PM PDT 24 |
| Peak memory | 146428 kb |
| Host | smart-584005f6-af71-4926-a885-c3e66f5a60fb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=122384610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.122384610 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.203102580 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9429697 ps |
| CPU time | 0.41 seconds |
| Started | Aug 17 04:22:34 PM PDT 24 |
| Finished | Aug 17 04:22:34 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-75beac4d-9bed-484e-b968-ebd1822e250b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=203102580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.203102580 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.3839293873 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9541480 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:24:54 PM PDT 24 |
| Finished | Aug 17 04:24:55 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-6b2668ea-f071-432c-9ea8-cf8ee58f2bef |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3839293873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3839293873 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.477569219 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8806869 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:23:45 PM PDT 24 |
| Finished | Aug 17 04:23:45 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-a359cd0e-50e8-4cd7-beb5-5f8728ecdfd5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=477569219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.477569219 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.3080748246 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 9241729 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:21:12 PM PDT 24 |
| Finished | Aug 17 04:21:12 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-ff64a84a-3941-40bf-bf8b-644e0322ebd3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3080748246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3080748246 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.3006619802 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9538457 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:21:11 PM PDT 24 |
| Finished | Aug 17 04:21:12 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-0d9a1571-7643-497c-a298-208b00d8544e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3006619802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3006619802 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.894379915 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8892025 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:22:48 PM PDT 24 |
| Finished | Aug 17 04:22:48 PM PDT 24 |
| Peak memory | 145380 kb |
| Host | smart-e6f42a85-0696-4d35-8e83-1ed9df5200ad |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=894379915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.894379915 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.963250415 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27861585 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:25:04 PM PDT 24 |
| Finished | Aug 17 04:25:05 PM PDT 24 |
| Peak memory | 145276 kb |
| Host | smart-7e33cdfb-1929-460c-adb5-25bd7df68e0a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=963250415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.963250415 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2519138926 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27958220 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:25:40 PM PDT 24 |
| Finished | Aug 17 04:25:40 PM PDT 24 |
| Peak memory | 146336 kb |
| Host | smart-327bc467-56a8-4825-88ac-6424efb49091 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2519138926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2519138926 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2049812391 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27483266 ps |
| CPU time | 0.41 seconds |
| Started | Aug 17 04:31:10 PM PDT 24 |
| Finished | Aug 17 04:31:11 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-5dc10f31-f1c0-4eda-b665-1818c4916e30 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2049812391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2049812391 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4183970214 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27086891 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:31:00 PM PDT 24 |
| Finished | Aug 17 04:31:01 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-7c31f0a6-d389-4dbc-acc8-53d2473f7adc |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4183970214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4183970214 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3638471062 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 28023880 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:31:07 PM PDT 24 |
| Finished | Aug 17 04:31:08 PM PDT 24 |
| Peak memory | 145456 kb |
| Host | smart-21f1dbbf-f2e5-4cc6-89da-6446ebefe93c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3638471062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3638471062 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3041476838 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27851143 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:30:59 PM PDT 24 |
| Finished | Aug 17 04:31:00 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-23ecefe2-7af9-44f2-8b53-ddda12aee505 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3041476838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3041476838 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.902522324 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 29214481 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:30:45 PM PDT 24 |
| Finished | Aug 17 04:30:46 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-d55ba851-9dfd-419e-83d8-5a8b249d5432 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=902522324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.902522324 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1785868702 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27213662 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:31:27 PM PDT 24 |
| Finished | Aug 17 04:31:27 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-b8007dd4-519d-458e-9686-37a07e765168 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1785868702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1785868702 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.507604026 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 29265488 ps |
| CPU time | 0.41 seconds |
| Started | Aug 17 04:30:59 PM PDT 24 |
| Finished | Aug 17 04:30:59 PM PDT 24 |
| Peak memory | 146316 kb |
| Host | smart-0f771c15-1984-47ba-a798-c319d529986f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=507604026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.507604026 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.805416340 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 29336691 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:31:12 PM PDT 24 |
| Finished | Aug 17 04:31:13 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-8d6e29e1-16db-4812-8949-e640c33c1d03 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=805416340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.805416340 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2923292232 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 25982889 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:31:08 PM PDT 24 |
| Finished | Aug 17 04:31:08 PM PDT 24 |
| Peak memory | 145324 kb |
| Host | smart-d56168c2-9cf4-4496-9095-daaa3c6381ab |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2923292232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2923292232 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1579574011 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 28004278 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:31:14 PM PDT 24 |
| Finished | Aug 17 04:31:14 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-0c19373a-00d8-46d7-a273-ee004bdff053 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1579574011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1579574011 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.485916834 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27508854 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:21:06 PM PDT 24 |
| Finished | Aug 17 04:21:07 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-a40b1855-9b7b-48d8-9d9a-483b22e19c29 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=485916834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.485916834 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3674001440 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 27682659 ps |
| CPU time | 0.45 seconds |
| Started | Aug 17 04:22:23 PM PDT 24 |
| Finished | Aug 17 04:22:24 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-0d6eb6e7-baf5-46d5-ae3c-dca3edca7e0d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3674001440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3674001440 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3054195908 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28374009 ps |
| CPU time | 0.43 seconds |
| Started | Aug 17 04:25:14 PM PDT 24 |
| Finished | Aug 17 04:25:15 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-d6072924-4e9c-44b2-a759-b22c3e0cd8d2 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3054195908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3054195908 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1865753144 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26444613 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:21:02 PM PDT 24 |
| Finished | Aug 17 04:21:02 PM PDT 24 |
| Peak memory | 145252 kb |
| Host | smart-78ba1d82-9cdb-40f4-a860-d55ceb167333 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1865753144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1865753144 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3432829063 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28473938 ps |
| CPU time | 0.43 seconds |
| Started | Aug 17 04:25:33 PM PDT 24 |
| Finished | Aug 17 04:25:34 PM PDT 24 |
| Peak memory | 146436 kb |
| Host | smart-439730a3-578a-4a1c-8d19-8b947ef4df8b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3432829063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3432829063 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.384772219 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26857119 ps |
| CPU time | 0.43 seconds |
| Started | Aug 17 04:25:32 PM PDT 24 |
| Finished | Aug 17 04:25:34 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-08349e3d-d731-4032-aca3-f6fdfe564b46 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=384772219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.384772219 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3723545861 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 29509174 ps |
| CPU time | 0.4 seconds |
| Started | Aug 17 04:21:43 PM PDT 24 |
| Finished | Aug 17 04:21:44 PM PDT 24 |
| Peak memory | 145316 kb |
| Host | smart-bfa2201f-8cb4-4081-a0a5-c4583f053e71 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3723545861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3723545861 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3565607083 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27705511 ps |
| CPU time | 0.45 seconds |
| Started | Aug 17 04:25:46 PM PDT 24 |
| Finished | Aug 17 04:25:46 PM PDT 24 |
| Peak memory | 146440 kb |
| Host | smart-4e2a8a51-9147-4967-a6f4-d1376bb6409a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3565607083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3565607083 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |