Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.28 88.28 100.00 100.00 93.75 93.75 96.43 96.43 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/1.prim_async_alert.3197863118
91.41 3.13 100.00 0.00 93.75 0.00 96.43 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/9.prim_sync_alert.2848151315
93.90 2.49 100.00 0.00 95.83 2.08 100.00 3.57 85.71 0.00 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2815572069
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/10.prim_async_alert.1399262862
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3570784276
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/0.prim_sync_alert.1009035634

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.447288334
/workspace/coverage/default/11.prim_async_alert.1682737687
/workspace/coverage/default/12.prim_async_alert.2155221192
/workspace/coverage/default/13.prim_async_alert.3883679691
/workspace/coverage/default/14.prim_async_alert.3902524892
/workspace/coverage/default/15.prim_async_alert.2687825503
/workspace/coverage/default/16.prim_async_alert.770828685
/workspace/coverage/default/17.prim_async_alert.3721765135
/workspace/coverage/default/18.prim_async_alert.1397743558
/workspace/coverage/default/19.prim_async_alert.1625763590
/workspace/coverage/default/2.prim_async_alert.2865830308
/workspace/coverage/default/3.prim_async_alert.1835226846
/workspace/coverage/default/4.prim_async_alert.3772022590
/workspace/coverage/default/5.prim_async_alert.3684096652
/workspace/coverage/default/6.prim_async_alert.3070544858
/workspace/coverage/default/7.prim_async_alert.2479151477
/workspace/coverage/default/8.prim_async_alert.2647122795
/workspace/coverage/default/9.prim_async_alert.3870491081
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3108438149
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.738948101
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.629449360
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2220711956
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1425226034
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4103555002
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.455515405
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3887678293
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1876207339
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1182617402
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3063947843
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.928971175
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2906512688
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3667726110
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3688213564
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1667977562
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.207737058
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2107148078
/workspace/coverage/sync_alert/1.prim_sync_alert.394145915
/workspace/coverage/sync_alert/10.prim_sync_alert.3261159726
/workspace/coverage/sync_alert/11.prim_sync_alert.1875223693
/workspace/coverage/sync_alert/12.prim_sync_alert.892178735
/workspace/coverage/sync_alert/13.prim_sync_alert.3767241897
/workspace/coverage/sync_alert/14.prim_sync_alert.80653024
/workspace/coverage/sync_alert/15.prim_sync_alert.156631708
/workspace/coverage/sync_alert/16.prim_sync_alert.2162715136
/workspace/coverage/sync_alert/17.prim_sync_alert.3919839772
/workspace/coverage/sync_alert/18.prim_sync_alert.672712672
/workspace/coverage/sync_alert/19.prim_sync_alert.1378313443
/workspace/coverage/sync_alert/2.prim_sync_alert.1243273495
/workspace/coverage/sync_alert/3.prim_sync_alert.2500762694
/workspace/coverage/sync_alert/4.prim_sync_alert.1561433643
/workspace/coverage/sync_alert/5.prim_sync_alert.3419032247
/workspace/coverage/sync_alert/6.prim_sync_alert.840422358
/workspace/coverage/sync_alert/7.prim_sync_alert.3148151751
/workspace/coverage/sync_alert/8.prim_sync_alert.1221224482
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3432614169
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2001156065
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.285685213
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1004923518
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2796019680
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1770037405
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4121859077
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2087431054
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1141861293
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3169147970
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3641731452
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2560798021
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4229222441
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2786413311
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.391383421
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.856331240
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2901727457
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2980097778
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3217732531
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1505242127



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/11.prim_async_alert.1682737687 Aug 18 05:03:30 PM PDT 24 Aug 18 05:03:30 PM PDT 24 10763926 ps
T2 /workspace/coverage/default/18.prim_async_alert.1397743558 Aug 18 05:03:27 PM PDT 24 Aug 18 05:03:28 PM PDT 24 11065799 ps
T3 /workspace/coverage/default/1.prim_async_alert.3197863118 Aug 18 05:03:28 PM PDT 24 Aug 18 05:03:28 PM PDT 24 11028368 ps
T16 /workspace/coverage/default/6.prim_async_alert.3070544858 Aug 18 05:03:30 PM PDT 24 Aug 18 05:03:31 PM PDT 24 10647007 ps
T7 /workspace/coverage/default/17.prim_async_alert.3721765135 Aug 18 05:03:30 PM PDT 24 Aug 18 05:03:30 PM PDT 24 11429312 ps
T8 /workspace/coverage/default/8.prim_async_alert.2647122795 Aug 18 05:03:27 PM PDT 24 Aug 18 05:03:27 PM PDT 24 10905887 ps
T19 /workspace/coverage/default/15.prim_async_alert.2687825503 Aug 18 05:03:31 PM PDT 24 Aug 18 05:03:31 PM PDT 24 10687434 ps
T9 /workspace/coverage/default/19.prim_async_alert.1625763590 Aug 18 05:03:29 PM PDT 24 Aug 18 05:03:30 PM PDT 24 10614051 ps
T20 /workspace/coverage/default/0.prim_async_alert.447288334 Aug 18 05:03:32 PM PDT 24 Aug 18 05:03:32 PM PDT 24 10488266 ps
T21 /workspace/coverage/default/12.prim_async_alert.2155221192 Aug 18 05:03:30 PM PDT 24 Aug 18 05:03:31 PM PDT 24 11181723 ps
T22 /workspace/coverage/default/5.prim_async_alert.3684096652 Aug 18 05:03:29 PM PDT 24 Aug 18 05:03:30 PM PDT 24 11182683 ps
T23 /workspace/coverage/default/2.prim_async_alert.2865830308 Aug 18 05:03:27 PM PDT 24 Aug 18 05:03:28 PM PDT 24 11093721 ps
T24 /workspace/coverage/default/4.prim_async_alert.3772022590 Aug 18 05:03:36 PM PDT 24 Aug 18 05:03:37 PM PDT 24 11212537 ps
T25 /workspace/coverage/default/7.prim_async_alert.2479151477 Aug 18 05:03:27 PM PDT 24 Aug 18 05:03:27 PM PDT 24 10667232 ps
T50 /workspace/coverage/default/9.prim_async_alert.3870491081 Aug 18 05:03:27 PM PDT 24 Aug 18 05:03:28 PM PDT 24 10219352 ps
T13 /workspace/coverage/default/14.prim_async_alert.3902524892 Aug 18 05:03:30 PM PDT 24 Aug 18 05:03:30 PM PDT 24 12154142 ps
T14 /workspace/coverage/default/10.prim_async_alert.1399262862 Aug 18 05:03:28 PM PDT 24 Aug 18 05:03:28 PM PDT 24 12617731 ps
T26 /workspace/coverage/default/16.prim_async_alert.770828685 Aug 18 05:03:31 PM PDT 24 Aug 18 05:03:31 PM PDT 24 10900008 ps
T17 /workspace/coverage/default/3.prim_async_alert.1835226846 Aug 18 05:03:29 PM PDT 24 Aug 18 05:03:30 PM PDT 24 10822925 ps
T51 /workspace/coverage/default/13.prim_async_alert.3883679691 Aug 18 05:03:37 PM PDT 24 Aug 18 05:03:37 PM PDT 24 11813350 ps
T15 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3108438149 Aug 18 05:17:55 PM PDT 24 Aug 18 05:17:55 PM PDT 24 30722979 ps
T18 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1425226034 Aug 18 05:17:57 PM PDT 24 Aug 18 05:17:57 PM PDT 24 29056910 ps
T27 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2815572069 Aug 18 05:17:52 PM PDT 24 Aug 18 05:17:53 PM PDT 24 29980287 ps
T44 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4103555002 Aug 18 05:18:00 PM PDT 24 Aug 18 05:18:01 PM PDT 24 30711911 ps
T45 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3667726110 Aug 18 05:17:56 PM PDT 24 Aug 18 05:17:57 PM PDT 24 28979505 ps
T46 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2107148078 Aug 18 05:17:55 PM PDT 24 Aug 18 05:17:55 PM PDT 24 30647844 ps
T47 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1182617402 Aug 18 05:17:56 PM PDT 24 Aug 18 05:17:57 PM PDT 24 30604515 ps
T48 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3063947843 Aug 18 05:17:55 PM PDT 24 Aug 18 05:17:55 PM PDT 24 29368010 ps
T4 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2906512688 Aug 18 05:17:57 PM PDT 24 Aug 18 05:17:57 PM PDT 24 28197875 ps
T49 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3688213564 Aug 18 05:17:51 PM PDT 24 Aug 18 05:17:52 PM PDT 24 31952719 ps
T52 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1876207339 Aug 18 05:18:08 PM PDT 24 Aug 18 05:18:08 PM PDT 24 30669420 ps
T53 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.738948101 Aug 18 05:17:51 PM PDT 24 Aug 18 05:17:52 PM PDT 24 30380802 ps
T5 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3570784276 Aug 18 05:17:52 PM PDT 24 Aug 18 05:17:53 PM PDT 24 29764091 ps
T54 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.928971175 Aug 18 05:17:56 PM PDT 24 Aug 18 05:17:57 PM PDT 24 31241372 ps
T55 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3887678293 Aug 18 05:18:00 PM PDT 24 Aug 18 05:18:01 PM PDT 24 28861210 ps
T6 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.455515405 Aug 18 05:17:58 PM PDT 24 Aug 18 05:17:58 PM PDT 24 29873653 ps
T56 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2220711956 Aug 18 05:17:56 PM PDT 24 Aug 18 05:17:57 PM PDT 24 29481680 ps
T57 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1667977562 Aug 18 05:17:53 PM PDT 24 Aug 18 05:17:53 PM PDT 24 29952157 ps
T58 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.207737058 Aug 18 05:17:54 PM PDT 24 Aug 18 05:17:55 PM PDT 24 30806437 ps
T59 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.629449360 Aug 18 05:17:55 PM PDT 24 Aug 18 05:17:55 PM PDT 24 30460235 ps
T10 /workspace/coverage/sync_alert/13.prim_sync_alert.3767241897 Aug 18 05:17:59 PM PDT 24 Aug 18 05:17:59 PM PDT 24 9270776 ps
T37 /workspace/coverage/sync_alert/9.prim_sync_alert.2848151315 Aug 18 05:17:56 PM PDT 24 Aug 18 05:17:57 PM PDT 24 9617902 ps
T28 /workspace/coverage/sync_alert/11.prim_sync_alert.1875223693 Aug 18 05:17:54 PM PDT 24 Aug 18 05:17:54 PM PDT 24 8592855 ps
T38 /workspace/coverage/sync_alert/15.prim_sync_alert.156631708 Aug 18 05:17:57 PM PDT 24 Aug 18 05:17:58 PM PDT 24 9126011 ps
T29 /workspace/coverage/sync_alert/8.prim_sync_alert.1221224482 Aug 18 05:17:57 PM PDT 24 Aug 18 05:17:57 PM PDT 24 10180615 ps
T39 /workspace/coverage/sync_alert/2.prim_sync_alert.1243273495 Aug 18 05:17:57 PM PDT 24 Aug 18 05:17:57 PM PDT 24 9005584 ps
T40 /workspace/coverage/sync_alert/4.prim_sync_alert.1561433643 Aug 18 05:17:51 PM PDT 24 Aug 18 05:17:52 PM PDT 24 10121559 ps
T41 /workspace/coverage/sync_alert/16.prim_sync_alert.2162715136 Aug 18 05:18:02 PM PDT 24 Aug 18 05:18:02 PM PDT 24 9253105 ps
T42 /workspace/coverage/sync_alert/10.prim_sync_alert.3261159726 Aug 18 05:17:55 PM PDT 24 Aug 18 05:17:55 PM PDT 24 8714685 ps
T43 /workspace/coverage/sync_alert/17.prim_sync_alert.3919839772 Aug 18 05:18:02 PM PDT 24 Aug 18 05:18:02 PM PDT 24 9457566 ps
T60 /workspace/coverage/sync_alert/3.prim_sync_alert.2500762694 Aug 18 05:17:58 PM PDT 24 Aug 18 05:17:59 PM PDT 24 8666753 ps
T61 /workspace/coverage/sync_alert/6.prim_sync_alert.840422358 Aug 18 05:17:55 PM PDT 24 Aug 18 05:17:55 PM PDT 24 9959574 ps
T62 /workspace/coverage/sync_alert/14.prim_sync_alert.80653024 Aug 18 05:17:54 PM PDT 24 Aug 18 05:17:54 PM PDT 24 8209730 ps
T30 /workspace/coverage/sync_alert/19.prim_sync_alert.1378313443 Aug 18 05:18:07 PM PDT 24 Aug 18 05:18:07 PM PDT 24 9681925 ps
T11 /workspace/coverage/sync_alert/18.prim_sync_alert.672712672 Aug 18 05:18:14 PM PDT 24 Aug 18 05:18:15 PM PDT 24 9089550 ps
T12 /workspace/coverage/sync_alert/0.prim_sync_alert.1009035634 Aug 18 05:18:00 PM PDT 24 Aug 18 05:18:01 PM PDT 24 8534840 ps
T31 /workspace/coverage/sync_alert/12.prim_sync_alert.892178735 Aug 18 05:17:56 PM PDT 24 Aug 18 05:17:57 PM PDT 24 7914777 ps
T32 /workspace/coverage/sync_alert/7.prim_sync_alert.3148151751 Aug 18 05:17:58 PM PDT 24 Aug 18 05:17:58 PM PDT 24 8911677 ps
T63 /workspace/coverage/sync_alert/5.prim_sync_alert.3419032247 Aug 18 05:17:57 PM PDT 24 Aug 18 05:17:58 PM PDT 24 9545883 ps
T64 /workspace/coverage/sync_alert/1.prim_sync_alert.394145915 Aug 18 05:17:58 PM PDT 24 Aug 18 05:17:59 PM PDT 24 8999899 ps
T33 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3217732531 Aug 18 05:18:02 PM PDT 24 Aug 18 05:18:03 PM PDT 24 29187262 ps
T65 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1141861293 Aug 18 05:18:08 PM PDT 24 Aug 18 05:18:08 PM PDT 24 27799503 ps
T34 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1004923518 Aug 18 05:18:01 PM PDT 24 Aug 18 05:18:02 PM PDT 24 26869090 ps
T35 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2901727457 Aug 18 05:18:10 PM PDT 24 Aug 18 05:18:11 PM PDT 24 25837548 ps
T66 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2001156065 Aug 18 05:18:02 PM PDT 24 Aug 18 05:18:02 PM PDT 24 29106674 ps
T36 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.285685213 Aug 18 05:18:14 PM PDT 24 Aug 18 05:18:14 PM PDT 24 28286707 ps
T67 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3169147970 Aug 18 05:18:02 PM PDT 24 Aug 18 05:18:02 PM PDT 24 28573049 ps
T68 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4229222441 Aug 18 05:18:03 PM PDT 24 Aug 18 05:18:03 PM PDT 24 27556975 ps
T69 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2087431054 Aug 18 05:18:11 PM PDT 24 Aug 18 05:18:11 PM PDT 24 25661649 ps
T70 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2796019680 Aug 18 05:18:08 PM PDT 24 Aug 18 05:18:09 PM PDT 24 26398696 ps
T71 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2560798021 Aug 18 05:18:01 PM PDT 24 Aug 18 05:18:01 PM PDT 24 29323716 ps
T72 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.856331240 Aug 18 05:18:02 PM PDT 24 Aug 18 05:18:03 PM PDT 24 28228800 ps
T73 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3641731452 Aug 18 05:18:11 PM PDT 24 Aug 18 05:18:11 PM PDT 24 27333173 ps
T74 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.391383421 Aug 18 05:18:08 PM PDT 24 Aug 18 05:18:09 PM PDT 24 28014296 ps
T75 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4121859077 Aug 18 05:18:07 PM PDT 24 Aug 18 05:18:07 PM PDT 24 30455635 ps
T76 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3432614169 Aug 18 05:18:01 PM PDT 24 Aug 18 05:18:01 PM PDT 24 26680513 ps
T77 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2980097778 Aug 18 05:18:11 PM PDT 24 Aug 18 05:18:11 PM PDT 24 26664075 ps
T78 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1505242127 Aug 18 05:18:05 PM PDT 24 Aug 18 05:18:06 PM PDT 24 27810986 ps
T79 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2786413311 Aug 18 05:18:08 PM PDT 24 Aug 18 05:18:09 PM PDT 24 27285694 ps
T80 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1770037405 Aug 18 05:18:02 PM PDT 24 Aug 18 05:18:02 PM PDT 24 26890046 ps

Test location /workspace/coverage/default/1.prim_async_alert.3197863118
Short name T3
Test name
Test status
Simulation time 11028368 ps
CPU time 0.38 seconds
Started Aug 18 05:03:28 PM PDT 24
Finished Aug 18 05:03:28 PM PDT 24
Peak memory 145712 kb
Host smart-87f1eaa7-cd56-4434-b6d0-4b798eb4d5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197863118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.3197863118
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2848151315
Short name T37
Test name
Test status
Simulation time 9617902 ps
CPU time 0.39 seconds
Started Aug 18 05:17:56 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 145468 kb
Host smart-c825e5ca-e0b0-4a5d-8978-c9183d8d9720
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2848151315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2848151315
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2815572069
Short name T27
Test name
Test status
Simulation time 29980287 ps
CPU time 0.39 seconds
Started Aug 18 05:17:52 PM PDT 24
Finished Aug 18 05:17:53 PM PDT 24
Peak memory 145264 kb
Host smart-160ea520-470e-49c8-a359-9f7614c38510
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2815572069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2815572069
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1399262862
Short name T14
Test name
Test status
Simulation time 12617731 ps
CPU time 0.39 seconds
Started Aug 18 05:03:28 PM PDT 24
Finished Aug 18 05:03:28 PM PDT 24
Peak memory 145692 kb
Host smart-5226ac5c-2096-41d4-990d-8d5f4d4003a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399262862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1399262862
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3570784276
Short name T5
Test name
Test status
Simulation time 29764091 ps
CPU time 0.45 seconds
Started Aug 18 05:17:52 PM PDT 24
Finished Aug 18 05:17:53 PM PDT 24
Peak memory 145316 kb
Host smart-7aa09161-c5d6-4d90-9cff-17a6ed7a4a00
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3570784276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3570784276
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1009035634
Short name T12
Test name
Test status
Simulation time 8534840 ps
CPU time 0.39 seconds
Started Aug 18 05:18:00 PM PDT 24
Finished Aug 18 05:18:01 PM PDT 24
Peak memory 145472 kb
Host smart-e22ca320-36c6-44b9-a158-94ca0ad904e6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1009035634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1009035634
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.447288334
Short name T20
Test name
Test status
Simulation time 10488266 ps
CPU time 0.4 seconds
Started Aug 18 05:03:32 PM PDT 24
Finished Aug 18 05:03:32 PM PDT 24
Peak memory 145724 kb
Host smart-d74b5096-edd9-4242-83f1-11fbdbbe2ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447288334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.447288334
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1682737687
Short name T1
Test name
Test status
Simulation time 10763926 ps
CPU time 0.38 seconds
Started Aug 18 05:03:30 PM PDT 24
Finished Aug 18 05:03:30 PM PDT 24
Peak memory 145700 kb
Host smart-dc65c500-ca3a-4c93-a617-7c9b2042101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682737687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1682737687
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2155221192
Short name T21
Test name
Test status
Simulation time 11181723 ps
CPU time 0.39 seconds
Started Aug 18 05:03:30 PM PDT 24
Finished Aug 18 05:03:31 PM PDT 24
Peak memory 145636 kb
Host smart-303bdec1-0e81-48e5-8f69-0bbe68af74ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155221192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2155221192
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3883679691
Short name T51
Test name
Test status
Simulation time 11813350 ps
CPU time 0.38 seconds
Started Aug 18 05:03:37 PM PDT 24
Finished Aug 18 05:03:37 PM PDT 24
Peak memory 145780 kb
Host smart-4bc5cc3f-0750-4333-a320-d56670b19507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883679691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3883679691
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.3902524892
Short name T13
Test name
Test status
Simulation time 12154142 ps
CPU time 0.41 seconds
Started Aug 18 05:03:30 PM PDT 24
Finished Aug 18 05:03:30 PM PDT 24
Peak memory 145624 kb
Host smart-a0d229c0-0ea5-47f0-ae25-10dcb52a563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902524892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3902524892
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2687825503
Short name T19
Test name
Test status
Simulation time 10687434 ps
CPU time 0.38 seconds
Started Aug 18 05:03:31 PM PDT 24
Finished Aug 18 05:03:31 PM PDT 24
Peak memory 145724 kb
Host smart-eb70ec56-5cb1-4997-b92d-45fa5040391f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687825503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2687825503
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.770828685
Short name T26
Test name
Test status
Simulation time 10900008 ps
CPU time 0.43 seconds
Started Aug 18 05:03:31 PM PDT 24
Finished Aug 18 05:03:31 PM PDT 24
Peak memory 145716 kb
Host smart-a6655739-8bf3-4444-b347-324e546b5ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770828685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.770828685
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3721765135
Short name T7
Test name
Test status
Simulation time 11429312 ps
CPU time 0.39 seconds
Started Aug 18 05:03:30 PM PDT 24
Finished Aug 18 05:03:30 PM PDT 24
Peak memory 145692 kb
Host smart-49b17a85-b856-4855-a52f-f71ad9f00a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721765135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3721765135
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1397743558
Short name T2
Test name
Test status
Simulation time 11065799 ps
CPU time 0.39 seconds
Started Aug 18 05:03:27 PM PDT 24
Finished Aug 18 05:03:28 PM PDT 24
Peak memory 145676 kb
Host smart-065479e1-63e1-4820-bac6-4416d4a37709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397743558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1397743558
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1625763590
Short name T9
Test name
Test status
Simulation time 10614051 ps
CPU time 0.38 seconds
Started Aug 18 05:03:29 PM PDT 24
Finished Aug 18 05:03:30 PM PDT 24
Peak memory 145700 kb
Host smart-10cc6bae-eef7-4e38-b3ea-fbe6112bba43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625763590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1625763590
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2865830308
Short name T23
Test name
Test status
Simulation time 11093721 ps
CPU time 0.39 seconds
Started Aug 18 05:03:27 PM PDT 24
Finished Aug 18 05:03:28 PM PDT 24
Peak memory 145792 kb
Host smart-bca3432a-a5db-46f9-bc78-0d64cb3f5a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865830308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2865830308
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.1835226846
Short name T17
Test name
Test status
Simulation time 10822925 ps
CPU time 0.38 seconds
Started Aug 18 05:03:29 PM PDT 24
Finished Aug 18 05:03:30 PM PDT 24
Peak memory 145696 kb
Host smart-7dc3a567-6dcd-4775-a577-0a0c50cfe0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835226846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1835226846
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3772022590
Short name T24
Test name
Test status
Simulation time 11212537 ps
CPU time 0.4 seconds
Started Aug 18 05:03:36 PM PDT 24
Finished Aug 18 05:03:37 PM PDT 24
Peak memory 145580 kb
Host smart-df811561-4e27-47da-832d-00e14c33061e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772022590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3772022590
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3684096652
Short name T22
Test name
Test status
Simulation time 11182683 ps
CPU time 0.39 seconds
Started Aug 18 05:03:29 PM PDT 24
Finished Aug 18 05:03:30 PM PDT 24
Peak memory 145672 kb
Host smart-3310d299-05db-455a-869c-e176b259a022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684096652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3684096652
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3070544858
Short name T16
Test name
Test status
Simulation time 10647007 ps
CPU time 0.39 seconds
Started Aug 18 05:03:30 PM PDT 24
Finished Aug 18 05:03:31 PM PDT 24
Peak memory 145696 kb
Host smart-824448b4-813a-4691-ac0d-0e4f72d61b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070544858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3070544858
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2479151477
Short name T25
Test name
Test status
Simulation time 10667232 ps
CPU time 0.38 seconds
Started Aug 18 05:03:27 PM PDT 24
Finished Aug 18 05:03:27 PM PDT 24
Peak memory 145676 kb
Host smart-e0e7ed9e-7a3c-4f44-9f23-69438fec76eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479151477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2479151477
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2647122795
Short name T8
Test name
Test status
Simulation time 10905887 ps
CPU time 0.38 seconds
Started Aug 18 05:03:27 PM PDT 24
Finished Aug 18 05:03:27 PM PDT 24
Peak memory 145828 kb
Host smart-f1498070-9595-407f-99e9-8978ff833dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647122795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2647122795
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3870491081
Short name T50
Test name
Test status
Simulation time 10219352 ps
CPU time 0.39 seconds
Started Aug 18 05:03:27 PM PDT 24
Finished Aug 18 05:03:28 PM PDT 24
Peak memory 145680 kb
Host smart-7a1fe1d5-a178-4509-8bea-0237e07f1128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870491081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3870491081
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3108438149
Short name T15
Test name
Test status
Simulation time 30722979 ps
CPU time 0.4 seconds
Started Aug 18 05:17:55 PM PDT 24
Finished Aug 18 05:17:55 PM PDT 24
Peak memory 145352 kb
Host smart-0ae683aa-306a-42f3-92ae-368925e587d0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3108438149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3108438149
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.738948101
Short name T53
Test name
Test status
Simulation time 30380802 ps
CPU time 0.39 seconds
Started Aug 18 05:17:51 PM PDT 24
Finished Aug 18 05:17:52 PM PDT 24
Peak memory 145244 kb
Host smart-5f0da3b2-8852-4db2-8095-dfb7c553f616
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=738948101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.738948101
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.629449360
Short name T59
Test name
Test status
Simulation time 30460235 ps
CPU time 0.4 seconds
Started Aug 18 05:17:55 PM PDT 24
Finished Aug 18 05:17:55 PM PDT 24
Peak memory 145224 kb
Host smart-a25f4224-b427-47e3-89cf-c531b7360abd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=629449360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.629449360
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2220711956
Short name T56
Test name
Test status
Simulation time 29481680 ps
CPU time 0.4 seconds
Started Aug 18 05:17:56 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 145224 kb
Host smart-b1e6fb16-7052-44e6-a2c6-6ba5c947c43b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2220711956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2220711956
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.1425226034
Short name T18
Test name
Test status
Simulation time 29056910 ps
CPU time 0.4 seconds
Started Aug 18 05:17:57 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 145208 kb
Host smart-616f2166-da53-4db2-bb9a-d9af37642289
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1425226034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.1425226034
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4103555002
Short name T44
Test name
Test status
Simulation time 30711911 ps
CPU time 0.4 seconds
Started Aug 18 05:18:00 PM PDT 24
Finished Aug 18 05:18:01 PM PDT 24
Peak memory 145224 kb
Host smart-dc5d18e8-19d8-4690-bda6-d336fd2d35b8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4103555002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4103555002
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.455515405
Short name T6
Test name
Test status
Simulation time 29873653 ps
CPU time 0.41 seconds
Started Aug 18 05:17:58 PM PDT 24
Finished Aug 18 05:17:58 PM PDT 24
Peak memory 145188 kb
Host smart-eb0aacdb-02b3-495c-be3d-053853238ecc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=455515405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.455515405
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3887678293
Short name T55
Test name
Test status
Simulation time 28861210 ps
CPU time 0.41 seconds
Started Aug 18 05:18:00 PM PDT 24
Finished Aug 18 05:18:01 PM PDT 24
Peak memory 145228 kb
Host smart-6be4f830-8061-4a1e-8ab8-f2d1c2ba655c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3887678293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3887678293
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1876207339
Short name T52
Test name
Test status
Simulation time 30669420 ps
CPU time 0.4 seconds
Started Aug 18 05:18:08 PM PDT 24
Finished Aug 18 05:18:08 PM PDT 24
Peak memory 145316 kb
Host smart-ae14e3e3-76c6-46a7-9fb4-ce519e06de98
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1876207339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1876207339
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1182617402
Short name T47
Test name
Test status
Simulation time 30604515 ps
CPU time 0.4 seconds
Started Aug 18 05:17:56 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 145228 kb
Host smart-876f34aa-c250-4ab4-aea0-fd3b6fc39375
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1182617402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1182617402
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3063947843
Short name T48
Test name
Test status
Simulation time 29368010 ps
CPU time 0.42 seconds
Started Aug 18 05:17:55 PM PDT 24
Finished Aug 18 05:17:55 PM PDT 24
Peak memory 145144 kb
Host smart-a7fdda0d-e655-4969-bdca-4d6ad64991c8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3063947843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3063947843
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.928971175
Short name T54
Test name
Test status
Simulation time 31241372 ps
CPU time 0.41 seconds
Started Aug 18 05:17:56 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 145300 kb
Host smart-3493fe9c-fea2-450a-bdb3-c78beb9586d3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=928971175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.928971175
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2906512688
Short name T4
Test name
Test status
Simulation time 28197875 ps
CPU time 0.41 seconds
Started Aug 18 05:17:57 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 145308 kb
Host smart-47f9b0a9-a428-49a4-b78a-d900422b1d8a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2906512688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2906512688
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3667726110
Short name T45
Test name
Test status
Simulation time 28979505 ps
CPU time 0.38 seconds
Started Aug 18 05:17:56 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 145320 kb
Host smart-67cb1cd6-fc8f-4c87-b07d-2fa0ca6a39a3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3667726110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3667726110
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3688213564
Short name T49
Test name
Test status
Simulation time 31952719 ps
CPU time 0.38 seconds
Started Aug 18 05:17:51 PM PDT 24
Finished Aug 18 05:17:52 PM PDT 24
Peak memory 145284 kb
Host smart-5a4d78d5-e96a-4b0d-817b-ff2c34c35a4b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3688213564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3688213564
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1667977562
Short name T57
Test name
Test status
Simulation time 29952157 ps
CPU time 0.41 seconds
Started Aug 18 05:17:53 PM PDT 24
Finished Aug 18 05:17:53 PM PDT 24
Peak memory 145296 kb
Host smart-f2c8c59a-2e0c-48ad-9c1a-2b65243eece8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1667977562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1667977562
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.207737058
Short name T58
Test name
Test status
Simulation time 30806437 ps
CPU time 0.41 seconds
Started Aug 18 05:17:54 PM PDT 24
Finished Aug 18 05:17:55 PM PDT 24
Peak memory 145356 kb
Host smart-9bb18779-7a8c-41a4-86aa-07bdfdb7c8ca
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=207737058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.207737058
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2107148078
Short name T46
Test name
Test status
Simulation time 30647844 ps
CPU time 0.43 seconds
Started Aug 18 05:17:55 PM PDT 24
Finished Aug 18 05:17:55 PM PDT 24
Peak memory 145092 kb
Host smart-2b5a3b7b-fb47-4efc-b927-9abfdc34e777
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2107148078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2107148078
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.394145915
Short name T64
Test name
Test status
Simulation time 8999899 ps
CPU time 0.45 seconds
Started Aug 18 05:17:58 PM PDT 24
Finished Aug 18 05:17:59 PM PDT 24
Peak memory 145612 kb
Host smart-792082ac-0985-43b3-a016-a8e4fce30119
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=394145915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.394145915
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3261159726
Short name T42
Test name
Test status
Simulation time 8714685 ps
CPU time 0.4 seconds
Started Aug 18 05:17:55 PM PDT 24
Finished Aug 18 05:17:55 PM PDT 24
Peak memory 145596 kb
Host smart-1b962219-9096-4e03-b48b-15e8ac497268
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3261159726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3261159726
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1875223693
Short name T28
Test name
Test status
Simulation time 8592855 ps
CPU time 0.41 seconds
Started Aug 18 05:17:54 PM PDT 24
Finished Aug 18 05:17:54 PM PDT 24
Peak memory 145600 kb
Host smart-fcc498e1-2ad5-4f55-b71e-ef91adf1dfef
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1875223693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1875223693
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.892178735
Short name T31
Test name
Test status
Simulation time 7914777 ps
CPU time 0.39 seconds
Started Aug 18 05:17:56 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 145404 kb
Host smart-d084338c-32f7-4571-94e4-9254cae731a4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=892178735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.892178735
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3767241897
Short name T10
Test name
Test status
Simulation time 9270776 ps
CPU time 0.36 seconds
Started Aug 18 05:17:59 PM PDT 24
Finished Aug 18 05:17:59 PM PDT 24
Peak memory 145464 kb
Host smart-52dba3a1-1793-4449-aa5c-2c37c5fb43c9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3767241897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3767241897
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.80653024
Short name T62
Test name
Test status
Simulation time 8209730 ps
CPU time 0.4 seconds
Started Aug 18 05:17:54 PM PDT 24
Finished Aug 18 05:17:54 PM PDT 24
Peak memory 145448 kb
Host smart-ddbc2313-3a06-4646-ae13-d070f36e04c6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=80653024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.80653024
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.156631708
Short name T38
Test name
Test status
Simulation time 9126011 ps
CPU time 0.39 seconds
Started Aug 18 05:17:57 PM PDT 24
Finished Aug 18 05:17:58 PM PDT 24
Peak memory 145616 kb
Host smart-e4ed949d-1844-4f70-9bb7-ca1ddcaeb7f2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=156631708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.156631708
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2162715136
Short name T41
Test name
Test status
Simulation time 9253105 ps
CPU time 0.38 seconds
Started Aug 18 05:18:02 PM PDT 24
Finished Aug 18 05:18:02 PM PDT 24
Peak memory 145464 kb
Host smart-d280d549-bfdc-438f-ba34-4ecc106867a4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2162715136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2162715136
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3919839772
Short name T43
Test name
Test status
Simulation time 9457566 ps
CPU time 0.39 seconds
Started Aug 18 05:18:02 PM PDT 24
Finished Aug 18 05:18:02 PM PDT 24
Peak memory 145464 kb
Host smart-3837e6d0-a89d-4ebe-8a86-c5bd6b3dc628
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3919839772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3919839772
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.672712672
Short name T11
Test name
Test status
Simulation time 9089550 ps
CPU time 0.42 seconds
Started Aug 18 05:18:14 PM PDT 24
Finished Aug 18 05:18:15 PM PDT 24
Peak memory 145608 kb
Host smart-80c80631-c0f0-4869-a6e6-dd5c029df9bd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=672712672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.672712672
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1378313443
Short name T30
Test name
Test status
Simulation time 9681925 ps
CPU time 0.38 seconds
Started Aug 18 05:18:07 PM PDT 24
Finished Aug 18 05:18:07 PM PDT 24
Peak memory 145496 kb
Host smart-d74bfedf-e845-4b8d-83b5-d65c6f5e1395
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1378313443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1378313443
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1243273495
Short name T39
Test name
Test status
Simulation time 9005584 ps
CPU time 0.38 seconds
Started Aug 18 05:17:57 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 145596 kb
Host smart-4fb06270-ccc8-400e-a72a-4660f9cce72a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1243273495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1243273495
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2500762694
Short name T60
Test name
Test status
Simulation time 8666753 ps
CPU time 0.39 seconds
Started Aug 18 05:17:58 PM PDT 24
Finished Aug 18 05:17:59 PM PDT 24
Peak memory 145468 kb
Host smart-36f0ecfc-8d54-41aa-8516-f0a52635e22f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2500762694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2500762694
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1561433643
Short name T40
Test name
Test status
Simulation time 10121559 ps
CPU time 0.39 seconds
Started Aug 18 05:17:51 PM PDT 24
Finished Aug 18 05:17:52 PM PDT 24
Peak memory 145596 kb
Host smart-2166561a-1048-44ed-a8ff-24ecd0fd77a9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1561433643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1561433643
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3419032247
Short name T63
Test name
Test status
Simulation time 9545883 ps
CPU time 0.41 seconds
Started Aug 18 05:17:57 PM PDT 24
Finished Aug 18 05:17:58 PM PDT 24
Peak memory 145596 kb
Host smart-1673be15-3b08-4198-bff7-f4e0760a379b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3419032247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3419032247
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.840422358
Short name T61
Test name
Test status
Simulation time 9959574 ps
CPU time 0.4 seconds
Started Aug 18 05:17:55 PM PDT 24
Finished Aug 18 05:17:55 PM PDT 24
Peak memory 145508 kb
Host smart-a245c537-1817-4c75-8c86-3e2c2df25347
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=840422358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.840422358
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3148151751
Short name T32
Test name
Test status
Simulation time 8911677 ps
CPU time 0.41 seconds
Started Aug 18 05:17:58 PM PDT 24
Finished Aug 18 05:17:58 PM PDT 24
Peak memory 145608 kb
Host smart-77e9a1a9-e0c8-43e6-b036-25d7bd6be6ae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3148151751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3148151751
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1221224482
Short name T29
Test name
Test status
Simulation time 10180615 ps
CPU time 0.43 seconds
Started Aug 18 05:17:57 PM PDT 24
Finished Aug 18 05:17:57 PM PDT 24
Peak memory 145596 kb
Host smart-fe4a31a4-7e60-4963-99eb-0ca0b8564369
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1221224482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1221224482
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3432614169
Short name T76
Test name
Test status
Simulation time 26680513 ps
CPU time 0.43 seconds
Started Aug 18 05:18:01 PM PDT 24
Finished Aug 18 05:18:01 PM PDT 24
Peak memory 145592 kb
Host smart-95978ab5-5acc-4b04-aa89-cfbb52e83198
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3432614169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3432614169
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2001156065
Short name T66
Test name
Test status
Simulation time 29106674 ps
CPU time 0.39 seconds
Started Aug 18 05:18:02 PM PDT 24
Finished Aug 18 05:18:02 PM PDT 24
Peak memory 145516 kb
Host smart-81ee876a-dbbc-47fd-923a-157bf3a9a4bb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2001156065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2001156065
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.285685213
Short name T36
Test name
Test status
Simulation time 28286707 ps
CPU time 0.41 seconds
Started Aug 18 05:18:14 PM PDT 24
Finished Aug 18 05:18:14 PM PDT 24
Peak memory 145620 kb
Host smart-c772396c-0a51-44d6-b1cd-7af64bd5ea2f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=285685213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.285685213
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1004923518
Short name T34
Test name
Test status
Simulation time 26869090 ps
CPU time 0.41 seconds
Started Aug 18 05:18:01 PM PDT 24
Finished Aug 18 05:18:02 PM PDT 24
Peak memory 145592 kb
Host smart-1310cafb-d8a1-464d-a6fd-7ca6301f25a2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1004923518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1004923518
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2796019680
Short name T70
Test name
Test status
Simulation time 26398696 ps
CPU time 0.39 seconds
Started Aug 18 05:18:08 PM PDT 24
Finished Aug 18 05:18:09 PM PDT 24
Peak memory 145524 kb
Host smart-74cac44c-bac2-4fea-891a-cbad9ac37ba4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2796019680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2796019680
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1770037405
Short name T80
Test name
Test status
Simulation time 26890046 ps
CPU time 0.4 seconds
Started Aug 18 05:18:02 PM PDT 24
Finished Aug 18 05:18:02 PM PDT 24
Peak memory 145636 kb
Host smart-97ded3c7-eb2b-46a9-9271-c5148bed437e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1770037405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1770037405
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4121859077
Short name T75
Test name
Test status
Simulation time 30455635 ps
CPU time 0.39 seconds
Started Aug 18 05:18:07 PM PDT 24
Finished Aug 18 05:18:07 PM PDT 24
Peak memory 145608 kb
Host smart-064b3b58-fa96-4bd5-9675-407b3ae2fdc3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4121859077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.4121859077
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2087431054
Short name T69
Test name
Test status
Simulation time 25661649 ps
CPU time 0.42 seconds
Started Aug 18 05:18:11 PM PDT 24
Finished Aug 18 05:18:11 PM PDT 24
Peak memory 145624 kb
Host smart-01d608a3-d30c-4e98-b7c7-3f0ef598a7fe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2087431054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2087431054
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1141861293
Short name T65
Test name
Test status
Simulation time 27799503 ps
CPU time 0.39 seconds
Started Aug 18 05:18:08 PM PDT 24
Finished Aug 18 05:18:08 PM PDT 24
Peak memory 145512 kb
Host smart-ce4a6ee1-1f63-4199-b042-793d79b8b35c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1141861293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1141861293
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3169147970
Short name T67
Test name
Test status
Simulation time 28573049 ps
CPU time 0.42 seconds
Started Aug 18 05:18:02 PM PDT 24
Finished Aug 18 05:18:02 PM PDT 24
Peak memory 145612 kb
Host smart-2a9a6b0c-f111-466d-bc60-0d013175a4cc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3169147970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3169147970
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3641731452
Short name T73
Test name
Test status
Simulation time 27333173 ps
CPU time 0.44 seconds
Started Aug 18 05:18:11 PM PDT 24
Finished Aug 18 05:18:11 PM PDT 24
Peak memory 145520 kb
Host smart-6eafcedc-dbfa-4e83-b2c6-9b6339cf7d6e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3641731452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3641731452
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2560798021
Short name T71
Test name
Test status
Simulation time 29323716 ps
CPU time 0.41 seconds
Started Aug 18 05:18:01 PM PDT 24
Finished Aug 18 05:18:01 PM PDT 24
Peak memory 145584 kb
Host smart-57112944-85b6-4b1f-bf6e-1ebfc8f59121
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2560798021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2560798021
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.4229222441
Short name T68
Test name
Test status
Simulation time 27556975 ps
CPU time 0.44 seconds
Started Aug 18 05:18:03 PM PDT 24
Finished Aug 18 05:18:03 PM PDT 24
Peak memory 145616 kb
Host smart-31860408-8aa2-428d-8aa2-9af283448b0e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4229222441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.4229222441
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2786413311
Short name T79
Test name
Test status
Simulation time 27285694 ps
CPU time 0.39 seconds
Started Aug 18 05:18:08 PM PDT 24
Finished Aug 18 05:18:09 PM PDT 24
Peak memory 145600 kb
Host smart-88de8787-82c1-4c4c-a15d-4328b36e5f5b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2786413311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2786413311
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.391383421
Short name T74
Test name
Test status
Simulation time 28014296 ps
CPU time 0.4 seconds
Started Aug 18 05:18:08 PM PDT 24
Finished Aug 18 05:18:09 PM PDT 24
Peak memory 145452 kb
Host smart-51ab2e68-cedc-4933-8e8c-04b1ec4dda3c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=391383421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.391383421
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.856331240
Short name T72
Test name
Test status
Simulation time 28228800 ps
CPU time 0.43 seconds
Started Aug 18 05:18:02 PM PDT 24
Finished Aug 18 05:18:03 PM PDT 24
Peak memory 145512 kb
Host smart-c261256d-05fa-42bf-a7b3-c0b9fec54073
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=856331240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.856331240
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2901727457
Short name T35
Test name
Test status
Simulation time 25837548 ps
CPU time 0.39 seconds
Started Aug 18 05:18:10 PM PDT 24
Finished Aug 18 05:18:11 PM PDT 24
Peak memory 145512 kb
Host smart-db9d23cd-ff9a-417b-bff3-da0ee7fb3c9a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2901727457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2901727457
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2980097778
Short name T77
Test name
Test status
Simulation time 26664075 ps
CPU time 0.44 seconds
Started Aug 18 05:18:11 PM PDT 24
Finished Aug 18 05:18:11 PM PDT 24
Peak memory 145512 kb
Host smart-b3578808-eb25-40ba-af30-3947d39f9796
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2980097778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2980097778
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3217732531
Short name T33
Test name
Test status
Simulation time 29187262 ps
CPU time 0.41 seconds
Started Aug 18 05:18:02 PM PDT 24
Finished Aug 18 05:18:03 PM PDT 24
Peak memory 145484 kb
Host smart-68fbfcfc-04f1-4ed1-8148-8f9440de4898
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3217732531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3217732531
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1505242127
Short name T78
Test name
Test status
Simulation time 27810986 ps
CPU time 0.38 seconds
Started Aug 18 05:18:05 PM PDT 24
Finished Aug 18 05:18:06 PM PDT 24
Peak memory 145616 kb
Host smart-233ee250-3aad-40d9-b13c-8bb2af13b944
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1505242127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1505242127
Directory /workspace/9.prim_sync_fatal_alert/latest
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