| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.60 | 100.00 | 100.00 | 100.00 | 85.71 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.24 | 88.24 | 100.00 | 100.00 | 95.83 | 95.83 | 96.43 | 96.43 | 78.57 | 78.57 | 95.83 | 95.83 | 62.79 | 62.79 | /workspace/coverage/default/16.prim_async_alert.3695231345 |
| 91.37 | 3.13 | 100.00 | 0.00 | 95.83 | 0.00 | 96.43 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 74.42 | 11.63 | /workspace/coverage/sync_alert/13.prim_sync_alert.2850930348 |
| 93.52 | 2.15 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 3.57 | 85.71 | 0.00 | 95.83 | 0.00 | 83.72 | 9.30 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2448818487 |
| 93.90 | 0.39 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 2.33 | /workspace/coverage/default/1.prim_async_alert.477711180 |
| 94.25 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.903965875 |
| 94.60 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_alert/8.prim_sync_alert.4213683808 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.3883266298 |
| /workspace/coverage/default/10.prim_async_alert.2078903106 |
| /workspace/coverage/default/11.prim_async_alert.1852369248 |
| /workspace/coverage/default/12.prim_async_alert.635807832 |
| /workspace/coverage/default/13.prim_async_alert.811017210 |
| /workspace/coverage/default/14.prim_async_alert.955849125 |
| /workspace/coverage/default/15.prim_async_alert.3762586185 |
| /workspace/coverage/default/17.prim_async_alert.392496914 |
| /workspace/coverage/default/18.prim_async_alert.1308219465 |
| /workspace/coverage/default/19.prim_async_alert.1040816237 |
| /workspace/coverage/default/2.prim_async_alert.2402537170 |
| /workspace/coverage/default/3.prim_async_alert.552699141 |
| /workspace/coverage/default/4.prim_async_alert.1514995954 |
| /workspace/coverage/default/5.prim_async_alert.998047026 |
| /workspace/coverage/default/6.prim_async_alert.1407940364 |
| /workspace/coverage/default/8.prim_async_alert.501494283 |
| /workspace/coverage/default/9.prim_async_alert.1356825415 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3541951056 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3461393485 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2414041554 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2079457707 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1871665283 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3032711293 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3091507325 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3767758753 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.132182316 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.523441655 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2948611605 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2877021020 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3240570003 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1299872174 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1428459708 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.737839604 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.2903774643 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.2709638643 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.1286593834 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.3510885204 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2125172789 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.197843538 |
| /workspace/coverage/sync_alert/15.prim_sync_alert.3450685763 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.1742103391 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.629866498 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.3617203368 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.1720455218 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.277359900 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3575063202 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.1890257131 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.2283259914 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.3590270706 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1684588817 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.4226879093 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.359082436 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.479353084 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3899953365 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2770195941 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2298684649 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2780247483 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2764773089 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.922204533 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1007810054 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.215576767 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1352056860 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3017067329 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2812439294 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.312978080 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2411669178 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2581200991 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2318240873 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2243614296 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.143760159 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1989258483 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_async_alert.1356825415 | Aug 19 04:29:50 PM PDT 24 | Aug 19 04:29:50 PM PDT 24 | 11867326 ps | ||
| T2 | /workspace/coverage/default/18.prim_async_alert.1308219465 | Aug 19 04:29:48 PM PDT 24 | Aug 19 04:29:49 PM PDT 24 | 10941855 ps | ||
| T3 | /workspace/coverage/default/4.prim_async_alert.1514995954 | Aug 19 04:29:46 PM PDT 24 | Aug 19 04:29:47 PM PDT 24 | 11374553 ps | ||
| T9 | /workspace/coverage/default/3.prim_async_alert.552699141 | Aug 19 04:29:52 PM PDT 24 | Aug 19 04:29:53 PM PDT 24 | 11214475 ps | ||
| T7 | /workspace/coverage/default/16.prim_async_alert.3695231345 | Aug 19 04:29:48 PM PDT 24 | Aug 19 04:29:48 PM PDT 24 | 11709263 ps | ||
| T17 | /workspace/coverage/default/11.prim_async_alert.1852369248 | Aug 19 04:29:44 PM PDT 24 | Aug 19 04:29:44 PM PDT 24 | 11511124 ps | ||
| T18 | /workspace/coverage/default/5.prim_async_alert.998047026 | Aug 19 04:29:50 PM PDT 24 | Aug 19 04:29:51 PM PDT 24 | 10957522 ps | ||
| T19 | /workspace/coverage/default/1.prim_async_alert.477711180 | Aug 19 04:29:32 PM PDT 24 | Aug 19 04:29:32 PM PDT 24 | 11653483 ps | ||
| T10 | /workspace/coverage/default/6.prim_async_alert.1407940364 | Aug 19 04:29:44 PM PDT 24 | Aug 19 04:29:45 PM PDT 24 | 12315744 ps | ||
| T8 | /workspace/coverage/default/19.prim_async_alert.1040816237 | Aug 19 04:29:42 PM PDT 24 | Aug 19 04:29:43 PM PDT 24 | 10705455 ps | ||
| T20 | /workspace/coverage/default/17.prim_async_alert.392496914 | Aug 19 04:29:51 PM PDT 24 | Aug 19 04:29:51 PM PDT 24 | 11155335 ps | ||
| T21 | /workspace/coverage/default/10.prim_async_alert.2078903106 | Aug 19 04:29:32 PM PDT 24 | Aug 19 04:29:33 PM PDT 24 | 11412385 ps | ||
| T16 | /workspace/coverage/default/14.prim_async_alert.955849125 | Aug 19 04:29:31 PM PDT 24 | Aug 19 04:29:32 PM PDT 24 | 11725481 ps | ||
| T12 | /workspace/coverage/default/15.prim_async_alert.3762586185 | Aug 19 04:29:32 PM PDT 24 | Aug 19 04:29:32 PM PDT 24 | 12027112 ps | ||
| T47 | /workspace/coverage/default/8.prim_async_alert.501494283 | Aug 19 04:29:43 PM PDT 24 | Aug 19 04:29:43 PM PDT 24 | 10301017 ps | ||
| T48 | /workspace/coverage/default/2.prim_async_alert.2402537170 | Aug 19 04:29:33 PM PDT 24 | Aug 19 04:29:33 PM PDT 24 | 11043967 ps | ||
| T22 | /workspace/coverage/default/13.prim_async_alert.811017210 | Aug 19 04:29:51 PM PDT 24 | Aug 19 04:29:51 PM PDT 24 | 11528215 ps | ||
| T13 | /workspace/coverage/default/12.prim_async_alert.635807832 | Aug 19 04:29:44 PM PDT 24 | Aug 19 04:29:45 PM PDT 24 | 11738033 ps | ||
| T49 | /workspace/coverage/default/0.prim_async_alert.3883266298 | Aug 19 04:29:36 PM PDT 24 | Aug 19 04:29:36 PM PDT 24 | 11482590 ps | ||
| T23 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1428459708 | Aug 19 04:37:09 PM PDT 24 | Aug 19 04:37:10 PM PDT 24 | 31963141 ps | ||
| T42 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3032711293 | Aug 19 04:36:39 PM PDT 24 | Aug 19 04:36:40 PM PDT 24 | 30938500 ps | ||
| T43 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.132182316 | Aug 19 04:36:58 PM PDT 24 | Aug 19 04:36:58 PM PDT 24 | 28840875 ps | ||
| T44 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2877021020 | Aug 19 04:36:35 PM PDT 24 | Aug 19 04:36:35 PM PDT 24 | 30529363 ps | ||
| T24 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2448818487 | Aug 19 04:36:58 PM PDT 24 | Aug 19 04:36:58 PM PDT 24 | 27132856 ps | ||
| T14 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.523441655 | Aug 19 04:36:51 PM PDT 24 | Aug 19 04:36:52 PM PDT 24 | 28589768 ps | ||
| T45 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2414041554 | Aug 19 04:36:48 PM PDT 24 | Aug 19 04:36:53 PM PDT 24 | 31239180 ps | ||
| T25 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2948611605 | Aug 19 04:36:47 PM PDT 24 | Aug 19 04:36:47 PM PDT 24 | 29503188 ps | ||
| T41 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.737839604 | Aug 19 04:37:07 PM PDT 24 | Aug 19 04:37:07 PM PDT 24 | 29681101 ps | ||
| T46 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3541951056 | Aug 19 04:36:57 PM PDT 24 | Aug 19 04:36:57 PM PDT 24 | 27612516 ps | ||
| T50 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2079457707 | Aug 19 04:36:50 PM PDT 24 | Aug 19 04:36:51 PM PDT 24 | 29260854 ps | ||
| T51 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3240570003 | Aug 19 04:36:59 PM PDT 24 | Aug 19 04:37:00 PM PDT 24 | 29426706 ps | ||
| T52 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3091507325 | Aug 19 04:36:52 PM PDT 24 | Aug 19 04:36:52 PM PDT 24 | 32148350 ps | ||
| T4 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3767758753 | Aug 19 04:36:57 PM PDT 24 | Aug 19 04:36:58 PM PDT 24 | 30307740 ps | ||
| T15 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1299872174 | Aug 19 04:36:55 PM PDT 24 | Aug 19 04:36:55 PM PDT 24 | 29377803 ps | ||
| T5 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.903965875 | Aug 19 04:36:43 PM PDT 24 | Aug 19 04:36:43 PM PDT 24 | 29957464 ps | ||
| T53 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1871665283 | Aug 19 04:36:48 PM PDT 24 | Aug 19 04:36:48 PM PDT 24 | 29047754 ps | ||
| T54 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3461393485 | Aug 19 04:36:48 PM PDT 24 | Aug 19 04:36:48 PM PDT 24 | 29510255 ps | ||
| T34 | /workspace/coverage/sync_alert/3.prim_sync_alert.3575063202 | Aug 19 04:38:21 PM PDT 24 | Aug 19 04:38:21 PM PDT 24 | 9616947 ps | ||
| T26 | /workspace/coverage/sync_alert/13.prim_sync_alert.2850930348 | Aug 19 04:38:04 PM PDT 24 | Aug 19 04:38:05 PM PDT 24 | 9362575 ps | ||
| T27 | /workspace/coverage/sync_alert/2.prim_sync_alert.277359900 | Aug 19 04:38:20 PM PDT 24 | Aug 19 04:38:20 PM PDT 24 | 9071420 ps | ||
| T35 | /workspace/coverage/sync_alert/6.prim_sync_alert.3590270706 | Aug 19 04:38:05 PM PDT 24 | Aug 19 04:38:06 PM PDT 24 | 9244422 ps | ||
| T36 | /workspace/coverage/sync_alert/5.prim_sync_alert.2283259914 | Aug 19 04:38:28 PM PDT 24 | Aug 19 04:38:28 PM PDT 24 | 9198279 ps | ||
| T37 | /workspace/coverage/sync_alert/4.prim_sync_alert.1890257131 | Aug 19 04:38:03 PM PDT 24 | Aug 19 04:38:04 PM PDT 24 | 9485512 ps | ||
| T38 | /workspace/coverage/sync_alert/18.prim_sync_alert.3617203368 | Aug 19 04:38:25 PM PDT 24 | Aug 19 04:38:25 PM PDT 24 | 9055247 ps | ||
| T39 | /workspace/coverage/sync_alert/17.prim_sync_alert.629866498 | Aug 19 04:38:03 PM PDT 24 | Aug 19 04:38:04 PM PDT 24 | 9006779 ps | ||
| T40 | /workspace/coverage/sync_alert/16.prim_sync_alert.1742103391 | Aug 19 04:38:04 PM PDT 24 | Aug 19 04:38:05 PM PDT 24 | 9675348 ps | ||
| T28 | /workspace/coverage/sync_alert/7.prim_sync_alert.1684588817 | Aug 19 04:38:04 PM PDT 24 | Aug 19 04:38:04 PM PDT 24 | 8709863 ps | ||
| T29 | /workspace/coverage/sync_alert/10.prim_sync_alert.1286593834 | Aug 19 04:38:25 PM PDT 24 | Aug 19 04:38:25 PM PDT 24 | 9329094 ps | ||
| T30 | /workspace/coverage/sync_alert/14.prim_sync_alert.197843538 | Aug 19 04:38:21 PM PDT 24 | Aug 19 04:38:22 PM PDT 24 | 10091019 ps | ||
| T55 | /workspace/coverage/sync_alert/15.prim_sync_alert.3450685763 | Aug 19 04:38:14 PM PDT 24 | Aug 19 04:38:15 PM PDT 24 | 8257737 ps | ||
| T56 | /workspace/coverage/sync_alert/9.prim_sync_alert.4226879093 | Aug 19 04:38:24 PM PDT 24 | Aug 19 04:38:25 PM PDT 24 | 8924462 ps | ||
| T31 | /workspace/coverage/sync_alert/19.prim_sync_alert.1720455218 | Aug 19 04:38:06 PM PDT 24 | Aug 19 04:38:06 PM PDT 24 | 9270284 ps | ||
| T57 | /workspace/coverage/sync_alert/1.prim_sync_alert.2709638643 | Aug 19 04:38:30 PM PDT 24 | Aug 19 04:38:30 PM PDT 24 | 9198208 ps | ||
| T32 | /workspace/coverage/sync_alert/12.prim_sync_alert.2125172789 | Aug 19 04:38:06 PM PDT 24 | Aug 19 04:38:06 PM PDT 24 | 8461525 ps | ||
| T58 | /workspace/coverage/sync_alert/11.prim_sync_alert.3510885204 | Aug 19 04:38:07 PM PDT 24 | Aug 19 04:38:08 PM PDT 24 | 9005146 ps | ||
| T11 | /workspace/coverage/sync_alert/8.prim_sync_alert.4213683808 | Aug 19 04:38:06 PM PDT 24 | Aug 19 04:38:06 PM PDT 24 | 8958077 ps | ||
| T59 | /workspace/coverage/sync_alert/0.prim_sync_alert.2903774643 | Aug 19 04:38:21 PM PDT 24 | Aug 19 04:38:22 PM PDT 24 | 9317724 ps | ||
| T33 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2764773089 | Aug 19 04:35:42 PM PDT 24 | Aug 19 04:35:43 PM PDT 24 | 28045653 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.922204533 | Aug 19 04:35:22 PM PDT 24 | Aug 19 04:35:22 PM PDT 24 | 25658466 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1989258483 | Aug 19 04:35:29 PM PDT 24 | Aug 19 04:35:30 PM PDT 24 | 25876596 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2812439294 | Aug 19 04:35:21 PM PDT 24 | Aug 19 04:35:21 PM PDT 24 | 28556321 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2411669178 | Aug 19 04:35:21 PM PDT 24 | Aug 19 04:35:21 PM PDT 24 | 27260916 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1352056860 | Aug 19 04:35:24 PM PDT 24 | Aug 19 04:35:24 PM PDT 24 | 27651465 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2780247483 | Aug 19 04:35:27 PM PDT 24 | Aug 19 04:35:27 PM PDT 24 | 26183098 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2318240873 | Aug 19 04:35:24 PM PDT 24 | Aug 19 04:35:25 PM PDT 24 | 27444424 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2581200991 | Aug 19 04:35:17 PM PDT 24 | Aug 19 04:35:17 PM PDT 24 | 27062224 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3017067329 | Aug 19 04:35:26 PM PDT 24 | Aug 19 04:35:26 PM PDT 24 | 28081323 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.215576767 | Aug 19 04:35:31 PM PDT 24 | Aug 19 04:35:32 PM PDT 24 | 26199347 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.359082436 | Aug 19 04:35:28 PM PDT 24 | Aug 19 04:35:28 PM PDT 24 | 28319359 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.143760159 | Aug 19 04:35:22 PM PDT 24 | Aug 19 04:35:22 PM PDT 24 | 28103699 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1007810054 | Aug 19 04:35:34 PM PDT 24 | Aug 19 04:35:35 PM PDT 24 | 26600377 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.312978080 | Aug 19 04:35:32 PM PDT 24 | Aug 19 04:35:32 PM PDT 24 | 26660616 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2298684649 | Aug 19 04:35:33 PM PDT 24 | Aug 19 04:35:33 PM PDT 24 | 26691524 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.479353084 | Aug 19 04:35:28 PM PDT 24 | Aug 19 04:35:28 PM PDT 24 | 29162933 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2243614296 | Aug 19 04:35:44 PM PDT 24 | Aug 19 04:35:45 PM PDT 24 | 28698190 ps | ||
| T76 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3899953365 | Aug 19 04:35:29 PM PDT 24 | Aug 19 04:35:30 PM PDT 24 | 27024018 ps | ||
| T77 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2770195941 | Aug 19 04:35:22 PM PDT 24 | Aug 19 04:35:23 PM PDT 24 | 28854311 ps |
| Test location | /workspace/coverage/default/16.prim_async_alert.3695231345 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11709263 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:29:48 PM PDT 24 |
| Finished | Aug 19 04:29:48 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-08618169-9723-4ca7-a30a-b1d0257ca699 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3695231345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3695231345 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.2850930348 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9362575 ps |
| CPU time | 0.37 seconds |
| Started | Aug 19 04:38:04 PM PDT 24 |
| Finished | Aug 19 04:38:05 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-6852b2c7-eff2-4ba1-8bc4-cfedb04f929c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2850930348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2850930348 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2448818487 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 27132856 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:36:58 PM PDT 24 |
| Finished | Aug 19 04:36:58 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-b92bfddf-a115-4f49-aa2e-4477a7995fd7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2448818487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2448818487 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.477711180 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11653483 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:29:32 PM PDT 24 |
| Finished | Aug 19 04:29:32 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-3b847ad7-d428-4857-aca5-ad9e2c180440 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=477711180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.477711180 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.903965875 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 29957464 ps |
| CPU time | 0.41 seconds |
| Started | Aug 19 04:36:43 PM PDT 24 |
| Finished | Aug 19 04:36:43 PM PDT 24 |
| Peak memory | 145260 kb |
| Host | smart-8327c343-0c75-4dd8-bece-ad601b17e899 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=903965875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.903965875 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.4213683808 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8958077 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:38:06 PM PDT 24 |
| Finished | Aug 19 04:38:06 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-193ad2ee-5250-4df5-8e66-486cab6b5080 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4213683808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.4213683808 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.3883266298 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11482590 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:29:36 PM PDT 24 |
| Finished | Aug 19 04:29:36 PM PDT 24 |
| Peak memory | 145668 kb |
| Host | smart-c25ed463-26f3-4d65-9b1d-519844f02943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883266298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3883266298 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.2078903106 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11412385 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:29:32 PM PDT 24 |
| Finished | Aug 19 04:29:33 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-96bc7b8b-b893-4543-addf-cc85d08bd490 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078903106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2078903106 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.1852369248 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11511124 ps |
| CPU time | 0.41 seconds |
| Started | Aug 19 04:29:44 PM PDT 24 |
| Finished | Aug 19 04:29:44 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-952292ec-82ce-4977-92b6-29a72dbe3bae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852369248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1852369248 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.635807832 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11738033 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:29:44 PM PDT 24 |
| Finished | Aug 19 04:29:45 PM PDT 24 |
| Peak memory | 145844 kb |
| Host | smart-687444ff-e84e-4f8f-a449-310b7a142624 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=635807832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.635807832 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.811017210 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11528215 ps |
| CPU time | 0.44 seconds |
| Started | Aug 19 04:29:51 PM PDT 24 |
| Finished | Aug 19 04:29:51 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-68583612-c2d8-4db7-80b4-b495e9020549 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811017210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.811017210 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.955849125 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11725481 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:29:31 PM PDT 24 |
| Finished | Aug 19 04:29:32 PM PDT 24 |
| Peak memory | 145728 kb |
| Host | smart-e6e371b6-14c3-43b8-87b7-b274d62b394c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955849125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.955849125 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3762586185 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12027112 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:29:32 PM PDT 24 |
| Finished | Aug 19 04:29:32 PM PDT 24 |
| Peak memory | 145676 kb |
| Host | smart-d0fe0e0e-6b55-45f0-a8c1-a48e4332017f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3762586185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3762586185 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.392496914 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11155335 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:29:51 PM PDT 24 |
| Finished | Aug 19 04:29:51 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-3f14a2de-18e9-4cb7-a3d3-fde568e2d658 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392496914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.392496914 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.1308219465 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10941855 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:29:48 PM PDT 24 |
| Finished | Aug 19 04:29:49 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-765eabd4-413b-4460-a0b1-691bdec367d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308219465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1308219465 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.1040816237 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10705455 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:29:42 PM PDT 24 |
| Finished | Aug 19 04:29:43 PM PDT 24 |
| Peak memory | 145744 kb |
| Host | smart-05147c73-ee9a-48d6-ad08-e8cc97c47629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040816237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1040816237 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.2402537170 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11043967 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:29:33 PM PDT 24 |
| Finished | Aug 19 04:29:33 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-ed1162da-5204-4820-bd1b-dc5d113b5ec3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402537170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2402537170 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.552699141 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11214475 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:29:52 PM PDT 24 |
| Finished | Aug 19 04:29:53 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-fc878c3c-62e3-4505-bf57-057b7d8df1f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552699141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.552699141 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.1514995954 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11374553 ps |
| CPU time | 0.42 seconds |
| Started | Aug 19 04:29:46 PM PDT 24 |
| Finished | Aug 19 04:29:47 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-7411f4b3-ac31-4430-9ab3-a70f3f5c4631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514995954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1514995954 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.998047026 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10957522 ps |
| CPU time | 0.42 seconds |
| Started | Aug 19 04:29:50 PM PDT 24 |
| Finished | Aug 19 04:29:51 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-737239b2-ebfa-4d7a-b301-f546f7581594 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998047026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.998047026 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.1407940364 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12315744 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:29:44 PM PDT 24 |
| Finished | Aug 19 04:29:45 PM PDT 24 |
| Peak memory | 145856 kb |
| Host | smart-ef926e5c-6ce7-4d36-8cc0-5df5a3adcbfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407940364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1407940364 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.501494283 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10301017 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:29:43 PM PDT 24 |
| Finished | Aug 19 04:29:43 PM PDT 24 |
| Peak memory | 145808 kb |
| Host | smart-e5ee9863-46fc-454e-9c90-7540fc03b52c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501494283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.501494283 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1356825415 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11867326 ps |
| CPU time | 0.37 seconds |
| Started | Aug 19 04:29:50 PM PDT 24 |
| Finished | Aug 19 04:29:50 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-7f39c53b-7f93-42df-8713-c97347fef605 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356825415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1356825415 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3541951056 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 27612516 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:36:57 PM PDT 24 |
| Finished | Aug 19 04:36:57 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-d239c5e0-049a-4882-860c-0bfa4717f11d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3541951056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3541951056 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3461393485 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 29510255 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:36:48 PM PDT 24 |
| Finished | Aug 19 04:36:48 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-c1e428a8-078f-4603-a8ae-5c5497437bea |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3461393485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3461393485 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2414041554 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 31239180 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:36:48 PM PDT 24 |
| Finished | Aug 19 04:36:53 PM PDT 24 |
| Peak memory | 145352 kb |
| Host | smart-e5314833-4f43-49de-9553-f4dba9e1e952 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2414041554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2414041554 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2079457707 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 29260854 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:36:50 PM PDT 24 |
| Finished | Aug 19 04:36:51 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-d60c0efc-f682-483d-a4a6-bcefa5cf2674 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2079457707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2079457707 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1871665283 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 29047754 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:36:48 PM PDT 24 |
| Finished | Aug 19 04:36:48 PM PDT 24 |
| Peak memory | 145348 kb |
| Host | smart-444e2079-0696-46ce-b776-e14780170de1 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1871665283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1871665283 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3032711293 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30938500 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:36:39 PM PDT 24 |
| Finished | Aug 19 04:36:40 PM PDT 24 |
| Peak memory | 145432 kb |
| Host | smart-900177c3-4cad-429f-9f82-1b1acf6428c3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3032711293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3032711293 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3091507325 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 32148350 ps |
| CPU time | 0.42 seconds |
| Started | Aug 19 04:36:52 PM PDT 24 |
| Finished | Aug 19 04:36:52 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-25c0624c-979f-4bba-ad64-a28484e687cb |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3091507325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3091507325 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3767758753 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30307740 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:36:57 PM PDT 24 |
| Finished | Aug 19 04:36:58 PM PDT 24 |
| Peak memory | 145340 kb |
| Host | smart-9bc57f48-bb5f-4c82-8278-f25911c83653 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3767758753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3767758753 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.132182316 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 28840875 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:36:58 PM PDT 24 |
| Finished | Aug 19 04:36:58 PM PDT 24 |
| Peak memory | 145376 kb |
| Host | smart-9a501987-8270-4c66-ba4b-0e6a52fd2b0e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=132182316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.132182316 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.523441655 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 28589768 ps |
| CPU time | 0.42 seconds |
| Started | Aug 19 04:36:51 PM PDT 24 |
| Finished | Aug 19 04:36:52 PM PDT 24 |
| Peak memory | 144480 kb |
| Host | smart-5d6e2326-81bd-47fb-b4c2-1e2f2b51410b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=523441655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.523441655 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2948611605 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 29503188 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:36:47 PM PDT 24 |
| Finished | Aug 19 04:36:47 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-301e90b2-c54b-4449-8a8a-81a0119fbccd |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2948611605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2948611605 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2877021020 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30529363 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:36:35 PM PDT 24 |
| Finished | Aug 19 04:36:35 PM PDT 24 |
| Peak memory | 145292 kb |
| Host | smart-5371128d-d27e-41b3-80e5-d59a83cc138e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2877021020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2877021020 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3240570003 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29426706 ps |
| CPU time | 0.42 seconds |
| Started | Aug 19 04:36:59 PM PDT 24 |
| Finished | Aug 19 04:37:00 PM PDT 24 |
| Peak memory | 145332 kb |
| Host | smart-eed9cae6-48e2-435a-8bbd-72a182e25ea4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3240570003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3240570003 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1299872174 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 29377803 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:36:55 PM PDT 24 |
| Finished | Aug 19 04:36:55 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-c11f8c53-d7c0-49e6-be3e-44b19fac323a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1299872174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1299872174 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1428459708 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 31963141 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:37:09 PM PDT 24 |
| Finished | Aug 19 04:37:10 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-5a947274-abb6-40f5-9f3b-7fdc074f3a3f |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1428459708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1428459708 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.737839604 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29681101 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:37:07 PM PDT 24 |
| Finished | Aug 19 04:37:07 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-1b1d622a-988f-41c5-a057-bd98eda6b920 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=737839604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.737839604 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.2903774643 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9317724 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:38:21 PM PDT 24 |
| Finished | Aug 19 04:38:22 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-13aeb308-0ffd-4f3a-97ba-083570512735 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2903774643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2903774643 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.2709638643 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9198208 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:38:30 PM PDT 24 |
| Finished | Aug 19 04:38:30 PM PDT 24 |
| Peak memory | 145556 kb |
| Host | smart-3bc8087b-c368-4fff-ae69-be4315f7bc33 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2709638643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2709638643 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1286593834 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9329094 ps |
| CPU time | 0.37 seconds |
| Started | Aug 19 04:38:25 PM PDT 24 |
| Finished | Aug 19 04:38:25 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-67e059d3-cf7b-4108-9d5e-c25503a8a7cf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1286593834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1286593834 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.3510885204 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9005146 ps |
| CPU time | 0.37 seconds |
| Started | Aug 19 04:38:07 PM PDT 24 |
| Finished | Aug 19 04:38:08 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-fc5d8917-bcc8-44ec-a534-9b35ce3bb8cf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3510885204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3510885204 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2125172789 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8461525 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:38:06 PM PDT 24 |
| Finished | Aug 19 04:38:06 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-78a718e7-ed1e-4e0a-bafe-5c6b73a691d3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2125172789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2125172789 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.197843538 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10091019 ps |
| CPU time | 0.36 seconds |
| Started | Aug 19 04:38:21 PM PDT 24 |
| Finished | Aug 19 04:38:22 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-fea93f0e-ec30-4765-bc3b-11418ef877f8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=197843538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.197843538 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.3450685763 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 8257737 ps |
| CPU time | 0.43 seconds |
| Started | Aug 19 04:38:14 PM PDT 24 |
| Finished | Aug 19 04:38:15 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-b7f58082-1082-44c4-9e4f-b5dc209d8393 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3450685763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3450685763 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.1742103391 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9675348 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:38:04 PM PDT 24 |
| Finished | Aug 19 04:38:05 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-92818668-a9e5-418c-9e71-e753ddf8a85a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1742103391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1742103391 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.629866498 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9006779 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:38:03 PM PDT 24 |
| Finished | Aug 19 04:38:04 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-97bb2b36-9da8-447d-83ba-fa08a8244d95 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=629866498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.629866498 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.3617203368 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9055247 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:38:25 PM PDT 24 |
| Finished | Aug 19 04:38:25 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-319ecf5c-c718-40a0-a6b4-83b69627dbeb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3617203368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.3617203368 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.1720455218 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9270284 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:38:06 PM PDT 24 |
| Finished | Aug 19 04:38:06 PM PDT 24 |
| Peak memory | 145544 kb |
| Host | smart-9e718b48-735f-4a0f-82f8-7147a4927053 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1720455218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1720455218 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.277359900 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9071420 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:38:20 PM PDT 24 |
| Finished | Aug 19 04:38:20 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-b3c1a128-78a9-4cc7-a03c-987972c861eb |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=277359900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.277359900 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3575063202 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9616947 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:38:21 PM PDT 24 |
| Finished | Aug 19 04:38:21 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-6e8440ed-46b6-48b9-bd81-d6f6ae829843 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3575063202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3575063202 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.1890257131 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9485512 ps |
| CPU time | 0.42 seconds |
| Started | Aug 19 04:38:03 PM PDT 24 |
| Finished | Aug 19 04:38:04 PM PDT 24 |
| Peak memory | 145616 kb |
| Host | smart-d7b8a0a5-d957-4f9c-bb6a-a3201aff1345 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1890257131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1890257131 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2283259914 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9198279 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:38:28 PM PDT 24 |
| Finished | Aug 19 04:38:28 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-36a8b4bd-19e2-41e4-aa02-26beb6400288 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2283259914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2283259914 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.3590270706 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9244422 ps |
| CPU time | 0.36 seconds |
| Started | Aug 19 04:38:05 PM PDT 24 |
| Finished | Aug 19 04:38:06 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-21bd4077-6cdf-4ff9-b0d0-60637716a49c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3590270706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3590270706 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1684588817 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8709863 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:38:04 PM PDT 24 |
| Finished | Aug 19 04:38:04 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-570ad95f-ce05-4ea9-9451-4df8756e916a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1684588817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1684588817 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.4226879093 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8924462 ps |
| CPU time | 0.37 seconds |
| Started | Aug 19 04:38:24 PM PDT 24 |
| Finished | Aug 19 04:38:25 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-fe1a02f2-acd8-4904-a385-a874f195f675 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4226879093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.4226879093 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.359082436 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28319359 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:35:28 PM PDT 24 |
| Finished | Aug 19 04:35:28 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-433b5143-c4a0-45c1-8c85-cac32f79aa11 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=359082436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.359082436 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.479353084 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 29162933 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:35:28 PM PDT 24 |
| Finished | Aug 19 04:35:28 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-fe883c78-deba-4249-874a-32df7c7a7abe |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=479353084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.479353084 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3899953365 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27024018 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:35:29 PM PDT 24 |
| Finished | Aug 19 04:35:30 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-5005a7f4-1f5b-470c-8f6f-df50da10a3d6 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3899953365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3899953365 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2770195941 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28854311 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:35:22 PM PDT 24 |
| Finished | Aug 19 04:35:23 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-bdd4eeb1-6bcb-45c3-aeff-3f5e808754c3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2770195941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2770195941 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2298684649 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26691524 ps |
| CPU time | 0.43 seconds |
| Started | Aug 19 04:35:33 PM PDT 24 |
| Finished | Aug 19 04:35:33 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-ab2183dc-e0bc-4304-869b-3e10b2e9b565 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2298684649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2298684649 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2780247483 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26183098 ps |
| CPU time | 0.42 seconds |
| Started | Aug 19 04:35:27 PM PDT 24 |
| Finished | Aug 19 04:35:27 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-4cadd264-ec1a-438f-9ed3-7ae031a6d300 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2780247483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2780247483 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2764773089 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 28045653 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:35:42 PM PDT 24 |
| Finished | Aug 19 04:35:43 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-74dc6321-2b9f-4c4c-a3f1-27ad3127f502 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2764773089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2764773089 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.922204533 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 25658466 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:35:22 PM PDT 24 |
| Finished | Aug 19 04:35:22 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-0b93ba50-e675-4983-8d52-900214240a91 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=922204533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.922204533 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1007810054 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26600377 ps |
| CPU time | 0.41 seconds |
| Started | Aug 19 04:35:34 PM PDT 24 |
| Finished | Aug 19 04:35:35 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-907ca2c3-7fad-426a-abee-76e298f0ab4a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1007810054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1007810054 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.215576767 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26199347 ps |
| CPU time | 0.41 seconds |
| Started | Aug 19 04:35:31 PM PDT 24 |
| Finished | Aug 19 04:35:32 PM PDT 24 |
| Peak memory | 145572 kb |
| Host | smart-674893ab-8e62-43d1-b839-7499e04f5331 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=215576767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.215576767 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1352056860 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27651465 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:35:24 PM PDT 24 |
| Finished | Aug 19 04:35:24 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-f50cd212-46dc-4516-b877-a6e842a4c95a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1352056860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1352056860 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3017067329 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28081323 ps |
| CPU time | 0.42 seconds |
| Started | Aug 19 04:35:26 PM PDT 24 |
| Finished | Aug 19 04:35:26 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-5b2800e0-bbd7-4308-9fe4-a7a0602ac951 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3017067329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3017067329 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2812439294 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 28556321 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:35:21 PM PDT 24 |
| Finished | Aug 19 04:35:21 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-c46fd506-85a3-4e4f-9a14-57ecdc41e5e9 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2812439294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2812439294 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.312978080 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26660616 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:35:32 PM PDT 24 |
| Finished | Aug 19 04:35:32 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-c93ccb25-68a9-4b7c-9410-e9c67e26b729 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=312978080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.312978080 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2411669178 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27260916 ps |
| CPU time | 0.38 seconds |
| Started | Aug 19 04:35:21 PM PDT 24 |
| Finished | Aug 19 04:35:21 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-252be482-4a62-42df-ab11-677e960a9e76 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2411669178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2411669178 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2581200991 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27062224 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:35:17 PM PDT 24 |
| Finished | Aug 19 04:35:17 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-12a783c8-c3a1-4c77-b3ea-9e21d9a6ee63 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2581200991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2581200991 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2318240873 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27444424 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:35:24 PM PDT 24 |
| Finished | Aug 19 04:35:25 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-ef1502ee-de26-4adf-8e74-ae289b4611e4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2318240873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2318240873 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2243614296 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 28698190 ps |
| CPU time | 0.39 seconds |
| Started | Aug 19 04:35:44 PM PDT 24 |
| Finished | Aug 19 04:35:45 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-4dacb68b-ec11-483f-8701-91088720b5c0 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2243614296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2243614296 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.143760159 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28103699 ps |
| CPU time | 0.4 seconds |
| Started | Aug 19 04:35:22 PM PDT 24 |
| Finished | Aug 19 04:35:22 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-91660957-8afe-4831-816f-71a741c3773a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=143760159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.143760159 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1989258483 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 25876596 ps |
| CPU time | 0.41 seconds |
| Started | Aug 19 04:35:29 PM PDT 24 |
| Finished | Aug 19 04:35:30 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-98eede10-cb27-4651-912f-f8321a05687f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1989258483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1989258483 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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