| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.92 | 88.92 | 100.00 | 100.00 | 91.67 | 91.67 | 96.43 | 96.43 | 82.14 | 82.14 | 95.83 | 95.83 | 67.44 | 67.44 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1326511049 |
| 91.80 | 2.88 | 100.00 | 0.00 | 93.75 | 2.08 | 96.43 | 0.00 | 85.71 | 3.57 | 95.83 | 0.00 | 79.07 | 11.63 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.4201181240 |
| 93.90 | 2.11 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 3.57 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.1650263396 |
| 94.85 | 0.94 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.3233924168 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3385271126 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2732635078 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.2810176723 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.4098661530 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.498787614 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1278907439 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.2335181103 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3491586126 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.4199726533 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.115066049 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3538812185 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.358700425 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.741592366 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2350385974 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.762782037 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.302298325 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2674244484 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.4245054256 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.905492825 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.2222275775 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2149743428 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3555311694 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1546323181 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.957193630 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3237500868 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3605443411 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2027986653 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.703111952 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.254500990 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1177257810 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2929808982 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3579031407 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.425560487 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.30660909 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.127956238 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.655241356 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1472000076 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2425726524 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1784510058 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1570784328 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.4043098171 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2434799355 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3853499793 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.2187722604 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3279239379 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.1730326192 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.4191863899 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3311755463 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2697269172 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.1418509825 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2455554712 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3975417897 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2909107003 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3840229836 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2335972889 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3117963264 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4075905235 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1826043135 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2506657130 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3978009902 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2406538602 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1392743331 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2671540163 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2585454212 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2073138822 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.412018078 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.422534174 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3718769623 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1226672929 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.549931012 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3219948595 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3191023593 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.955302806 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3428056313 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.2810176723 | Aug 23 03:53:06 PM UTC 24 | Aug 23 03:53:07 PM UTC 24 | 10576376 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2732635078 | Aug 23 03:53:06 PM UTC 24 | Aug 23 03:53:07 PM UTC 24 | 11068560 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.762782037 | Aug 23 03:53:07 PM UTC 24 | Aug 23 03:53:09 PM UTC 24 | 10550811 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2350385974 | Aug 23 03:53:07 PM UTC 24 | Aug 23 03:53:09 PM UTC 24 | 10774128 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.302298325 | Aug 23 03:53:07 PM UTC 24 | Aug 23 03:53:09 PM UTC 24 | 10706048 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1326511049 | Aug 23 03:53:08 PM UTC 24 | Aug 23 03:53:10 PM UTC 24 | 10968867 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.2222275775 | Aug 23 03:53:09 PM UTC 24 | Aug 23 03:53:10 PM UTC 24 | 12537795 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2674244484 | Aug 23 03:53:08 PM UTC 24 | Aug 23 03:53:10 PM UTC 24 | 10780021 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.4245054256 | Aug 23 03:53:09 PM UTC 24 | Aug 23 03:53:10 PM UTC 24 | 12363320 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.905492825 | Aug 23 03:53:09 PM UTC 24 | Aug 23 03:53:10 PM UTC 24 | 11829937 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.4098661530 | Aug 23 03:53:09 PM UTC 24 | Aug 23 03:53:10 PM UTC 24 | 11300339 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.2335181103 | Aug 23 03:53:10 PM UTC 24 | Aug 23 03:53:11 PM UTC 24 | 11157746 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1278907439 | Aug 23 03:53:10 PM UTC 24 | Aug 23 03:53:11 PM UTC 24 | 11276939 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.498787614 | Aug 23 03:53:10 PM UTC 24 | Aug 23 03:53:11 PM UTC 24 | 11393899 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3491586126 | Aug 23 03:53:10 PM UTC 24 | Aug 23 03:53:11 PM UTC 24 | 11155145 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.115066049 | Aug 23 03:53:10 PM UTC 24 | Aug 23 03:53:11 PM UTC 24 | 10778382 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.4199726533 | Aug 23 03:53:10 PM UTC 24 | Aug 23 03:53:11 PM UTC 24 | 10604871 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3538812185 | Aug 23 03:53:11 PM UTC 24 | Aug 23 03:53:12 PM UTC 24 | 11176268 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.358700425 | Aug 23 03:53:12 PM UTC 24 | Aug 23 03:53:14 PM UTC 24 | 10843779 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.741592366 | Aug 23 03:53:12 PM UTC 24 | Aug 23 03:53:14 PM UTC 24 | 11737358 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.1650263396 | Aug 23 04:58:36 PM UTC 24 | Aug 23 04:58:37 PM UTC 24 | 29416620 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1177257810 | Aug 23 04:58:38 PM UTC 24 | Aug 23 04:58:39 PM UTC 24 | 32166390 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2149743428 | Aug 23 04:58:38 PM UTC 24 | Aug 23 04:58:39 PM UTC 24 | 31077688 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2929808982 | Aug 23 04:58:40 PM UTC 24 | Aug 23 04:58:41 PM UTC 24 | 31280109 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3579031407 | Aug 23 04:58:40 PM UTC 24 | Aug 23 04:58:42 PM UTC 24 | 30728960 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.425560487 | Aug 23 04:58:42 PM UTC 24 | Aug 23 04:58:44 PM UTC 24 | 30642967 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.3233924168 | Aug 23 04:58:42 PM UTC 24 | Aug 23 04:58:44 PM UTC 24 | 28818701 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.127956238 | Aug 23 04:58:44 PM UTC 24 | Aug 23 04:58:46 PM UTC 24 | 27967810 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.30660909 | Aug 23 04:58:44 PM UTC 24 | Aug 23 04:58:46 PM UTC 24 | 32463450 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.655241356 | Aug 23 04:58:46 PM UTC 24 | Aug 23 04:58:48 PM UTC 24 | 30101976 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3555311694 | Aug 23 04:58:46 PM UTC 24 | Aug 23 04:58:48 PM UTC 24 | 29455328 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1546323181 | Aug 23 04:58:49 PM UTC 24 | Aug 23 04:58:51 PM UTC 24 | 30169485 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.957193630 | Aug 23 04:58:49 PM UTC 24 | Aug 23 04:58:51 PM UTC 24 | 32140183 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3237500868 | Aug 23 04:58:52 PM UTC 24 | Aug 23 04:58:53 PM UTC 24 | 31047151 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3605443411 | Aug 23 04:58:52 PM UTC 24 | Aug 23 04:58:53 PM UTC 24 | 30333877 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.703111952 | Aug 23 04:58:54 PM UTC 24 | Aug 23 04:58:55 PM UTC 24 | 30715859 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2027986653 | Aug 23 04:58:54 PM UTC 24 | Aug 23 04:58:55 PM UTC 24 | 27857519 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.254500990 | Aug 23 04:58:56 PM UTC 24 | Aug 23 04:58:57 PM UTC 24 | 30655747 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1472000076 | Aug 23 04:58:56 PM UTC 24 | Aug 23 04:58:57 PM UTC 24 | 8371065 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2425726524 | Aug 23 04:58:56 PM UTC 24 | Aug 23 04:58:57 PM UTC 24 | 9943070 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3311755463 | Aug 23 04:58:58 PM UTC 24 | Aug 23 04:58:59 PM UTC 24 | 8903633 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.4201181240 | Aug 23 04:58:58 PM UTC 24 | Aug 23 04:58:59 PM UTC 24 | 9580642 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2697269172 | Aug 23 04:58:58 PM UTC 24 | Aug 23 04:58:59 PM UTC 24 | 9171702 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.1418509825 | Aug 23 04:59:00 PM UTC 24 | Aug 23 04:59:02 PM UTC 24 | 9069777 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2455554712 | Aug 23 04:59:00 PM UTC 24 | Aug 23 04:59:02 PM UTC 24 | 10090984 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3975417897 | Aug 23 04:59:00 PM UTC 24 | Aug 23 04:59:02 PM UTC 24 | 9293751 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3840229836 | Aug 23 04:59:02 PM UTC 24 | Aug 23 04:59:03 PM UTC 24 | 9110579 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2909107003 | Aug 23 04:59:02 PM UTC 24 | Aug 23 04:59:04 PM UTC 24 | 9412041 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1784510058 | Aug 23 04:59:02 PM UTC 24 | Aug 23 04:59:04 PM UTC 24 | 10007880 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2434799355 | Aug 23 04:59:04 PM UTC 24 | Aug 23 04:59:06 PM UTC 24 | 9282897 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.4043098171 | Aug 23 04:59:04 PM UTC 24 | Aug 23 04:59:06 PM UTC 24 | 8999640 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1570784328 | Aug 23 04:59:04 PM UTC 24 | Aug 23 04:59:06 PM UTC 24 | 9316809 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3385271126 | Aug 23 04:59:06 PM UTC 24 | Aug 23 04:59:08 PM UTC 24 | 9033112 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.2187722604 | Aug 23 04:59:06 PM UTC 24 | Aug 23 04:59:08 PM UTC 24 | 8941544 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3853499793 | Aug 23 04:59:06 PM UTC 24 | Aug 23 04:59:08 PM UTC 24 | 8421896 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3279239379 | Aug 23 04:59:08 PM UTC 24 | Aug 23 04:59:10 PM UTC 24 | 8634415 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.4191863899 | Aug 23 04:59:09 PM UTC 24 | Aug 23 04:59:10 PM UTC 24 | 9059268 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.1730326192 | Aug 23 04:59:09 PM UTC 24 | Aug 23 04:59:10 PM UTC 24 | 10467153 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3117963264 | Aug 23 05:01:41 PM UTC 24 | Aug 23 05:01:43 PM UTC 24 | 27717925 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2335972889 | Aug 23 05:01:41 PM UTC 24 | Aug 23 05:01:43 PM UTC 24 | 26563144 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3718769623 | Aug 23 05:01:41 PM UTC 24 | Aug 23 05:01:43 PM UTC 24 | 27627117 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.422534174 | Aug 23 05:01:41 PM UTC 24 | Aug 23 05:01:43 PM UTC 24 | 27829130 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1226672929 | Aug 23 05:01:41 PM UTC 24 | Aug 23 05:01:43 PM UTC 24 | 26150849 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.549931012 | Aug 23 05:01:43 PM UTC 24 | Aug 23 05:01:44 PM UTC 24 | 27031554 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3219948595 | Aug 23 05:01:43 PM UTC 24 | Aug 23 05:01:44 PM UTC 24 | 26415746 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.955302806 | Aug 23 05:01:43 PM UTC 24 | Aug 23 05:01:44 PM UTC 24 | 27290780 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3191023593 | Aug 23 05:01:43 PM UTC 24 | Aug 23 05:01:44 PM UTC 24 | 28658177 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4075905235 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:45 PM UTC 24 | 28677848 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3428056313 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:45 PM UTC 24 | 29078030 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1826043135 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:45 PM UTC 24 | 27402611 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3978009902 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:46 PM UTC 24 | 26409766 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2506657130 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:46 PM UTC 24 | 28386469 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1392743331 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:46 PM UTC 24 | 26264704 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2406538602 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:46 PM UTC 24 | 27121165 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2671540163 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:46 PM UTC 24 | 26936178 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2585454212 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:46 PM UTC 24 | 27372316 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2073138822 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:46 PM UTC 24 | 29071091 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.412018078 | Aug 23 05:01:44 PM UTC 24 | Aug 23 05:01:46 PM UTC 24 | 29208170 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1326511049 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10968867 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 03:53:08 PM UTC 24 |
| Finished | Aug 23 03:53:10 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326511049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 5.prim_async_alert.1326511049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/5.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.4201181240 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9580642 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:58:58 PM UTC 24 |
| Finished | Aug 23 04:58:59 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201181240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 3.prim_sync_alert.4201181240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/3.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.1650263396 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29416620 ps |
| CPU time | 0.36 seconds |
| Started | Aug 23 04:58:36 PM UTC 24 |
| Finished | Aug 23 04:58:37 PM UTC 24 |
| Peak memory | 155084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650263396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 0.prim_async_fatal_alert.1650263396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.3233924168 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 28818701 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:58:42 PM UTC 24 |
| Finished | Aug 23 04:58:44 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233924168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 6.prim_async_fatal_alert.3233924168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3385271126 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9033112 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 04:59:06 PM UTC 24 |
| Finished | Aug 23 04:59:08 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385271126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.3385271126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/14.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2732635078 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11068560 ps |
| CPU time | 0.4 seconds |
| Started | Aug 23 03:53:06 PM UTC 24 |
| Finished | Aug 23 03:53:07 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732635078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.prim_async_alert.2732635078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/0.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.2810176723 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10576376 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 03:53:06 PM UTC 24 |
| Finished | Aug 23 03:53:07 PM UTC 24 |
| Peak memory | 155228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810176723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.prim_async_alert.2810176723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/1.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.4098661530 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11300339 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 03:53:09 PM UTC 24 |
| Finished | Aug 23 03:53:10 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098661530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 10.prim_async_alert.4098661530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/10.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.498787614 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11393899 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 03:53:10 PM UTC 24 |
| Finished | Aug 23 03:53:11 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498787614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 11.prim_async_alert.498787614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/11.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1278907439 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11276939 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 03:53:10 PM UTC 24 |
| Finished | Aug 23 03:53:11 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278907439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 12.prim_async_alert.1278907439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/12.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.2335181103 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11157746 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 03:53:10 PM UTC 24 |
| Finished | Aug 23 03:53:11 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335181103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.prim_async_alert.2335181103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/13.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3491586126 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11155145 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 03:53:10 PM UTC 24 |
| Finished | Aug 23 03:53:11 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491586126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.3491586126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/14.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.4199726533 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10604871 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 03:53:10 PM UTC 24 |
| Finished | Aug 23 03:53:11 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199726533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.4199726533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/15.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.115066049 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10778382 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 03:53:10 PM UTC 24 |
| Finished | Aug 23 03:53:11 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115066049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 16.prim_async_alert.115066049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/16.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3538812185 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11176268 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 03:53:11 PM UTC 24 |
| Finished | Aug 23 03:53:12 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538812185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.3538812185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/17.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.358700425 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10843779 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 03:53:12 PM UTC 24 |
| Finished | Aug 23 03:53:14 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358700425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 18.prim_async_alert.358700425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/18.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.741592366 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11737358 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 03:53:12 PM UTC 24 |
| Finished | Aug 23 03:53:14 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741592366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 19.prim_async_alert.741592366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/19.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2350385974 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10774128 ps |
| CPU time | 0.32 seconds |
| Started | Aug 23 03:53:07 PM UTC 24 |
| Finished | Aug 23 03:53:09 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350385974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.prim_async_alert.2350385974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/2.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.762782037 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10550811 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 03:53:07 PM UTC 24 |
| Finished | Aug 23 03:53:09 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762782037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 3.prim_async_alert.762782037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/3.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.302298325 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10706048 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 03:53:07 PM UTC 24 |
| Finished | Aug 23 03:53:09 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302298325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 4.prim_async_alert.302298325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/4.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2674244484 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10780021 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 03:53:08 PM UTC 24 |
| Finished | Aug 23 03:53:10 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674244484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.prim_async_alert.2674244484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/6.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.4245054256 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12363320 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 03:53:09 PM UTC 24 |
| Finished | Aug 23 03:53:10 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245054256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 7.prim_async_alert.4245054256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/7.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.905492825 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11829937 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 03:53:09 PM UTC 24 |
| Finished | Aug 23 03:53:10 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905492825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 8.prim_async_alert.905492825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/8.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.2222275775 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12537795 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 03:53:09 PM UTC 24 |
| Finished | Aug 23 03:53:10 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222275775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.2222275775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/9.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2149743428 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31077688 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:58:38 PM UTC 24 |
| Finished | Aug 23 04:58:39 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149743428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.2149743428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3555311694 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29455328 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:58:46 PM UTC 24 |
| Finished | Aug 23 04:58:48 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555311694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.3555311694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1546323181 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30169485 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:58:49 PM UTC 24 |
| Finished | Aug 23 04:58:51 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546323181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.1546323181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.957193630 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 32140183 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:58:49 PM UTC 24 |
| Finished | Aug 23 04:58:51 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957193630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 12.prim_async_fatal_alert.957193630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3237500868 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31047151 ps |
| CPU time | 0.36 seconds |
| Started | Aug 23 04:58:52 PM UTC 24 |
| Finished | Aug 23 04:58:53 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237500868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 13.prim_async_fatal_alert.3237500868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3605443411 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30333877 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:58:52 PM UTC 24 |
| Finished | Aug 23 04:58:53 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605443411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.3605443411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2027986653 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 27857519 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:58:54 PM UTC 24 |
| Finished | Aug 23 04:58:55 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027986653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 16.prim_async_fatal_alert.2027986653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.703111952 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30715859 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:58:54 PM UTC 24 |
| Finished | Aug 23 04:58:55 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703111952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 17.prim_async_fatal_alert.703111952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.254500990 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 30655747 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:58:56 PM UTC 24 |
| Finished | Aug 23 04:58:57 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254500990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 19.prim_async_fatal_alert.254500990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1177257810 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 32166390 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:58:38 PM UTC 24 |
| Finished | Aug 23 04:58:39 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177257810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.1177257810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2929808982 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 31280109 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:58:40 PM UTC 24 |
| Finished | Aug 23 04:58:41 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929808982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 3.prim_async_fatal_alert.2929808982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3579031407 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30728960 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:58:40 PM UTC 24 |
| Finished | Aug 23 04:58:42 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579031407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 4.prim_async_fatal_alert.3579031407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.425560487 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30642967 ps |
| CPU time | 0.36 seconds |
| Started | Aug 23 04:58:42 PM UTC 24 |
| Finished | Aug 23 04:58:44 PM UTC 24 |
| Peak memory | 155004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425560487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 5.prim_async_fatal_alert.425560487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.30660909 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 32463450 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:58:44 PM UTC 24 |
| Finished | Aug 23 04:58:46 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30660909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 7.prim_async_fatal_alert.30660909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.127956238 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 27967810 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:58:44 PM UTC 24 |
| Finished | Aug 23 04:58:46 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127956238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 8.prim_async_fatal_alert.127956238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.655241356 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 30101976 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:58:46 PM UTC 24 |
| Finished | Aug 23 04:58:48 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655241356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 9.prim_async_fatal_alert.655241356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1472000076 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8371065 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:58:56 PM UTC 24 |
| Finished | Aug 23 04:58:57 PM UTC 24 |
| Peak memory | 154616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472000076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.1472000076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/0.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2425726524 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9943070 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 04:58:56 PM UTC 24 |
| Finished | Aug 23 04:58:57 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425726524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 1.prim_sync_alert.2425726524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/1.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1784510058 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 10007880 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:59:02 PM UTC 24 |
| Finished | Aug 23 04:59:04 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784510058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.1784510058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/10.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1570784328 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9316809 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:59:04 PM UTC 24 |
| Finished | Aug 23 04:59:06 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570784328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.1570784328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/11.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.4043098171 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8999640 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 04:59:04 PM UTC 24 |
| Finished | Aug 23 04:59:06 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043098171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.4043098171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/12.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2434799355 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9282897 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 04:59:04 PM UTC 24 |
| Finished | Aug 23 04:59:06 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434799355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 13.prim_sync_alert.2434799355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/13.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3853499793 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8421896 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 04:59:06 PM UTC 24 |
| Finished | Aug 23 04:59:08 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853499793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.3853499793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/15.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.2187722604 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8941544 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:59:06 PM UTC 24 |
| Finished | Aug 23 04:59:08 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187722604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 16.prim_sync_alert.2187722604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/16.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3279239379 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8634415 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 04:59:08 PM UTC 24 |
| Finished | Aug 23 04:59:10 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279239379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 17.prim_sync_alert.3279239379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/17.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.1730326192 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 10467153 ps |
| CPU time | 0.37 seconds |
| Started | Aug 23 04:59:09 PM UTC 24 |
| Finished | Aug 23 04:59:10 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730326192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 18.prim_sync_alert.1730326192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/18.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.4191863899 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9059268 ps |
| CPU time | 0.37 seconds |
| Started | Aug 23 04:59:09 PM UTC 24 |
| Finished | Aug 23 04:59:10 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191863899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 19.prim_sync_alert.4191863899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/19.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3311755463 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8903633 ps |
| CPU time | 0.32 seconds |
| Started | Aug 23 04:58:58 PM UTC 24 |
| Finished | Aug 23 04:58:59 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311755463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 2.prim_sync_alert.3311755463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/2.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2697269172 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9171702 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 04:58:58 PM UTC 24 |
| Finished | Aug 23 04:58:59 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697269172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.2697269172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/4.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.1418509825 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9069777 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 04:59:00 PM UTC 24 |
| Finished | Aug 23 04:59:02 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418509825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 5.prim_sync_alert.1418509825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/5.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2455554712 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10090984 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 04:59:00 PM UTC 24 |
| Finished | Aug 23 04:59:02 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455554712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 6.prim_sync_alert.2455554712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/6.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3975417897 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9293751 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:59:00 PM UTC 24 |
| Finished | Aug 23 04:59:02 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975417897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.3975417897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/7.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2909107003 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9412041 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 04:59:02 PM UTC 24 |
| Finished | Aug 23 04:59:04 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909107003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.2909107003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/8.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3840229836 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9110579 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 04:59:02 PM UTC 24 |
| Finished | Aug 23 04:59:03 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840229836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.3840229836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/9.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2335972889 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26563144 ps |
| CPU time | 0.38 seconds |
| Started | Aug 23 05:01:41 PM UTC 24 |
| Finished | Aug 23 05:01:43 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335972889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2335972889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3117963264 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27717925 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 05:01:41 PM UTC 24 |
| Finished | Aug 23 05:01:43 PM UTC 24 |
| Peak memory | 154248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117963264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3117963264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4075905235 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28677848 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:45 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075905235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.4075905235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1826043135 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27402611 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:45 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826043135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1826043135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2506657130 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28386469 ps |
| CPU time | 0.41 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:46 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506657130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2506657130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3978009902 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26409766 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:46 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978009902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3978009902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2406538602 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27121165 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:46 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406538602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2406538602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1392743331 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26264704 ps |
| CPU time | 0.36 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:46 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392743331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1392743331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2671540163 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26936178 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:46 PM UTC 24 |
| Peak memory | 154124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671540163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2671540163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2585454212 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27372316 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:46 PM UTC 24 |
| Peak memory | 154116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585454212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2585454212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2073138822 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 29071091 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:46 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073138822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2073138822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.412018078 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 29208170 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:46 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412018078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.412018078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.422534174 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27829130 ps |
| CPU time | 0.36 seconds |
| Started | Aug 23 05:01:41 PM UTC 24 |
| Finished | Aug 23 05:01:43 PM UTC 24 |
| Peak memory | 155372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422534174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.422534174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3718769623 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27627117 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 05:01:41 PM UTC 24 |
| Finished | Aug 23 05:01:43 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718769623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3718769623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1226672929 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 26150849 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 05:01:41 PM UTC 24 |
| Finished | Aug 23 05:01:43 PM UTC 24 |
| Peak memory | 153984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226672929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1226672929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.549931012 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27031554 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 05:01:43 PM UTC 24 |
| Finished | Aug 23 05:01:44 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549931012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.549931012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3219948595 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 26415746 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 05:01:43 PM UTC 24 |
| Finished | Aug 23 05:01:44 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219948595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3219948595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3191023593 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28658177 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 05:01:43 PM UTC 24 |
| Finished | Aug 23 05:01:44 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191023593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3191023593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.955302806 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27290780 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 05:01:43 PM UTC 24 |
| Finished | Aug 23 05:01:44 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955302806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.955302806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3428056313 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 29078030 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 05:01:44 PM UTC 24 |
| Finished | Aug 23 05:01:45 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428056313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3428056313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest |
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