| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.88 | 88.88 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.3649649883 |
| 92.60 | 3.72 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 89.29 | 10.71 | 95.83 | 0.00 | 76.74 | 11.63 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.1027873473 |
| 94.50 | 1.90 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 9.30 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.1293864605 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1114664273 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1846206554 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.1736761814 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.4231592755 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.4085694359 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.2311315389 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3959827588 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1230042856 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.1897768050 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.1080026233 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.3565689082 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1259692861 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.374236858 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.110602986 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.1406092370 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1275476697 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1296039007 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.53122937 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.1182245349 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.2020535116 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.1031790606 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3386795420 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2850681715 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.3233368136 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3582661414 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.3506470328 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3952053294 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2339439375 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2686648132 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.1725938263 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1930211360 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.300467112 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3145980554 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.856735067 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.780750829 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.1786981148 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.144522165 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1799078584 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1644091010 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3824481539 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.1541600582 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.139623934 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2298522295 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3267309649 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.3937926753 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.534692701 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.639679513 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.1503699462 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3054798081 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2531551023 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.1483539711 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2182953656 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.1859991652 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2673685067 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1482669128 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1601936966 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.306863235 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1623909004 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2828658469 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.990702999 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1474707592 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.965798826 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.229771286 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3263854869 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2155355068 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2183062864 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2825467906 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3066965869 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2945079158 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.705154396 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2130006592 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4270619730 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.769455026 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4064085701 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4104380968 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.1736761814 | Aug 24 09:34:13 PM UTC 24 | Aug 24 09:34:14 PM UTC 24 | 11487292 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.4231592755 | Aug 24 09:34:13 PM UTC 24 | Aug 24 09:34:14 PM UTC 24 | 11381405 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.3649649883 | Aug 24 09:34:13 PM UTC 24 | Aug 24 09:34:14 PM UTC 24 | 11911358 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.1406092370 | Aug 24 09:34:13 PM UTC 24 | Aug 24 09:34:14 PM UTC 24 | 11146690 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1296039007 | Aug 24 09:34:23 PM UTC 24 | Aug 24 09:34:25 PM UTC 24 | 10542518 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1275476697 | Aug 24 09:34:23 PM UTC 24 | Aug 24 09:34:25 PM UTC 24 | 11293627 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.53122937 | Aug 24 09:34:23 PM UTC 24 | Aug 24 09:34:25 PM UTC 24 | 11013896 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.1182245349 | Aug 24 09:34:23 PM UTC 24 | Aug 24 09:34:25 PM UTC 24 | 11262459 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.2020535116 | Aug 24 09:34:24 PM UTC 24 | Aug 24 09:34:25 PM UTC 24 | 10624173 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.4085694359 | Aug 24 09:34:24 PM UTC 24 | Aug 24 09:34:25 PM UTC 24 | 10455960 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.2311315389 | Aug 24 09:34:24 PM UTC 24 | Aug 24 09:34:25 PM UTC 24 | 12385167 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3959827588 | Aug 24 09:34:24 PM UTC 24 | Aug 24 09:34:25 PM UTC 24 | 12041898 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1230042856 | Aug 24 09:34:24 PM UTC 24 | Aug 24 09:34:25 PM UTC 24 | 10717056 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.1897768050 | Aug 24 09:34:24 PM UTC 24 | Aug 24 09:34:25 PM UTC 24 | 11477392 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.1080026233 | Aug 24 09:34:24 PM UTC 24 | Aug 24 09:34:26 PM UTC 24 | 10621854 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.3565689082 | Aug 24 09:34:24 PM UTC 24 | Aug 24 09:34:26 PM UTC 24 | 10371893 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1259692861 | Aug 24 09:34:25 PM UTC 24 | Aug 24 09:34:27 PM UTC 24 | 11094764 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.110602986 | Aug 24 09:34:26 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 11569635 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.374236858 | Aug 24 09:34:26 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 10965171 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.1293864605 | Aug 24 09:34:26 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 32588796 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.1031790606 | Aug 24 09:34:26 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 29764561 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1930211360 | Aug 24 09:34:26 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 29112031 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.300467112 | Aug 24 09:34:26 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 29560823 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.856735067 | Aug 24 09:34:26 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 31081948 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3145980554 | Aug 24 09:34:26 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 30580284 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.780750829 | Aug 24 09:34:26 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 31205444 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.1786981148 | Aug 24 09:34:27 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 31288112 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1114664273 | Aug 24 09:34:27 PM UTC 24 | Aug 24 09:34:28 PM UTC 24 | 30459348 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.144522165 | Aug 24 09:34:27 PM UTC 24 | Aug 24 09:34:29 PM UTC 24 | 30524397 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3386795420 | Aug 24 09:34:27 PM UTC 24 | Aug 24 09:34:29 PM UTC 24 | 31116183 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2850681715 | Aug 24 09:34:30 PM UTC 24 | Aug 24 09:34:32 PM UTC 24 | 31500676 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3582661414 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:32 PM UTC 24 | 31062269 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.3233368136 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:32 PM UTC 24 | 31514949 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.3506470328 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 29666928 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2339439375 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 31527244 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3952053294 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 30038858 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2686648132 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 28324766 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.1725938263 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 30194434 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1846206554 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 9899193 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1799078584 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 9164288 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3054798081 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 9404378 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2531551023 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 9251308 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.1027873473 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 9978393 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.1483539711 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 9073009 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.1859991652 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 8764332 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2182953656 | Aug 24 09:34:31 PM UTC 24 | Aug 24 09:34:33 PM UTC 24 | 9375613 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1644091010 | Aug 24 09:34:33 PM UTC 24 | Aug 24 09:34:34 PM UTC 24 | 9453771 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2673685067 | Aug 24 09:34:32 PM UTC 24 | Aug 24 09:34:34 PM UTC 24 | 9191343 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1482669128 | Aug 24 09:34:33 PM UTC 24 | Aug 24 09:34:34 PM UTC 24 | 9417315 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.1541600582 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:35 PM UTC 24 | 8806485 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3824481539 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 9593851 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.139623934 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 9479301 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2298522295 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 9790175 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3267309649 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 9786563 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.3937926753 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 9479700 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.639679513 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 10228314 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.534692701 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 9699641 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.1503699462 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 10321029 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.306863235 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 29105597 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1601936966 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 28146477 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.705154396 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 28426052 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3066965869 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 26559687 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2945079158 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 26713220 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2130006592 | Aug 24 09:34:34 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 28623371 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4270619730 | Aug 24 09:34:35 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 26921114 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.769455026 | Aug 24 09:34:35 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 27213079 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4064085701 | Aug 24 09:34:35 PM UTC 24 | Aug 24 09:34:36 PM UTC 24 | 26326474 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4104380968 | Aug 24 09:34:36 PM UTC 24 | Aug 24 09:34:37 PM UTC 24 | 28091232 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2828658469 | Aug 24 09:34:36 PM UTC 24 | Aug 24 09:34:37 PM UTC 24 | 27881604 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1623909004 | Aug 24 09:34:36 PM UTC 24 | Aug 24 09:34:37 PM UTC 24 | 28333789 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.990702999 | Aug 24 09:34:36 PM UTC 24 | Aug 24 09:34:38 PM UTC 24 | 27392446 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1474707592 | Aug 24 09:34:36 PM UTC 24 | Aug 24 09:34:38 PM UTC 24 | 27101067 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.965798826 | Aug 24 09:34:37 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 28616489 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3263854869 | Aug 24 09:34:37 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 26936471 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.229771286 | Aug 24 09:34:37 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 27458339 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2155355068 | Aug 24 09:34:37 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 28661869 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2183062864 | Aug 24 09:34:37 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 28084719 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2825467906 | Aug 24 09:34:37 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 28327576 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.3649649883 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11911358 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:13 PM UTC 24 |
| Finished | Aug 24 09:34:14 PM UTC 24 |
| Peak memory | 155116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649649883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 3.prim_async_alert.3649649883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/3.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.1027873473 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9978393 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027873473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 3.prim_sync_alert.1027873473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/3.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.1293864605 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 32588796 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:26 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293864605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 0.prim_async_fatal_alert.1293864605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1114664273 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30459348 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:27 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114664273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 7.prim_async_fatal_alert.1114664273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1846206554 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9899193 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 154616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846206554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 1.prim_sync_alert.1846206554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/1.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.1736761814 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11487292 ps |
| CPU time | 0.59 seconds |
| Started | Aug 24 09:34:13 PM UTC 24 |
| Finished | Aug 24 09:34:14 PM UTC 24 |
| Peak memory | 154900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736761814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.prim_async_alert.1736761814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/0.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.4231592755 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11381405 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:13 PM UTC 24 |
| Finished | Aug 24 09:34:14 PM UTC 24 |
| Peak memory | 154720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231592755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.prim_async_alert.4231592755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/1.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.4085694359 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10455960 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:24 PM UTC 24 |
| Finished | Aug 24 09:34:25 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085694359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 10.prim_async_alert.4085694359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/10.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.2311315389 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12385167 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:24 PM UTC 24 |
| Finished | Aug 24 09:34:25 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311315389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 11.prim_async_alert.2311315389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/11.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3959827588 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 12041898 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:24 PM UTC 24 |
| Finished | Aug 24 09:34:25 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959827588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 12.prim_async_alert.3959827588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/12.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1230042856 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10717056 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:24 PM UTC 24 |
| Finished | Aug 24 09:34:25 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230042856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.prim_async_alert.1230042856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/13.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.1897768050 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11477392 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:24 PM UTC 24 |
| Finished | Aug 24 09:34:25 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897768050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.1897768050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/14.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.1080026233 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10621854 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:24 PM UTC 24 |
| Finished | Aug 24 09:34:26 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080026233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.1080026233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/15.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.3565689082 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10371893 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:24 PM UTC 24 |
| Finished | Aug 24 09:34:26 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565689082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 16.prim_async_alert.3565689082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/16.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1259692861 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11094764 ps |
| CPU time | 0.59 seconds |
| Started | Aug 24 09:34:25 PM UTC 24 |
| Finished | Aug 24 09:34:27 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259692861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.1259692861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/17.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.374236858 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10965171 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:26 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374236858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 18.prim_async_alert.374236858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/18.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.110602986 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11569635 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:26 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110602986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 19.prim_async_alert.110602986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/19.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.1406092370 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11146690 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:13 PM UTC 24 |
| Finished | Aug 24 09:34:14 PM UTC 24 |
| Peak memory | 155100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406092370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.prim_async_alert.1406092370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/2.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1275476697 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11293627 ps |
| CPU time | 0.59 seconds |
| Started | Aug 24 09:34:23 PM UTC 24 |
| Finished | Aug 24 09:34:25 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275476697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 4.prim_async_alert.1275476697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/4.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1296039007 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10542518 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:23 PM UTC 24 |
| Finished | Aug 24 09:34:25 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296039007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 5.prim_async_alert.1296039007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/5.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.53122937 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11013896 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:23 PM UTC 24 |
| Finished | Aug 24 09:34:25 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53122937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 7.prim_async_alert.53122937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/7.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.1182245349 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11262459 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:23 PM UTC 24 |
| Finished | Aug 24 09:34:25 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182245349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.prim_async_alert.1182245349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/8.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.2020535116 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10624173 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:24 PM UTC 24 |
| Finished | Aug 24 09:34:25 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020535116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.2020535116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/9.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.1031790606 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 29764561 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:26 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031790606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.1031790606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3386795420 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 31116183 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:27 PM UTC 24 |
| Finished | Aug 24 09:34:29 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386795420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.3386795420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2850681715 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 31500676 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:30 PM UTC 24 |
| Finished | Aug 24 09:34:32 PM UTC 24 |
| Peak memory | 154368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850681715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.2850681715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.3233368136 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 31514949 ps |
| CPU time | 0.61 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:32 PM UTC 24 |
| Peak memory | 154504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233368136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 12.prim_async_fatal_alert.3233368136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3582661414 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 31062269 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:32 PM UTC 24 |
| Peak memory | 154932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582661414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 13.prim_async_fatal_alert.3582661414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.3506470328 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 29666928 ps |
| CPU time | 0.61 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506470328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 14.prim_async_fatal_alert.3506470328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3952053294 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30038858 ps |
| CPU time | 0.62 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 154944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952053294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.3952053294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2339439375 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31527244 ps |
| CPU time | 0.59 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339439375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 16.prim_async_fatal_alert.2339439375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2686648132 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 28324766 ps |
| CPU time | 0.59 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686648132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 17.prim_async_fatal_alert.2686648132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.1725938263 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30194434 ps |
| CPU time | 0.59 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725938263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 19.prim_async_fatal_alert.1725938263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1930211360 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 29112031 ps |
| CPU time | 0.63 seconds |
| Started | Aug 24 09:34:26 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930211360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.1930211360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.300467112 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 29560823 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:26 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300467112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 3.prim_async_fatal_alert.300467112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3145980554 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30580284 ps |
| CPU time | 0.61 seconds |
| Started | Aug 24 09:34:26 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145980554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 4.prim_async_fatal_alert.3145980554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.856735067 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 31081948 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:26 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856735067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 5.prim_async_fatal_alert.856735067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.780750829 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 31205444 ps |
| CPU time | 0.61 seconds |
| Started | Aug 24 09:34:26 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780750829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 6.prim_async_fatal_alert.780750829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.1786981148 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31288112 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:27 PM UTC 24 |
| Finished | Aug 24 09:34:28 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786981148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 8.prim_async_fatal_alert.1786981148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.144522165 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30524397 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:27 PM UTC 24 |
| Finished | Aug 24 09:34:29 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144522165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 9.prim_async_fatal_alert.144522165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1799078584 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9164288 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799078584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.1799078584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/0.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1644091010 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9453771 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:33 PM UTC 24 |
| Finished | Aug 24 09:34:34 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644091010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.1644091010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/10.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3824481539 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9593851 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824481539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.3824481539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/11.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.1541600582 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8806485 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:35 PM UTC 24 |
| Peak memory | 154488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541600582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.1541600582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/12.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.139623934 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9479301 ps |
| CPU time | 0.55 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139623934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 13.prim_sync_alert.139623934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/13.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2298522295 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9790175 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298522295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.2298522295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/14.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3267309649 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9786563 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267309649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.3267309649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/15.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.3937926753 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9479700 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937926753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 16.prim_sync_alert.3937926753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/16.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.534692701 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9699641 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534692701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 17.prim_sync_alert.534692701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/17.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.639679513 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 10228314 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639679513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 18.prim_sync_alert.639679513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/18.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.1503699462 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10321029 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503699462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 19.prim_sync_alert.1503699462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/19.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3054798081 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9404378 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054798081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 2.prim_sync_alert.3054798081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/2.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2531551023 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9251308 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531551023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.2531551023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/4.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.1483539711 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9073009 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483539711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 5.prim_sync_alert.1483539711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/5.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2182953656 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9375613 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182953656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 6.prim_sync_alert.2182953656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/6.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.1859991652 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8764332 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:31 PM UTC 24 |
| Finished | Aug 24 09:34:33 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859991652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.1859991652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/7.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2673685067 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9191343 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:32 PM UTC 24 |
| Finished | Aug 24 09:34:34 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673685067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.2673685067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/8.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1482669128 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9417315 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:33 PM UTC 24 |
| Finished | Aug 24 09:34:34 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482669128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.1482669128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/9.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1601936966 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 28146477 ps |
| CPU time | 0.61 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601936966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1601936966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.306863235 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 29105597 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306863235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.306863235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1623909004 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28333789 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:36 PM UTC 24 |
| Finished | Aug 24 09:34:37 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623909004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1623909004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2828658469 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27881604 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:36 PM UTC 24 |
| Finished | Aug 24 09:34:37 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828658469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2828658469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.990702999 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27392446 ps |
| CPU time | 0.62 seconds |
| Started | Aug 24 09:34:36 PM UTC 24 |
| Finished | Aug 24 09:34:38 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990702999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.990702999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1474707592 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27101067 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:36 PM UTC 24 |
| Finished | Aug 24 09:34:38 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474707592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1474707592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.965798826 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 28616489 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:37 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965798826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.965798826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.229771286 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27458339 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:37 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 153968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229771286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.229771286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3263854869 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26936471 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:37 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 153868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263854869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3263854869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2155355068 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28661869 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:37 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155355068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2155355068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2183062864 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28084719 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:37 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183062864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2183062864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2825467906 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 28327576 ps |
| CPU time | 0.61 seconds |
| Started | Aug 24 09:34:37 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 154184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825467906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2825467906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3066965869 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26559687 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066965869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3066965869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2945079158 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26713220 ps |
| CPU time | 0.59 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945079158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2945079158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.705154396 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 28426052 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705154396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.705154396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2130006592 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28623371 ps |
| CPU time | 0.6 seconds |
| Started | Aug 24 09:34:34 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130006592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2130006592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4270619730 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26921114 ps |
| CPU time | 0.59 seconds |
| Started | Aug 24 09:34:35 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270619730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.4270619730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.769455026 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27213079 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:35 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769455026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.769455026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4064085701 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 26326474 ps |
| CPU time | 0.58 seconds |
| Started | Aug 24 09:34:35 PM UTC 24 |
| Finished | Aug 24 09:34:36 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064085701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.4064085701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4104380968 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28091232 ps |
| CPU time | 0.61 seconds |
| Started | Aug 24 09:34:36 PM UTC 24 |
| Finished | Aug 24 09:34:37 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104380968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.4104380968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |