Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.85	100.00	97.92	100.00	89.29	95.83	86.05

Total tests in report: 80

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
87.94	87.94	100.00	100.00	91.67	91.67	100.00	100.00	75.00	75.00	95.83	95.83	65.12	65.12	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.578878706
91.23	3.30	100.00	0.00	93.75	2.08	100.00	0.00	85.71	10.71	95.83	0.00	72.09	6.98	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.2259737995
93.17	1.94	100.00	0.00	93.75	0.00	100.00	0.00	85.71	0.00	95.83	0.00	83.72	11.63	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1558721533
94.85	1.68	100.00	0.00	97.92	4.17	100.00	0.00	89.29	3.57	95.83	0.00	86.05	2.33	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.861432011

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.1248434255
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3745946531
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.39464698
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.203442534
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.124982943
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1562060506
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2175668779
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.150543339
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.358736469
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.4054941914
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2625103224
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.273115697
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.3267595660
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.1940436663
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.654273766
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1656144184
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3897165102
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1545930715
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.1968794235
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2654354128
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1767423275
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.919346615
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.73455679
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3076704801
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2785906257
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3538654650
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.226842738
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.3097043119
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.612424500
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2050926525
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1525624469
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.141332153
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3833629798
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.775715303
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2845626066
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.2804143583
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.4002548815
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.991813036
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1069766445
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2011867220
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.4079243205
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.985542982
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1452680692
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.429237882
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.2145163487
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.2103212180
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.11749165
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.4248323126
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2662517581
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.149399704
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2596488097
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3182287644
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2694943503
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.574537840
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3348011134
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.4057185880
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3165332160
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3803416394
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2480908076
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4165700945
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3585102543
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1957173464
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2335147399
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.813041631
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3174790990
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2864435105
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3085055436
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.808207642
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2394816886
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2205760203
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.965105424
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3951182125
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.637763969
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.175155804
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.217089707
/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3176030035

Total test records in report: 80

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.1940436663	Aug 27 12:02:59 AM UTC 24	Aug 27 12:03:00 AM UTC 24	10952535 ps
T2	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3745946531	Aug 27 12:02:59 AM UTC 24	Aug 27 12:03:00 AM UTC 24	11122640 ps
T3	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.1248434255	Aug 27 12:02:59 AM UTC 24	Aug 27 12:03:00 AM UTC 24	10645624 ps
T11	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.3267595660	Aug 27 12:02:59 AM UTC 24	Aug 27 12:03:01 AM UTC 24	11428510 ps
T10	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.578878706	Aug 27 12:02:59 AM UTC 24	Aug 27 12:03:01 AM UTC 24	12498448 ps
T7	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1656144184	Aug 27 12:02:59 AM UTC 24	Aug 27 12:03:01 AM UTC 24	11336365 ps
T9	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.654273766	Aug 27 12:02:59 AM UTC 24	Aug 27 12:03:01 AM UTC 24	11763503 ps
T8	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.861432011	Aug 27 12:02:59 AM UTC 24	Aug 27 12:03:01 AM UTC 24	11846829 ps
T18	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3897165102	Aug 27 12:02:59 AM UTC 24	Aug 27 12:03:01 AM UTC 24	10620223 ps
T19	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1545930715	Aug 27 12:02:59 AM UTC 24	Aug 27 12:03:01 AM UTC 24	10701331 ps
T15	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.203442534	Aug 27 12:03:00 AM UTC 24	Aug 27 12:03:02 AM UTC 24	11732361 ps
T12	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.124982943	Aug 27 12:03:00 AM UTC 24	Aug 27 12:03:02 AM UTC 24	12296043 ps
T13	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2175668779	Aug 27 12:03:00 AM UTC 24	Aug 27 12:03:02 AM UTC 24	11797082 ps
T16	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.39464698	Aug 27 12:03:00 AM UTC 24	Aug 27 12:03:02 AM UTC 24	11672766 ps
T45	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1562060506	Aug 27 12:03:00 AM UTC 24	Aug 27 12:03:02 AM UTC 24	12000095 ps
T20	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.150543339	Aug 27 12:03:00 AM UTC 24	Aug 27 12:03:02 AM UTC 24	12579479 ps
T17	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.358736469	Aug 27 12:03:00 AM UTC 24	Aug 27 12:03:02 AM UTC 24	11581715 ps
T21	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.273115697	Aug 27 12:03:01 AM UTC 24	Aug 27 12:03:03 AM UTC 24	11082381 ps
T46	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2625103224	Aug 27 12:03:01 AM UTC 24	Aug 27 12:03:03 AM UTC 24	11084843 ps
T47	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.4054941914	Aug 27 12:03:01 AM UTC 24	Aug 27 12:03:03 AM UTC 24	11075147 ps
T14	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.1968794235	Aug 27 12:02:38 AM UTC 24	Aug 27 12:02:39 AM UTC 24	31841011 ps
T38	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1525624469	Aug 27 12:02:40 AM UTC 24	Aug 27 12:02:41 AM UTC 24	29723931 ps
T39	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2654354128	Aug 27 12:02:40 AM UTC 24	Aug 27 12:02:41 AM UTC 24	30571610 ps
T40	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.141332153	Aug 27 12:02:41 AM UTC 24	Aug 27 12:02:42 AM UTC 24	29854858 ps
T41	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.775715303	Aug 27 12:02:42 AM UTC 24	Aug 27 12:02:43 AM UTC 24	29630921 ps
T42	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.2804143583	Aug 27 12:02:42 AM UTC 24	Aug 27 12:02:43 AM UTC 24	30339736 ps
T4	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3833629798	Aug 27 12:02:42 AM UTC 24	Aug 27 12:02:43 AM UTC 24	28913654 ps
T43	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2845626066	Aug 27 12:02:42 AM UTC 24	Aug 27 12:02:43 AM UTC 24	30792194 ps
T5	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.2259737995	Aug 27 12:02:42 AM UTC 24	Aug 27 12:02:43 AM UTC 24	29212993 ps
T44	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.4002548815	Aug 27 12:02:42 AM UTC 24	Aug 27 12:02:43 AM UTC 24	30622963 ps
T37	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3538654650	Aug 27 12:02:43 AM UTC 24	Aug 27 12:02:44 AM UTC 24	29890330 ps
T48	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1767423275	Aug 27 12:02:43 AM UTC 24	Aug 27 12:02:44 AM UTC 24	31743900 ps
T49	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.3097043119	Aug 27 12:02:43 AM UTC 24	Aug 27 12:02:45 AM UTC 24	29707840 ps
T50	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.919346615	Aug 27 12:02:43 AM UTC 24	Aug 27 12:02:45 AM UTC 24	31917011 ps
T51	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3076704801	Aug 27 12:02:43 AM UTC 24	Aug 27 12:02:45 AM UTC 24	28160674 ps
T52	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.73455679	Aug 27 12:02:43 AM UTC 24	Aug 27 12:02:45 AM UTC 24	29668689 ps
T53	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2785906257	Aug 27 12:02:43 AM UTC 24	Aug 27 12:02:45 AM UTC 24	29592791 ps
T54	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.226842738	Aug 27 12:02:43 AM UTC 24	Aug 27 12:02:45 AM UTC 24	31102129 ps
T55	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.612424500	Aug 27 12:02:43 AM UTC 24	Aug 27 12:02:45 AM UTC 24	29969946 ps
T56	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2050926525	Aug 27 12:02:43 AM UTC 24	Aug 27 12:02:45 AM UTC 24	28645680 ps
T22	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1558721533	Aug 27 12:03:01 AM UTC 24	Aug 27 12:03:03 AM UTC 24	9786926 ps
T32	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.149399704	Aug 27 12:03:02 AM UTC 24	Aug 27 12:03:03 AM UTC 24	9530165 ps
T33	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2662517581	Aug 27 12:03:01 AM UTC 24	Aug 27 12:03:03 AM UTC 24	9603387 ps
T23	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.991813036	Aug 27 12:03:01 AM UTC 24	Aug 27 12:03:03 AM UTC 24	9208597 ps
T24	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3182287644	Aug 27 12:03:02 AM UTC 24	Aug 27 12:03:03 AM UTC 24	9655794 ps
T34	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2596488097	Aug 27 12:03:02 AM UTC 24	Aug 27 12:03:03 AM UTC 24	9574930 ps
T25	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2694943503	Aug 27 12:03:02 AM UTC 24	Aug 27 12:03:03 AM UTC 24	9632383 ps
T35	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.574537840	Aug 27 12:03:02 AM UTC 24	Aug 27 12:03:03 AM UTC 24	8783671 ps
T36	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.4057185880	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:04 AM UTC 24	9830033 ps
T26	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3348011134	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:04 AM UTC 24	9356003 ps
T27	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1069766445	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:04 AM UTC 24	8523680 ps
T57	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.4079243205	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:04 AM UTC 24	9053536 ps
T58	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2011867220	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:05 AM UTC 24	9802934 ps
T59	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.985542982	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:05 AM UTC 24	8707803 ps
T60	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1452680692	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:05 AM UTC 24	9794177 ps
T28	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.2103212180	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:05 AM UTC 24	9111210 ps
T61	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.4248323126	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:05 AM UTC 24	9311183 ps
T62	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.429237882	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:05 AM UTC 24	9030694 ps
T63	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.2145163487	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:05 AM UTC 24	9451008 ps
T29	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.11749165	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:05 AM UTC 24	9822038 ps
T30	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3165332160	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:05 AM UTC 24	28148809 ps
T64	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3803416394	Aug 27 12:03:03 AM UTC 24	Aug 27 12:03:05 AM UTC 24	26883176 ps
T31	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2394816886	Aug 27 12:03:04 AM UTC 24	Aug 27 12:03:06 AM UTC 24	27830905 ps
T65	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.965105424	Aug 27 12:03:04 AM UTC 24	Aug 27 12:03:06 AM UTC 24	27168217 ps
T6	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2205760203	Aug 27 12:03:04 AM UTC 24	Aug 27 12:03:06 AM UTC 24	28979039 ps
T66	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3951182125	Aug 27 12:03:04 AM UTC 24	Aug 27 12:03:06 AM UTC 24	27216845 ps
T67	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.637763969	Aug 27 12:03:04 AM UTC 24	Aug 27 12:03:06 AM UTC 24	28975458 ps
T68	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.217089707	Aug 27 12:03:05 AM UTC 24	Aug 27 12:03:06 AM UTC 24	27545348 ps
T69	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2480908076	Aug 27 12:03:05 AM UTC 24	Aug 27 12:03:06 AM UTC 24	26173004 ps
T70	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.175155804	Aug 27 12:03:05 AM UTC 24	Aug 27 12:03:06 AM UTC 24	29812360 ps
T71	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3176030035	Aug 27 12:03:05 AM UTC 24	Aug 27 12:03:06 AM UTC 24	27495023 ps
T72	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3585102543	Aug 27 12:03:05 AM UTC 24	Aug 27 12:03:06 AM UTC 24	27004040 ps
T73	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2335147399	Aug 27 12:03:05 AM UTC 24	Aug 27 12:03:06 AM UTC 24	29258479 ps
T74	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4165700945	Aug 27 12:03:05 AM UTC 24	Aug 27 12:03:06 AM UTC 24	28467788 ps
T75	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1957173464	Aug 27 12:03:05 AM UTC 24	Aug 27 12:03:06 AM UTC 24	28821526 ps
T76	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3174790990	Aug 27 12:03:06 AM UTC 24	Aug 27 12:03:07 AM UTC 24	29082820 ps
T77	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.813041631	Aug 27 12:03:06 AM UTC 24	Aug 27 12:03:08 AM UTC 24	29746630 ps
T78	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2864435105	Aug 27 12:03:06 AM UTC 24	Aug 27 12:03:08 AM UTC 24	32230963 ps
T79	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.808207642	Aug 27 12:03:06 AM UTC 24	Aug 27 12:03:08 AM UTC 24	27306570 ps
T80	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3085055436	Aug 27 12:03:06 AM UTC 24	Aug 27 12:03:08 AM UTC 24	26124970 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.578878706
Short name	T10
Test name
Test status
Simulation time	12498448 ps
CPU time	0.41 seconds
Started	Aug 27 12:02:59 AM UTC 24
Finished	Aug 27 12:03:01 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578878706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 4.prim_async_alert.578878706
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/4.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.2259737995
Short name	T5
Test name
Test status
Simulation time	29212993 ps
CPU time	0.36 seconds
Started	Aug 27 12:02:42 AM UTC 24
Finished	Aug 27 12:02:43 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259737995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 9.prim_async_fatal_alert.2259737995
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1558721533
Short name	T22
Test name
Test status
Simulation time	9786926 ps
CPU time	0.48 seconds
Started	Aug 27 12:03:01 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	154612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558721533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.1558721533
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/0.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.861432011
Short name	T8
Test name
Test status
Simulation time	11846829 ps
CPU time	0.46 seconds
Started	Aug 27 12:02:59 AM UTC 24
Finished	Aug 27 12:03:01 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861432011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 5.prim_async_alert.861432011
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/5.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.1248434255
Short name	T3
Test name
Test status
Simulation time	10645624 ps
CPU time	0.49 seconds
Started	Aug 27 12:02:59 AM UTC 24
Finished	Aug 27 12:03:00 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248434255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.prim_async_alert.1248434255
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/0.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3745946531
Short name	T2
Test name
Test status
Simulation time	11122640 ps
CPU time	0.45 seconds
Started	Aug 27 12:02:59 AM UTC 24
Finished	Aug 27 12:03:00 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745946531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.prim_async_alert.3745946531
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/1.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.39464698
Short name	T16
Test name
Test status
Simulation time	11672766 ps
CPU time	0.56 seconds
Started	Aug 27 12:03:00 AM UTC 24
Finished	Aug 27 12:03:02 AM UTC 24
Peak memory	155168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39464698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 10.prim_async_alert.39464698
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/10.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.203442534
Short name	T15
Test name
Test status
Simulation time	11732361 ps
CPU time	0.44 seconds
Started	Aug 27 12:03:00 AM UTC 24
Finished	Aug 27 12:03:02 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203442534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 11.prim_async_alert.203442534
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/11.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.124982943
Short name	T12
Test name
Test status
Simulation time	12296043 ps
CPU time	0.41 seconds
Started	Aug 27 12:03:00 AM UTC 24
Finished	Aug 27 12:03:02 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124982943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 12.prim_async_alert.124982943
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/12.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1562060506
Short name	T45
Test name
Test status
Simulation time	12000095 ps
CPU time	0.51 seconds
Started	Aug 27 12:03:00 AM UTC 24
Finished	Aug 27 12:03:02 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562060506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.prim_async_alert.1562060506
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/13.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2175668779
Short name	T13
Test name
Test status
Simulation time	11797082 ps
CPU time	0.47 seconds
Started	Aug 27 12:03:00 AM UTC 24
Finished	Aug 27 12:03:02 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175668779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.2175668779
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/14.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.150543339
Short name	T20
Test name
Test status
Simulation time	12579479 ps
CPU time	0.5 seconds
Started	Aug 27 12:03:00 AM UTC 24
Finished	Aug 27 12:03:02 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150543339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 15.prim_async_alert.150543339
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/15.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.358736469
Short name	T17
Test name
Test status
Simulation time	11581715 ps
CPU time	0.49 seconds
Started	Aug 27 12:03:00 AM UTC 24
Finished	Aug 27 12:03:02 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358736469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 16.prim_async_alert.358736469
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/16.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.4054941914
Short name	T47
Test name
Test status
Simulation time	11075147 ps
CPU time	0.51 seconds
Started	Aug 27 12:03:01 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054941914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.4054941914
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/17.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2625103224
Short name	T46
Test name
Test status
Simulation time	11084843 ps
CPU time	0.4 seconds
Started	Aug 27 12:03:01 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625103224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.prim_async_alert.2625103224
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/18.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.273115697
Short name	T21
Test name
Test status
Simulation time	11082381 ps
CPU time	0.42 seconds
Started	Aug 27 12:03:01 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273115697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 19.prim_async_alert.273115697
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/19.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.3267595660
Short name	T11
Test name
Test status
Simulation time	11428510 ps
CPU time	0.44 seconds
Started	Aug 27 12:02:59 AM UTC 24
Finished	Aug 27 12:03:01 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267595660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.prim_async_alert.3267595660
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/2.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.1940436663
Short name	T1
Test name
Test status
Simulation time	10952535 ps
CPU time	0.4 seconds
Started	Aug 27 12:02:59 AM UTC 24
Finished	Aug 27 12:03:00 AM UTC 24
Peak memory	155224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940436663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 3.prim_async_alert.1940436663
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/3.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.654273766
Short name	T9
Test name
Test status
Simulation time	11763503 ps
CPU time	0.41 seconds
Started	Aug 27 12:02:59 AM UTC 24
Finished	Aug 27 12:03:01 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654273766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 6.prim_async_alert.654273766
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/6.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1656144184
Short name	T7
Test name
Test status
Simulation time	11336365 ps
CPU time	0.48 seconds
Started	Aug 27 12:02:59 AM UTC 24
Finished	Aug 27 12:03:01 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656144184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 7.prim_async_alert.1656144184
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/7.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3897165102
Short name	T18
Test name
Test status
Simulation time	10620223 ps
CPU time	0.45 seconds
Started	Aug 27 12:02:59 AM UTC 24
Finished	Aug 27 12:03:01 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897165102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.prim_async_alert.3897165102
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/8.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1545930715
Short name	T19
Test name
Test status
Simulation time	10701331 ps
CPU time	0.51 seconds
Started	Aug 27 12:02:59 AM UTC 24
Finished	Aug 27 12:03:01 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545930715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.1545930715
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/9.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.1968794235
Short name	T14
Test name
Test status
Simulation time	31841011 ps
CPU time	0.56 seconds
Started	Aug 27 12:02:38 AM UTC 24
Finished	Aug 27 12:02:39 AM UTC 24
Peak memory	155084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968794235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 0.prim_async_fatal_alert.1968794235
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2654354128
Short name	T39
Test name
Test status
Simulation time	30571610 ps
CPU time	0.35 seconds
Started	Aug 27 12:02:40 AM UTC 24
Finished	Aug 27 12:02:41 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654354128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.2654354128
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1767423275
Short name	T48
Test name
Test status
Simulation time	31743900 ps
CPU time	0.44 seconds
Started	Aug 27 12:02:43 AM UTC 24
Finished	Aug 27 12:02:44 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767423275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.1767423275
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.919346615
Short name	T50
Test name
Test status
Simulation time	31917011 ps
CPU time	0.45 seconds
Started	Aug 27 12:02:43 AM UTC 24
Finished	Aug 27 12:02:45 AM UTC 24
Peak memory	155780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919346615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 11.prim_async_fatal_alert.919346615
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.73455679
Short name	T52
Test name
Test status
Simulation time	29668689 ps
CPU time	0.45 seconds
Started	Aug 27 12:02:43 AM UTC 24
Finished	Aug 27 12:02:45 AM UTC 24
Peak memory	155016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73455679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 12.prim_async_fatal_alert.73455679
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3076704801
Short name	T51
Test name
Test status
Simulation time	28160674 ps
CPU time	0.41 seconds
Started	Aug 27 12:02:43 AM UTC 24
Finished	Aug 27 12:02:45 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076704801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 13.prim_async_fatal_alert.3076704801
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2785906257
Short name	T53
Test name
Test status
Simulation time	29592791 ps
CPU time	0.43 seconds
Started	Aug 27 12:02:43 AM UTC 24
Finished	Aug 27 12:02:45 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785906257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 14.prim_async_fatal_alert.2785906257
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3538654650
Short name	T37
Test name
Test status
Simulation time	29890330 ps
CPU time	0.36 seconds
Started	Aug 27 12:02:43 AM UTC 24
Finished	Aug 27 12:02:44 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538654650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.3538654650
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.226842738
Short name	T54
Test name
Test status
Simulation time	31102129 ps
CPU time	0.42 seconds
Started	Aug 27 12:02:43 AM UTC 24
Finished	Aug 27 12:02:45 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226842738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 16.prim_async_fatal_alert.226842738
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.3097043119
Short name	T49
Test name
Test status
Simulation time	29707840 ps
CPU time	0.35 seconds
Started	Aug 27 12:02:43 AM UTC 24
Finished	Aug 27 12:02:45 AM UTC 24
Peak memory	156144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097043119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 17.prim_async_fatal_alert.3097043119
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.612424500
Short name	T55
Test name
Test status
Simulation time	29969946 ps
CPU time	0.39 seconds
Started	Aug 27 12:02:43 AM UTC 24
Finished	Aug 27 12:02:45 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612424500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 18.prim_async_fatal_alert.612424500
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2050926525
Short name	T56
Test name
Test status
Simulation time	28645680 ps
CPU time	0.38 seconds
Started	Aug 27 12:02:43 AM UTC 24
Finished	Aug 27 12:02:45 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050926525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 19.prim_async_fatal_alert.2050926525
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1525624469
Short name	T38
Test name
Test status
Simulation time	29723931 ps
CPU time	0.34 seconds
Started	Aug 27 12:02:40 AM UTC 24
Finished	Aug 27 12:02:41 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525624469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.1525624469
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.141332153
Short name	T40
Test name
Test status
Simulation time	29854858 ps
CPU time	0.37 seconds
Started	Aug 27 12:02:41 AM UTC 24
Finished	Aug 27 12:02:42 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141332153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 3.prim_async_fatal_alert.141332153
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3833629798
Short name	T4
Test name
Test status
Simulation time	28913654 ps
CPU time	0.4 seconds
Started	Aug 27 12:02:42 AM UTC 24
Finished	Aug 27 12:02:43 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833629798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 4.prim_async_fatal_alert.3833629798
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.775715303
Short name	T41
Test name
Test status
Simulation time	29630921 ps
CPU time	0.37 seconds
Started	Aug 27 12:02:42 AM UTC 24
Finished	Aug 27 12:02:43 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775715303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 5.prim_async_fatal_alert.775715303
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2845626066
Short name	T43
Test name
Test status
Simulation time	30792194 ps
CPU time	0.43 seconds
Started	Aug 27 12:02:42 AM UTC 24
Finished	Aug 27 12:02:43 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845626066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 6.prim_async_fatal_alert.2845626066
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.2804143583
Short name	T42
Test name
Test status
Simulation time	30339736 ps
CPU time	0.38 seconds
Started	Aug 27 12:02:42 AM UTC 24
Finished	Aug 27 12:02:43 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804143583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 7.prim_async_fatal_alert.2804143583
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.4002548815
Short name	T44
Test name
Test status
Simulation time	30622963 ps
CPU time	0.42 seconds
Started	Aug 27 12:02:42 AM UTC 24
Finished	Aug 27 12:02:43 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002548815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 8.prim_async_fatal_alert.4002548815
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.991813036
Short name	T23
Test name
Test status
Simulation time	9208597 ps
CPU time	0.48 seconds
Started	Aug 27 12:03:01 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991813036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 1.prim_sync_alert.991813036
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/1.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1069766445
Short name	T27
Test name
Test status
Simulation time	8523680 ps
CPU time	0.45 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:04 AM UTC 24
Peak memory	154476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069766445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.1069766445
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/10.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2011867220
Short name	T58
Test name
Test status
Simulation time	9802934 ps
CPU time	0.52 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:05 AM UTC 24
Peak memory	154524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011867220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.2011867220
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/11.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.4079243205
Short name	T57
Test name
Test status
Simulation time	9053536 ps
CPU time	0.45 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:04 AM UTC 24
Peak memory	154512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079243205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.4079243205
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/12.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.985542982
Short name	T59
Test name
Test status
Simulation time	8707803 ps
CPU time	0.46 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:05 AM UTC 24
Peak memory	154552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985542982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 13.prim_sync_alert.985542982
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/13.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1452680692
Short name	T60
Test name
Test status
Simulation time	9794177 ps
CPU time	0.43 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:05 AM UTC 24
Peak memory	154540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452680692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.1452680692
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/14.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.429237882
Short name	T62
Test name
Test status
Simulation time	9030694 ps
CPU time	0.46 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:05 AM UTC 24
Peak memory	154552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429237882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 15.prim_sync_alert.429237882
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/15.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.2145163487
Short name	T63
Test name
Test status
Simulation time	9451008 ps
CPU time	0.46 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:05 AM UTC 24
Peak memory	154544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145163487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 16.prim_sync_alert.2145163487
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/16.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.2103212180
Short name	T28
Test name
Test status
Simulation time	9111210 ps
CPU time	0.44 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:05 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103212180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 17.prim_sync_alert.2103212180
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/17.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.11749165
Short name	T29
Test name
Test status
Simulation time	9822038 ps
CPU time	0.42 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:05 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11749165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.11749165
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/18.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.4248323126
Short name	T61
Test name
Test status
Simulation time	9311183 ps
CPU time	0.44 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:05 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248323126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 19.prim_sync_alert.4248323126
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/19.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2662517581
Short name	T33
Test name
Test status
Simulation time	9603387 ps
CPU time	0.5 seconds
Started	Aug 27 12:03:01 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662517581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 2.prim_sync_alert.2662517581
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/2.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.149399704
Short name	T32
Test name
Test status
Simulation time	9530165 ps
CPU time	0.41 seconds
Started	Aug 27 12:03:02 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149399704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 3.prim_sync_alert.149399704
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/3.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2596488097
Short name	T34
Test name
Test status
Simulation time	9574930 ps
CPU time	0.46 seconds
Started	Aug 27 12:03:02 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	154544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596488097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.2596488097
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/4.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3182287644
Short name	T24
Test name
Test status
Simulation time	9655794 ps
CPU time	0.4 seconds
Started	Aug 27 12:03:02 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182287644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 5.prim_sync_alert.3182287644
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/5.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2694943503
Short name	T25
Test name
Test status
Simulation time	9632383 ps
CPU time	0.47 seconds
Started	Aug 27 12:03:02 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694943503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 6.prim_sync_alert.2694943503
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/6.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.574537840
Short name	T35
Test name
Test status
Simulation time	8783671 ps
CPU time	0.47 seconds
Started	Aug 27 12:03:02 AM UTC 24
Finished	Aug 27 12:03:03 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574537840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 7.prim_sync_alert.574537840
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/7.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3348011134
Short name	T26
Test name
Test status
Simulation time	9356003 ps
CPU time	0.48 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:04 AM UTC 24
Peak memory	154508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348011134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.3348011134
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/8.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.4057185880
Short name	T36
Test name
Test status
Simulation time	9830033 ps
CPU time	0.49 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:04 AM UTC 24
Peak memory	154524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057185880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.4057185880
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/9.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3165332160
Short name	T30
Test name
Test status
Simulation time	28148809 ps
CPU time	0.42 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:05 AM UTC 24
Peak memory	154252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165332160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3165332160
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3803416394
Short name	T64
Test name
Test status
Simulation time	26883176 ps
CPU time	0.45 seconds
Started	Aug 27 12:03:03 AM UTC 24
Finished	Aug 27 12:03:05 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803416394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3803416394
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2480908076
Short name	T69
Test name
Test status
Simulation time	26173004 ps
CPU time	0.47 seconds
Started	Aug 27 12:03:05 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480908076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2480908076
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4165700945
Short name	T74
Test name
Test status
Simulation time	28467788 ps
CPU time	0.43 seconds
Started	Aug 27 12:03:05 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165700945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4165700945
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3585102543
Short name	T72
Test name
Test status
Simulation time	27004040 ps
CPU time	0.48 seconds
Started	Aug 27 12:03:05 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585102543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3585102543
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1957173464
Short name	T75
Test name
Test status
Simulation time	28821526 ps
CPU time	0.43 seconds
Started	Aug 27 12:03:05 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957173464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1957173464
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2335147399
Short name	T73
Test name
Test status
Simulation time	29258479 ps
CPU time	0.37 seconds
Started	Aug 27 12:03:05 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335147399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2335147399
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.813041631
Short name	T77
Test name
Test status
Simulation time	29746630 ps
CPU time	0.43 seconds
Started	Aug 27 12:03:06 AM UTC 24
Finished	Aug 27 12:03:08 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813041631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.813041631
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3174790990
Short name	T76
Test name
Test status
Simulation time	29082820 ps
CPU time	0.45 seconds
Started	Aug 27 12:03:06 AM UTC 24
Finished	Aug 27 12:03:07 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174790990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3174790990
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2864435105
Short name	T78
Test name
Test status
Simulation time	32230963 ps
CPU time	0.46 seconds
Started	Aug 27 12:03:06 AM UTC 24
Finished	Aug 27 12:03:08 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864435105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2864435105
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3085055436
Short name	T80
Test name
Test status
Simulation time	26124970 ps
CPU time	0.48 seconds
Started	Aug 27 12:03:06 AM UTC 24
Finished	Aug 27 12:03:08 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085055436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3085055436
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.808207642
Short name	T79
Test name
Test status
Simulation time	27306570 ps
CPU time	0.42 seconds
Started	Aug 27 12:03:06 AM UTC 24
Finished	Aug 27 12:03:08 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808207642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.808207642
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2394816886
Short name	T31
Test name
Test status
Simulation time	27830905 ps
CPU time	0.4 seconds
Started	Aug 27 12:03:04 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394816886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2394816886
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2205760203
Short name	T6
Test name
Test status
Simulation time	28979039 ps
CPU time	0.41 seconds
Started	Aug 27 12:03:04 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205760203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2205760203
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.965105424
Short name	T65
Test name
Test status
Simulation time	27168217 ps
CPU time	0.49 seconds
Started	Aug 27 12:03:04 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965105424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.965105424
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3951182125
Short name	T66
Test name
Test status
Simulation time	27216845 ps
CPU time	0.41 seconds
Started	Aug 27 12:03:04 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951182125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3951182125
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.637763969
Short name	T67
Test name
Test status
Simulation time	28975458 ps
CPU time	0.44 seconds
Started	Aug 27 12:03:04 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637763969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.637763969
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.175155804
Short name	T70
Test name
Test status
Simulation time	29812360 ps
CPU time	0.49 seconds
Started	Aug 27 12:03:05 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175155804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.175155804
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.217089707
Short name	T68
Test name
Test status
Simulation time	27545348 ps
CPU time	0.46 seconds
Started	Aug 27 12:03:05 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217089707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.217089707
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3176030035
Short name	T71
Test name
Test status
Simulation time	27495023 ps
CPU time	0.46 seconds
Started	Aug 27 12:03:05 AM UTC 24
Finished	Aug 27 12:03:06 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176030035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3176030035
Directory	/workspaces/repo/scratch/os_regression_2024_08_26/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest