| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.92 | 88.92 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.1135440998 |
| 92.05 | 3.13 | 100.00 | 0.00 | 91.67 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3387114459 |
| 93.90 | 1.86 | 100.00 | 0.00 | 95.83 | 4.17 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.4035475311 |
| 94.50 | 0.60 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1178347252 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.2387775974 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3015664276 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.548166711 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2736023283 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.3889891453 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.248909202 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2872701522 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.3595394857 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.482159536 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.601046567 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2592155505 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.3519897898 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.313907636 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3531988079 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.383174734 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.2763059645 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2631932846 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1771513176 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.435051369 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.149698296 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1109527892 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.3059642032 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.2025265924 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.3518325808 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2805230933 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.325029321 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.81102568 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.198104085 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2020954106 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1511733591 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.205230754 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.338569205 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.3550397673 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1662743136 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2889807215 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.2221455357 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.880552752 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.4259730959 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1139017085 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3027479185 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.1114484719 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1014498311 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.1611370585 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.1820828963 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1637350468 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.57583873 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.772934573 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.1481791693 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.477809952 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.126529465 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2216689122 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.2129520439 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.1142291355 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1525438716 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.595183377 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.521701408 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3815293568 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4203975277 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1581097966 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3403027013 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3142226547 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2770902208 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3975447692 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.802470314 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3002454805 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.521668396 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1137254776 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3016187080 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.605092166 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1687833580 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1329222543 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2079128694 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1011942988 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3196766511 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.3519897898 | Aug 28 04:59:40 PM UTC 24 | Aug 28 04:59:42 PM UTC 24 | 11674176 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.2387775974 | Aug 28 04:59:40 PM UTC 24 | Aug 28 04:59:42 PM UTC 24 | 10545170 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.548166711 | Aug 28 04:59:40 PM UTC 24 | Aug 28 04:59:42 PM UTC 24 | 10562678 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.313907636 | Aug 28 04:59:40 PM UTC 24 | Aug 28 04:59:42 PM UTC 24 | 11145056 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3531988079 | Aug 28 04:59:40 PM UTC 24 | Aug 28 04:59:42 PM UTC 24 | 11115465 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.383174734 | Aug 28 04:59:40 PM UTC 24 | Aug 28 04:59:42 PM UTC 24 | 12040224 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.1135440998 | Aug 28 04:59:41 PM UTC 24 | Aug 28 04:59:42 PM UTC 24 | 12119605 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.2763059645 | Aug 28 04:59:41 PM UTC 24 | Aug 28 04:59:42 PM UTC 24 | 10686681 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1771513176 | Aug 28 04:59:42 PM UTC 24 | Aug 28 04:59:43 PM UTC 24 | 10662798 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2631932846 | Aug 28 04:59:42 PM UTC 24 | Aug 28 04:59:43 PM UTC 24 | 12038923 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.3889891453 | Aug 28 04:59:42 PM UTC 24 | Aug 28 04:59:43 PM UTC 24 | 11074021 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1178347252 | Aug 28 04:59:42 PM UTC 24 | Aug 28 04:59:43 PM UTC 24 | 12180750 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2736023283 | Aug 28 04:59:42 PM UTC 24 | Aug 28 04:59:43 PM UTC 24 | 10901760 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.248909202 | Aug 28 04:59:42 PM UTC 24 | Aug 28 04:59:43 PM UTC 24 | 10726137 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.3595394857 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 11617468 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.601046567 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 11033618 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.482159536 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 10929274 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2872701522 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 10806450 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2592155505 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 12664343 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.435051369 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 28517968 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1511733591 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 30233171 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.4035475311 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 30689927 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.3550397673 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 32142599 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1662743136 | Aug 28 04:59:44 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 29626692 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.205230754 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 28467583 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2889807215 | Aug 28 04:59:44 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 32598811 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.2221455357 | Aug 28 04:59:44 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 29604738 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.338569205 | Aug 28 04:59:43 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 30745557 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.149698296 | Aug 28 04:59:44 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 31301147 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.3059642032 | Aug 28 04:59:44 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 30098833 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1109527892 | Aug 28 04:59:44 PM UTC 24 | Aug 28 04:59:45 PM UTC 24 | 30905666 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.2025265924 | Aug 28 04:59:45 PM UTC 24 | Aug 28 04:59:46 PM UTC 24 | 29243986 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.3518325808 | Aug 28 04:59:45 PM UTC 24 | Aug 28 04:59:46 PM UTC 24 | 28529784 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.325029321 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:47 PM UTC 24 | 29903621 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2805230933 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:47 PM UTC 24 | 28756607 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2020954106 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:47 PM UTC 24 | 28562748 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.81102568 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:47 PM UTC 24 | 30287976 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.198104085 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 29485898 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3387114459 | Aug 28 05:14:32 PM UTC 24 | Aug 28 05:14:34 PM UTC 24 | 9085850 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.880552752 | Aug 28 05:14:32 PM UTC 24 | Aug 28 05:14:34 PM UTC 24 | 9341841 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.1481791693 | Aug 28 05:14:33 PM UTC 24 | Aug 28 05:14:35 PM UTC 24 | 8809458 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.477809952 | Aug 28 05:14:33 PM UTC 24 | Aug 28 05:14:35 PM UTC 24 | 9723433 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3015664276 | Aug 28 05:14:34 PM UTC 24 | Aug 28 05:14:36 PM UTC 24 | 9285168 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2216689122 | Aug 28 05:14:34 PM UTC 24 | Aug 28 05:14:36 PM UTC 24 | 8490865 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.126529465 | Aug 28 05:14:34 PM UTC 24 | Aug 28 05:14:36 PM UTC 24 | 9570747 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.2129520439 | Aug 28 05:14:35 PM UTC 24 | Aug 28 05:14:37 PM UTC 24 | 8926056 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1525438716 | Aug 28 05:14:36 PM UTC 24 | Aug 28 05:14:37 PM UTC 24 | 8619932 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.1142291355 | Aug 28 05:14:36 PM UTC 24 | Aug 28 05:14:37 PM UTC 24 | 9396961 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.4259730959 | Aug 28 05:14:37 PM UTC 24 | Aug 28 05:14:38 PM UTC 24 | 9279738 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3027479185 | Aug 28 05:14:37 PM UTC 24 | Aug 28 05:14:38 PM UTC 24 | 8550174 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1139017085 | Aug 28 05:14:37 PM UTC 24 | Aug 28 05:14:38 PM UTC 24 | 9887656 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.1114484719 | Aug 28 05:14:37 PM UTC 24 | Aug 28 05:14:38 PM UTC 24 | 8703042 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1014498311 | Aug 28 05:14:38 PM UTC 24 | Aug 28 05:14:39 PM UTC 24 | 9408759 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.1820828963 | Aug 28 05:14:38 PM UTC 24 | Aug 28 05:14:39 PM UTC 24 | 8835969 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.1611370585 | Aug 28 05:14:38 PM UTC 24 | Aug 28 05:14:39 PM UTC 24 | 9563995 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1637350468 | Aug 28 05:14:38 PM UTC 24 | Aug 28 05:14:39 PM UTC 24 | 9164475 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.57583873 | Aug 28 05:14:38 PM UTC 24 | Aug 28 05:14:39 PM UTC 24 | 8654643 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.772934573 | Aug 28 05:14:39 PM UTC 24 | Aug 28 05:14:40 PM UTC 24 | 8680271 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.521701408 | Aug 28 04:59:15 PM UTC 24 | Aug 28 04:59:17 PM UTC 24 | 27363580 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.595183377 | Aug 28 04:59:15 PM UTC 24 | Aug 28 04:59:17 PM UTC 24 | 27368553 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1137254776 | Aug 28 04:59:16 PM UTC 24 | Aug 28 04:59:17 PM UTC 24 | 28664843 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.605092166 | Aug 28 04:59:17 PM UTC 24 | Aug 28 04:59:18 PM UTC 24 | 27690979 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3016187080 | Aug 28 04:59:17 PM UTC 24 | Aug 28 04:59:18 PM UTC 24 | 28246439 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1687833580 | Aug 28 04:59:17 PM UTC 24 | Aug 28 04:59:18 PM UTC 24 | 26930416 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1329222543 | Aug 28 04:59:18 PM UTC 24 | Aug 28 04:59:20 PM UTC 24 | 27521274 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1011942988 | Aug 28 04:59:19 PM UTC 24 | Aug 28 04:59:20 PM UTC 24 | 26182175 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2079128694 | Aug 28 04:59:19 PM UTC 24 | Aug 28 04:59:20 PM UTC 24 | 25371530 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3196766511 | Aug 28 04:59:19 PM UTC 24 | Aug 28 04:59:21 PM UTC 24 | 27723946 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3815293568 | Aug 28 04:59:19 PM UTC 24 | Aug 28 04:59:21 PM UTC 24 | 29797596 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4203975277 | Aug 28 04:59:20 PM UTC 24 | Aug 28 04:59:22 PM UTC 24 | 28167508 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3403027013 | Aug 28 04:59:21 PM UTC 24 | Aug 28 04:59:23 PM UTC 24 | 26295719 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3142226547 | Aug 28 04:59:21 PM UTC 24 | Aug 28 04:59:23 PM UTC 24 | 28057660 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1581097966 | Aug 28 04:59:21 PM UTC 24 | Aug 28 04:59:23 PM UTC 24 | 27612346 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.802470314 | Aug 28 04:59:21 PM UTC 24 | Aug 28 04:59:23 PM UTC 24 | 27263538 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2770902208 | Aug 28 04:59:21 PM UTC 24 | Aug 28 04:59:23 PM UTC 24 | 29508851 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3975447692 | Aug 28 04:59:21 PM UTC 24 | Aug 28 04:59:23 PM UTC 24 | 28497635 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3002454805 | Aug 28 04:59:22 PM UTC 24 | Aug 28 04:59:24 PM UTC 24 | 28499382 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.521668396 | Aug 28 04:59:22 PM UTC 24 | Aug 28 04:59:24 PM UTC 24 | 27791367 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.1135440998 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12119605 ps |
| CPU time | 0.42 seconds |
| Started | Aug 28 04:59:41 PM UTC 24 |
| Finished | Aug 28 04:59:42 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135440998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.prim_async_alert.1135440998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/6.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3387114459 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9085850 ps |
| CPU time | 0.51 seconds |
| Started | Aug 28 05:14:32 PM UTC 24 |
| Finished | Aug 28 05:14:34 PM UTC 24 |
| Peak memory | 154616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387114459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.3387114459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/0.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.4035475311 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30689927 ps |
| CPU time | 0.42 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 154648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035475311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.4035475311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1178347252 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12180750 ps |
| CPU time | 0.48 seconds |
| Started | Aug 28 04:59:42 PM UTC 24 |
| Finished | Aug 28 04:59:43 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178347252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.prim_async_alert.1178347252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/13.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.2387775974 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10545170 ps |
| CPU time | 0.51 seconds |
| Started | Aug 28 04:59:40 PM UTC 24 |
| Finished | Aug 28 04:59:42 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387775974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.prim_async_alert.2387775974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/1.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3015664276 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9285168 ps |
| CPU time | 0.35 seconds |
| Started | Aug 28 05:14:34 PM UTC 24 |
| Finished | Aug 28 05:14:36 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015664276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 5.prim_sync_alert.3015664276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/5.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.548166711 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10562678 ps |
| CPU time | 0.58 seconds |
| Started | Aug 28 04:59:40 PM UTC 24 |
| Finished | Aug 28 04:59:42 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548166711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.prim_async_alert.548166711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/0.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2736023283 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10901760 ps |
| CPU time | 0.54 seconds |
| Started | Aug 28 04:59:42 PM UTC 24 |
| Finished | Aug 28 04:59:43 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736023283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 10.prim_async_alert.2736023283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/10.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.3889891453 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11074021 ps |
| CPU time | 0.45 seconds |
| Started | Aug 28 04:59:42 PM UTC 24 |
| Finished | Aug 28 04:59:43 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889891453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 11.prim_async_alert.3889891453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/11.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.248909202 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10726137 ps |
| CPU time | 0.52 seconds |
| Started | Aug 28 04:59:42 PM UTC 24 |
| Finished | Aug 28 04:59:43 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248909202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 12.prim_async_alert.248909202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/12.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2872701522 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10806450 ps |
| CPU time | 0.53 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872701522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.2872701522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/14.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.3595394857 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11617468 ps |
| CPU time | 0.48 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595394857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.3595394857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/15.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.482159536 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10929274 ps |
| CPU time | 0.44 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482159536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 16.prim_async_alert.482159536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/16.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.601046567 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11033618 ps |
| CPU time | 0.44 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601046567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 17.prim_async_alert.601046567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/17.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2592155505 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12664343 ps |
| CPU time | 0.47 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592155505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.prim_async_alert.2592155505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/18.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.3519897898 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11674176 ps |
| CPU time | 0.48 seconds |
| Started | Aug 28 04:59:40 PM UTC 24 |
| Finished | Aug 28 04:59:42 PM UTC 24 |
| Peak memory | 155224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519897898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.prim_async_alert.3519897898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/2.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.313907636 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11145056 ps |
| CPU time | 0.51 seconds |
| Started | Aug 28 04:59:40 PM UTC 24 |
| Finished | Aug 28 04:59:42 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313907636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 3.prim_async_alert.313907636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/3.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3531988079 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11115465 ps |
| CPU time | 0.53 seconds |
| Started | Aug 28 04:59:40 PM UTC 24 |
| Finished | Aug 28 04:59:42 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531988079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 4.prim_async_alert.3531988079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/4.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.383174734 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12040224 ps |
| CPU time | 0.46 seconds |
| Started | Aug 28 04:59:40 PM UTC 24 |
| Finished | Aug 28 04:59:42 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383174734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 5.prim_async_alert.383174734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/5.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.2763059645 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10686681 ps |
| CPU time | 0.53 seconds |
| Started | Aug 28 04:59:41 PM UTC 24 |
| Finished | Aug 28 04:59:42 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763059645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 7.prim_async_alert.2763059645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/7.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2631932846 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12038923 ps |
| CPU time | 0.48 seconds |
| Started | Aug 28 04:59:42 PM UTC 24 |
| Finished | Aug 28 04:59:43 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631932846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.prim_async_alert.2631932846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/8.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1771513176 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10662798 ps |
| CPU time | 0.52 seconds |
| Started | Aug 28 04:59:42 PM UTC 24 |
| Finished | Aug 28 04:59:43 PM UTC 24 |
| Peak memory | 155160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771513176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.1771513176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/9.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.435051369 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 28517968 ps |
| CPU time | 0.43 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 154716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435051369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 0.prim_async_fatal_alert.435051369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.149698296 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 31301147 ps |
| CPU time | 0.38 seconds |
| Started | Aug 28 04:59:44 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 154896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149698296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 10.prim_async_fatal_alert.149698296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1109527892 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30905666 ps |
| CPU time | 0.4 seconds |
| Started | Aug 28 04:59:44 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109527892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.1109527892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.3059642032 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 30098833 ps |
| CPU time | 0.47 seconds |
| Started | Aug 28 04:59:44 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059642032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 12.prim_async_fatal_alert.3059642032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.2025265924 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29243986 ps |
| CPU time | 0.39 seconds |
| Started | Aug 28 04:59:45 PM UTC 24 |
| Finished | Aug 28 04:59:46 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025265924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 13.prim_async_fatal_alert.2025265924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.3518325808 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 28529784 ps |
| CPU time | 0.43 seconds |
| Started | Aug 28 04:59:45 PM UTC 24 |
| Finished | Aug 28 04:59:46 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518325808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 14.prim_async_fatal_alert.3518325808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2805230933 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 28756607 ps |
| CPU time | 0.39 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:47 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805230933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.2805230933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.325029321 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29903621 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:47 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325029321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 16.prim_async_fatal_alert.325029321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.81102568 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30287976 ps |
| CPU time | 0.38 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:47 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81102568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 17.prim_async_fatal_alert.81102568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.198104085 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29485898 ps |
| CPU time | 0.48 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 154996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198104085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 18.prim_async_fatal_alert.198104085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2020954106 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 28562748 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:47 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020954106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 19.prim_async_fatal_alert.2020954106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1511733591 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30233171 ps |
| CPU time | 0.45 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511733591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.1511733591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.205230754 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 28467583 ps |
| CPU time | 0.5 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205230754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 3.prim_async_fatal_alert.205230754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.338569205 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 30745557 ps |
| CPU time | 0.5 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338569205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 4.prim_async_fatal_alert.338569205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.3550397673 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 32142599 ps |
| CPU time | 0.41 seconds |
| Started | Aug 28 04:59:43 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550397673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 6.prim_async_fatal_alert.3550397673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1662743136 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29626692 ps |
| CPU time | 0.39 seconds |
| Started | Aug 28 04:59:44 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662743136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 7.prim_async_fatal_alert.1662743136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2889807215 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 32598811 ps |
| CPU time | 0.43 seconds |
| Started | Aug 28 04:59:44 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889807215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 8.prim_async_fatal_alert.2889807215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.2221455357 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 29604738 ps |
| CPU time | 0.37 seconds |
| Started | Aug 28 04:59:44 PM UTC 24 |
| Finished | Aug 28 04:59:45 PM UTC 24 |
| Peak memory | 155020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221455357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 9.prim_async_fatal_alert.2221455357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.880552752 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9341841 ps |
| CPU time | 0.39 seconds |
| Started | Aug 28 05:14:32 PM UTC 24 |
| Finished | Aug 28 05:14:34 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880552752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 1.prim_sync_alert.880552752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/1.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.4259730959 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9279738 ps |
| CPU time | 0.32 seconds |
| Started | Aug 28 05:14:37 PM UTC 24 |
| Finished | Aug 28 05:14:38 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259730959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.4259730959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/10.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1139017085 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9887656 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 05:14:37 PM UTC 24 |
| Finished | Aug 28 05:14:38 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139017085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.1139017085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/11.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3027479185 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8550174 ps |
| CPU time | 0.35 seconds |
| Started | Aug 28 05:14:37 PM UTC 24 |
| Finished | Aug 28 05:14:38 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027479185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.3027479185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/12.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.1114484719 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8703042 ps |
| CPU time | 0.33 seconds |
| Started | Aug 28 05:14:37 PM UTC 24 |
| Finished | Aug 28 05:14:38 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114484719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 13.prim_sync_alert.1114484719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/13.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1014498311 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9408759 ps |
| CPU time | 0.33 seconds |
| Started | Aug 28 05:14:38 PM UTC 24 |
| Finished | Aug 28 05:14:39 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014498311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.1014498311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/14.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.1611370585 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9563995 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 05:14:38 PM UTC 24 |
| Finished | Aug 28 05:14:39 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611370585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.1611370585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/15.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.1820828963 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8835969 ps |
| CPU time | 0.32 seconds |
| Started | Aug 28 05:14:38 PM UTC 24 |
| Finished | Aug 28 05:14:39 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820828963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 16.prim_sync_alert.1820828963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/16.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1637350468 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9164475 ps |
| CPU time | 0.33 seconds |
| Started | Aug 28 05:14:38 PM UTC 24 |
| Finished | Aug 28 05:14:39 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637350468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 17.prim_sync_alert.1637350468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/17.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.57583873 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8654643 ps |
| CPU time | 0.32 seconds |
| Started | Aug 28 05:14:38 PM UTC 24 |
| Finished | Aug 28 05:14:39 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57583873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.57583873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/18.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.772934573 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8680271 ps |
| CPU time | 0.33 seconds |
| Started | Aug 28 05:14:39 PM UTC 24 |
| Finished | Aug 28 05:14:40 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772934573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 19.prim_sync_alert.772934573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/19.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.1481791693 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8809458 ps |
| CPU time | 0.32 seconds |
| Started | Aug 28 05:14:33 PM UTC 24 |
| Finished | Aug 28 05:14:35 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481791693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 2.prim_sync_alert.1481791693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/2.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.477809952 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9723433 ps |
| CPU time | 0.32 seconds |
| Started | Aug 28 05:14:33 PM UTC 24 |
| Finished | Aug 28 05:14:35 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477809952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 3.prim_sync_alert.477809952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/3.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.126529465 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9570747 ps |
| CPU time | 0.32 seconds |
| Started | Aug 28 05:14:34 PM UTC 24 |
| Finished | Aug 28 05:14:36 PM UTC 24 |
| Peak memory | 154548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126529465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 4.prim_sync_alert.126529465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/4.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2216689122 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8490865 ps |
| CPU time | 0.32 seconds |
| Started | Aug 28 05:14:34 PM UTC 24 |
| Finished | Aug 28 05:14:36 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216689122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 6.prim_sync_alert.2216689122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/6.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.2129520439 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8926056 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 05:14:35 PM UTC 24 |
| Finished | Aug 28 05:14:37 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129520439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.2129520439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/7.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.1142291355 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9396961 ps |
| CPU time | 0.32 seconds |
| Started | Aug 28 05:14:36 PM UTC 24 |
| Finished | Aug 28 05:14:37 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142291355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.1142291355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/8.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1525438716 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8619932 ps |
| CPU time | 0.32 seconds |
| Started | Aug 28 05:14:36 PM UTC 24 |
| Finished | Aug 28 05:14:37 PM UTC 24 |
| Peak memory | 154552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525438716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.1525438716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/9.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.595183377 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27368553 ps |
| CPU time | 0.56 seconds |
| Started | Aug 28 04:59:15 PM UTC 24 |
| Finished | Aug 28 04:59:17 PM UTC 24 |
| Peak memory | 154328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595183377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.595183377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.521701408 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 27363580 ps |
| CPU time | 0.41 seconds |
| Started | Aug 28 04:59:15 PM UTC 24 |
| Finished | Aug 28 04:59:17 PM UTC 24 |
| Peak memory | 154616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521701408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.521701408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3815293568 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 29797596 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 04:59:19 PM UTC 24 |
| Finished | Aug 28 04:59:21 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815293568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3815293568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4203975277 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28167508 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 04:59:20 PM UTC 24 |
| Finished | Aug 28 04:59:22 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203975277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4203975277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1581097966 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27612346 ps |
| CPU time | 0.38 seconds |
| Started | Aug 28 04:59:21 PM UTC 24 |
| Finished | Aug 28 04:59:23 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581097966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1581097966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3403027013 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26295719 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 04:59:21 PM UTC 24 |
| Finished | Aug 28 04:59:23 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403027013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3403027013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3142226547 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28057660 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 04:59:21 PM UTC 24 |
| Finished | Aug 28 04:59:23 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142226547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3142226547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2770902208 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 29508851 ps |
| CPU time | 0.38 seconds |
| Started | Aug 28 04:59:21 PM UTC 24 |
| Finished | Aug 28 04:59:23 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770902208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2770902208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3975447692 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28497635 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 04:59:21 PM UTC 24 |
| Finished | Aug 28 04:59:23 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975447692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3975447692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.802470314 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27263538 ps |
| CPU time | 0.37 seconds |
| Started | Aug 28 04:59:21 PM UTC 24 |
| Finished | Aug 28 04:59:23 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802470314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.802470314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3002454805 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 28499382 ps |
| CPU time | 0.38 seconds |
| Started | Aug 28 04:59:22 PM UTC 24 |
| Finished | Aug 28 04:59:24 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002454805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3002454805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.521668396 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 27791367 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 04:59:22 PM UTC 24 |
| Finished | Aug 28 04:59:24 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521668396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.521668396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1137254776 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 28664843 ps |
| CPU time | 0.33 seconds |
| Started | Aug 28 04:59:16 PM UTC 24 |
| Finished | Aug 28 04:59:17 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137254776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1137254776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3016187080 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28246439 ps |
| CPU time | 0.4 seconds |
| Started | Aug 28 04:59:17 PM UTC 24 |
| Finished | Aug 28 04:59:18 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016187080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3016187080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.605092166 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27690979 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 04:59:17 PM UTC 24 |
| Finished | Aug 28 04:59:18 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605092166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.605092166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1687833580 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26930416 ps |
| CPU time | 0.38 seconds |
| Started | Aug 28 04:59:17 PM UTC 24 |
| Finished | Aug 28 04:59:18 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687833580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1687833580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1329222543 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27521274 ps |
| CPU time | 0.37 seconds |
| Started | Aug 28 04:59:18 PM UTC 24 |
| Finished | Aug 28 04:59:20 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329222543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1329222543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2079128694 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 25371530 ps |
| CPU time | 0.33 seconds |
| Started | Aug 28 04:59:19 PM UTC 24 |
| Finished | Aug 28 04:59:20 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079128694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2079128694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1011942988 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26182175 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 04:59:19 PM UTC 24 |
| Finished | Aug 28 04:59:20 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011942988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1011942988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3196766511 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 27723946 ps |
| CPU time | 0.37 seconds |
| Started | Aug 28 04:59:19 PM UTC 24 |
| Finished | Aug 28 04:59:21 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196766511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3196766511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |