Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	100.00	100.00	89.29	95.83	86.05

Total tests in report: 79

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
89.72	89.72	100.00	100.00	91.67	91.67	100.00	100.00	85.71	85.71	95.83	95.83	65.12	65.12	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1926524375
92.25	2.53	100.00	0.00	91.67	0.00	100.00	0.00	89.29	3.57	95.83	0.00	76.74	11.63	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1955221598
93.81	1.55	100.00	0.00	91.67	0.00	100.00	0.00	89.29	0.00	95.83	0.00	86.05	9.30	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.984005956
94.50	0.69	100.00	0.00	95.83	4.17	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2675939526
94.85	0.35	100.00	0.00	97.92	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.4008967959
95.19	0.35	100.00	0.00	100.00	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2043199948

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.594466823
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3307825157
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.963408944
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.2447482405
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1201360092
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1251836924
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3868882505
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.271623599
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3416875429
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.745377839
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.1978207199
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2257261404
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.2906016763
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1489984294
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.406669770
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3604097946
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2463637851
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3192183644
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2164456510
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.2198261475
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.368465944
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.4093069955
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.4175201842
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.1385904598
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2895151463
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.12928410
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2020245789
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.990354391
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2515072166
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1453175820
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.187736078
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1775728965
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2010435051
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2248921219
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.667899115
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.200773685
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3876876913
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3828546866
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.2867712572
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2702024845
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2510088111
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2457298958
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.945681797
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1498411701
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.3954565465
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.312005341
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3788576985
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.3039679822
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2615624263
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.817949517
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.4087404742
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3192836688
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3025911833
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3895513939
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2768299257
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2457496068
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4008555265
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3075548568
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3515718636
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1037506472
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3830962166
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2522686159
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.209020119
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3772713648
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3396741389
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1522342640
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.518898856
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1540054967
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.536544237
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2238435501
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3886703261
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1798617782
/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.173061541

Total test records in report: 79

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2257261404	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:27 AM UTC 24	10664149 ps
T2	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3307825157	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:27 AM UTC 24	11717761 ps
T3	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.594466823	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:27 AM UTC 24	10675443 ps
T7	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.406669770	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:27 AM UTC 24	11536851 ps
T14	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1489984294	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:27 AM UTC 24	10879877 ps
T17	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.2906016763	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:27 AM UTC 24	10853573 ps
T13	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1926524375	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:27 AM UTC 24	11935248 ps
T8	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2463637851	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:27 AM UTC 24	11307457 ps
T9	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3604097946	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:27 AM UTC 24	11767285 ps
T15	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.2447482405	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:27 AM UTC 24	12754496 ps
T10	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3192183644	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:28 AM UTC 24	10887116 ps
T18	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.963408944	Sep 01 03:34:26 AM UTC 24	Sep 01 03:34:28 AM UTC 24	12024586 ps
T19	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1201360092	Sep 01 03:34:27 AM UTC 24	Sep 01 03:34:29 AM UTC 24	10994949 ps
T20	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1251836924	Sep 01 03:34:27 AM UTC 24	Sep 01 03:34:29 AM UTC 24	11103233 ps
T45	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3868882505	Sep 01 03:34:27 AM UTC 24	Sep 01 03:34:29 AM UTC 24	10357230 ps
T21	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2675939526	Sep 01 03:34:27 AM UTC 24	Sep 01 03:34:29 AM UTC 24	11105070 ps
T22	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3416875429	Sep 01 03:34:27 AM UTC 24	Sep 01 03:34:29 AM UTC 24	11605986 ps
T23	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.271623599	Sep 01 03:34:27 AM UTC 24	Sep 01 03:34:29 AM UTC 24	12024979 ps
T46	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.745377839	Sep 01 03:34:27 AM UTC 24	Sep 01 03:34:29 AM UTC 24	11003288 ps
T47	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.1978207199	Sep 01 03:34:27 AM UTC 24	Sep 01 03:34:29 AM UTC 24	11377771 ps
T24	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.984005956	Sep 01 03:34:27 AM UTC 24	Sep 01 03:34:29 AM UTC 24	30936187 ps
T38	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2164456510	Sep 01 03:34:28 AM UTC 24	Sep 01 03:34:29 AM UTC 24	29487949 ps
T39	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1453175820	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:30 AM UTC 24	28646385 ps
T40	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2515072166	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:30 AM UTC 24	29945916 ps
T41	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1775728965	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:30 AM UTC 24	31218772 ps
T42	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2010435051	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:30 AM UTC 24	28087362 ps
T43	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.187736078	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	28761501 ps
T44	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2248921219	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	29904329 ps
T4	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.667899115	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	29221619 ps
T5	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.4008967959	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	29050539 ps
T48	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.2198261475	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	29848864 ps
T49	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2895151463	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	31258998 ps
T50	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.4175201842	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	31724323 ps
T6	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.368465944	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	28026762 ps
T51	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.4093069955	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	31371935 ps
T52	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.1385904598	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	29306119 ps
T53	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.12928410	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	30016785 ps
T54	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2020245789	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	29928286 ps
T55	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.990354391	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	31524936 ps
T34	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.200773685	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	8443947 ps
T25	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3788576985	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	9599108 ps
T26	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2615624263	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	10628374 ps
T27	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.3039679822	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	9709615 ps
T35	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1955221598	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	9633094 ps
T36	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3192836688	Sep 01 03:34:30 AM UTC 24	Sep 01 03:34:31 AM UTC 24	9180360 ps
T28	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.4087404742	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	9312347 ps
T29	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.817949517	Sep 01 03:34:29 AM UTC 24	Sep 01 03:34:31 AM UTC 24	8996124 ps
T30	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3895513939	Sep 01 03:34:30 AM UTC 24	Sep 01 03:34:31 AM UTC 24	9312586 ps
T37	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3876876913	Sep 01 03:34:30 AM UTC 24	Sep 01 03:34:31 AM UTC 24	8935366 ps
T56	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3025911833	Sep 01 03:34:30 AM UTC 24	Sep 01 03:34:31 AM UTC 24	8181653 ps
T57	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3828546866	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:32 AM UTC 24	9807563 ps
T31	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2702024845	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:32 AM UTC 24	9375605 ps
T58	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2457298958	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:32 AM UTC 24	9480224 ps
T16	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1498411701	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:32 AM UTC 24	10978421 ps
T32	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.2867712572	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:32 AM UTC 24	7884451 ps
T33	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.945681797	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:32 AM UTC 24	8641400 ps
T59	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2510088111	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:32 AM UTC 24	10220346 ps
T60	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.3954565465	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	9500580 ps
T61	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.312005341	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	8346673 ps
T62	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2768299257	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	25494579 ps
T63	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1522342640	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	27389045 ps
T64	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2457496068	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	25617473 ps
T65	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1798617782	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	27373052 ps
T66	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.518898856	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	28116731 ps
T67	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1540054967	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	27496708 ps
T68	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2238435501	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	28747504 ps
T69	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.536544237	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	27395253 ps
T70	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3886703261	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	26964034 ps
T11	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.173061541	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	27763310 ps
T71	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4008555265	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	27682769 ps
T72	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3075548568	Sep 01 03:34:31 AM UTC 24	Sep 01 03:34:33 AM UTC 24	27722340 ps
T73	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1037506472	Sep 01 03:34:33 AM UTC 24	Sep 01 03:34:34 AM UTC 24	28829985 ps
T74	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3515718636	Sep 01 03:34:33 AM UTC 24	Sep 01 03:34:34 AM UTC 24	28162827 ps
T75	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3830962166	Sep 01 03:34:33 AM UTC 24	Sep 01 03:34:34 AM UTC 24	29136290 ps
T76	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.209020119	Sep 01 03:34:33 AM UTC 24	Sep 01 03:34:34 AM UTC 24	27561368 ps
T77	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2522686159	Sep 01 03:34:33 AM UTC 24	Sep 01 03:34:34 AM UTC 24	27374305 ps
T12	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2043199948	Sep 01 03:34:33 AM UTC 24	Sep 01 03:34:34 AM UTC 24	28529760 ps
T78	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3772713648	Sep 01 03:34:33 AM UTC 24	Sep 01 03:34:34 AM UTC 24	30207045 ps
T79	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3396741389	Sep 01 03:34:33 AM UTC 24	Sep 01 03:34:34 AM UTC 24	26737705 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1926524375
Short name	T13
Test name
Test status
Simulation time	11935248 ps
CPU time	0.49 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:27 AM UTC 24
Peak memory	154892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926524375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 7.prim_async_alert.1926524375
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/7.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1955221598
Short name	T35
Test name
Test status
Simulation time	9633094 ps
CPU time	0.45 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955221598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.1955221598
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/0.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.984005956
Short name	T24
Test name
Test status
Simulation time	30936187 ps
CPU time	0.5 seconds
Started	Sep 01 03:34:27 AM UTC 24
Finished	Sep 01 03:34:29 AM UTC 24
Peak memory	155084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984005956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 0.prim_async_fatal_alert.984005956
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2675939526
Short name	T21
Test name
Test status
Simulation time	11105070 ps
CPU time	0.51 seconds
Started	Sep 01 03:34:27 AM UTC 24
Finished	Sep 01 03:34:29 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675939526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.2675939526
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/15.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.4008967959
Short name	T5
Test name
Test status
Simulation time	29050539 ps
CPU time	0.43 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008967959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.4008967959
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2043199948
Short name	T12
Test name
Test status
Simulation time	28529760 ps
CPU time	0.38 seconds
Started	Sep 01 03:34:33 AM UTC 24
Finished	Sep 01 03:34:34 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043199948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2043199948
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.594466823
Short name	T3
Test name
Test status
Simulation time	10675443 ps
CPU time	0.54 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:27 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594466823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.prim_async_alert.594466823
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/0.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3307825157
Short name	T2
Test name
Test status
Simulation time	11717761 ps
CPU time	0.51 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:27 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307825157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.prim_async_alert.3307825157
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/1.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.963408944
Short name	T18
Test name
Test status
Simulation time	12024586 ps
CPU time	0.47 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:28 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963408944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 10.prim_async_alert.963408944
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/10.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.2447482405
Short name	T15
Test name
Test status
Simulation time	12754496 ps
CPU time	0.42 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:27 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447482405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 11.prim_async_alert.2447482405
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/11.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1201360092
Short name	T19
Test name
Test status
Simulation time	10994949 ps
CPU time	0.47 seconds
Started	Sep 01 03:34:27 AM UTC 24
Finished	Sep 01 03:34:29 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201360092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 12.prim_async_alert.1201360092
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/12.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1251836924
Short name	T20
Test name
Test status
Simulation time	11103233 ps
CPU time	0.51 seconds
Started	Sep 01 03:34:27 AM UTC 24
Finished	Sep 01 03:34:29 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251836924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.prim_async_alert.1251836924
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/13.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3868882505
Short name	T45
Test name
Test status
Simulation time	10357230 ps
CPU time	0.55 seconds
Started	Sep 01 03:34:27 AM UTC 24
Finished	Sep 01 03:34:29 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868882505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.3868882505
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/14.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.271623599
Short name	T23
Test name
Test status
Simulation time	12024979 ps
CPU time	0.5 seconds
Started	Sep 01 03:34:27 AM UTC 24
Finished	Sep 01 03:34:29 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271623599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 16.prim_async_alert.271623599
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/16.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3416875429
Short name	T22
Test name
Test status
Simulation time	11605986 ps
CPU time	0.49 seconds
Started	Sep 01 03:34:27 AM UTC 24
Finished	Sep 01 03:34:29 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416875429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.3416875429
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/17.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.745377839
Short name	T46
Test name
Test status
Simulation time	11003288 ps
CPU time	0.45 seconds
Started	Sep 01 03:34:27 AM UTC 24
Finished	Sep 01 03:34:29 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745377839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 18.prim_async_alert.745377839
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/18.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.1978207199
Short name	T47
Test name
Test status
Simulation time	11377771 ps
CPU time	0.45 seconds
Started	Sep 01 03:34:27 AM UTC 24
Finished	Sep 01 03:34:29 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978207199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 19.prim_async_alert.1978207199
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/19.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2257261404
Short name	T1
Test name
Test status
Simulation time	10664149 ps
CPU time	0.48 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:27 AM UTC 24
Peak memory	155224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257261404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.prim_async_alert.2257261404
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/2.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.2906016763
Short name	T17
Test name
Test status
Simulation time	10853573 ps
CPU time	0.53 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:27 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906016763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 3.prim_async_alert.2906016763
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/3.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1489984294
Short name	T14
Test name
Test status
Simulation time	10879877 ps
CPU time	0.46 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:27 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489984294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 4.prim_async_alert.1489984294
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/4.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.406669770
Short name	T7
Test name
Test status
Simulation time	11536851 ps
CPU time	0.44 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:27 AM UTC 24
Peak memory	155016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406669770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 5.prim_async_alert.406669770
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/5.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3604097946
Short name	T9
Test name
Test status
Simulation time	11767285 ps
CPU time	0.5 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:27 AM UTC 24
Peak memory	154732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604097946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.prim_async_alert.3604097946
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/6.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2463637851
Short name	T8
Test name
Test status
Simulation time	11307457 ps
CPU time	0.47 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:27 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463637851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.prim_async_alert.2463637851
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/8.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3192183644
Short name	T10
Test name
Test status
Simulation time	10887116 ps
CPU time	0.47 seconds
Started	Sep 01 03:34:26 AM UTC 24
Finished	Sep 01 03:34:28 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192183644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.3192183644
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/9.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2164456510
Short name	T38
Test name
Test status
Simulation time	29487949 ps
CPU time	0.45 seconds
Started	Sep 01 03:34:28 AM UTC 24
Finished	Sep 01 03:34:29 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164456510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.2164456510
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.2198261475
Short name	T48
Test name
Test status
Simulation time	29848864 ps
CPU time	0.41 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198261475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.2198261475
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.368465944
Short name	T6
Test name
Test status
Simulation time	28026762 ps
CPU time	0.41 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368465944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 12.prim_async_fatal_alert.368465944
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.4093069955
Short name	T51
Test name
Test status
Simulation time	31371935 ps
CPU time	0.4 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093069955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 13.prim_async_fatal_alert.4093069955
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.4175201842
Short name	T50
Test name
Test status
Simulation time	31724323 ps
CPU time	0.39 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175201842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 14.prim_async_fatal_alert.4175201842
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.1385904598
Short name	T52
Test name
Test status
Simulation time	29306119 ps
CPU time	0.42 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385904598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.1385904598
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2895151463
Short name	T49
Test name
Test status
Simulation time	31258998 ps
CPU time	0.38 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895151463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 16.prim_async_fatal_alert.2895151463
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.12928410
Short name	T53
Test name
Test status
Simulation time	30016785 ps
CPU time	0.4 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12928410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 17.prim_async_fatal_alert.12928410
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2020245789
Short name	T54
Test name
Test status
Simulation time	29928286 ps
CPU time	0.38 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020245789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 18.prim_async_fatal_alert.2020245789
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.990354391
Short name	T55
Test name
Test status
Simulation time	31524936 ps
CPU time	0.42 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990354391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 19.prim_async_fatal_alert.990354391
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2515072166
Short name	T40
Test name
Test status
Simulation time	29945916 ps
CPU time	0.43 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:30 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515072166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.2515072166
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1453175820
Short name	T39
Test name
Test status
Simulation time	28646385 ps
CPU time	0.39 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:30 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453175820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 3.prim_async_fatal_alert.1453175820
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.187736078
Short name	T43
Test name
Test status
Simulation time	28761501 ps
CPU time	0.49 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187736078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 4.prim_async_fatal_alert.187736078
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1775728965
Short name	T41
Test name
Test status
Simulation time	31218772 ps
CPU time	0.42 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:30 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775728965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 5.prim_async_fatal_alert.1775728965
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2010435051
Short name	T42
Test name
Test status
Simulation time	28087362 ps
CPU time	0.41 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:30 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010435051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 6.prim_async_fatal_alert.2010435051
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2248921219
Short name	T44
Test name
Test status
Simulation time	29904329 ps
CPU time	0.42 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248921219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 8.prim_async_fatal_alert.2248921219
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.667899115
Short name	T4
Test name
Test status
Simulation time	29221619 ps
CPU time	0.44 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667899115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 9.prim_async_fatal_alert.667899115
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.200773685
Short name	T34
Test name
Test status
Simulation time	8443947 ps
CPU time	0.39 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200773685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 1.prim_sync_alert.200773685
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/1.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3876876913
Short name	T37
Test name
Test status
Simulation time	8935366 ps
CPU time	0.38 seconds
Started	Sep 01 03:34:30 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876876913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.3876876913
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/10.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3828546866
Short name	T57
Test name
Test status
Simulation time	9807563 ps
CPU time	0.44 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:32 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828546866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.3828546866
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/11.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.2867712572
Short name	T32
Test name
Test status
Simulation time	7884451 ps
CPU time	0.39 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:32 AM UTC 24
Peak memory	154544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867712572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.2867712572
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/12.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2702024845
Short name	T31
Test name
Test status
Simulation time	9375605 ps
CPU time	0.38 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:32 AM UTC 24
Peak memory	154544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702024845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 13.prim_sync_alert.2702024845
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/13.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2510088111
Short name	T59
Test name
Test status
Simulation time	10220346 ps
CPU time	0.4 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:32 AM UTC 24
Peak memory	154544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510088111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.2510088111
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/14.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2457298958
Short name	T58
Test name
Test status
Simulation time	9480224 ps
CPU time	0.44 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:32 AM UTC 24
Peak memory	154384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457298958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.2457298958
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/15.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.945681797
Short name	T33
Test name
Test status
Simulation time	8641400 ps
CPU time	0.41 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:32 AM UTC 24
Peak memory	154552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945681797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 16.prim_sync_alert.945681797
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/16.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1498411701
Short name	T16
Test name
Test status
Simulation time	10978421 ps
CPU time	0.36 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:32 AM UTC 24
Peak memory	154544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498411701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 17.prim_sync_alert.1498411701
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/17.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.3954565465
Short name	T60
Test name
Test status
Simulation time	9500580 ps
CPU time	0.37 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954565465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 18.prim_sync_alert.3954565465
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/18.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.312005341
Short name	T61
Test name
Test status
Simulation time	8346673 ps
CPU time	0.41 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312005341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 19.prim_sync_alert.312005341
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/19.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3788576985
Short name	T25
Test name
Test status
Simulation time	9599108 ps
CPU time	0.39 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788576985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 2.prim_sync_alert.3788576985
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/2.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.3039679822
Short name	T27
Test name
Test status
Simulation time	9709615 ps
CPU time	0.39 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039679822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 3.prim_sync_alert.3039679822
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/3.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2615624263
Short name	T26
Test name
Test status
Simulation time	10628374 ps
CPU time	0.37 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615624263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.2615624263
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/4.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.817949517
Short name	T29
Test name
Test status
Simulation time	8996124 ps
CPU time	0.38 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817949517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 5.prim_sync_alert.817949517
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/5.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.4087404742
Short name	T28
Test name
Test status
Simulation time	9312347 ps
CPU time	0.46 seconds
Started	Sep 01 03:34:29 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087404742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 6.prim_sync_alert.4087404742
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/6.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3192836688
Short name	T36
Test name
Test status
Simulation time	9180360 ps
CPU time	0.38 seconds
Started	Sep 01 03:34:30 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192836688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.3192836688
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/7.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3025911833
Short name	T56
Test name
Test status
Simulation time	8181653 ps
CPU time	0.43 seconds
Started	Sep 01 03:34:30 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025911833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.3025911833
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/8.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3895513939
Short name	T30
Test name
Test status
Simulation time	9312586 ps
CPU time	0.39 seconds
Started	Sep 01 03:34:30 AM UTC 24
Finished	Sep 01 03:34:31 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895513939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.3895513939
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/9.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2768299257
Short name	T62
Test name
Test status
Simulation time	25494579 ps
CPU time	0.42 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768299257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2768299257
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2457496068
Short name	T64
Test name
Test status
Simulation time	25617473 ps
CPU time	0.43 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457496068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2457496068
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4008555265
Short name	T71
Test name
Test status
Simulation time	27682769 ps
CPU time	0.36 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008555265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.4008555265
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3075548568
Short name	T72
Test name
Test status
Simulation time	27722340 ps
CPU time	0.37 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075548568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3075548568
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3515718636
Short name	T74
Test name
Test status
Simulation time	28162827 ps
CPU time	0.44 seconds
Started	Sep 01 03:34:33 AM UTC 24
Finished	Sep 01 03:34:34 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515718636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3515718636
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1037506472
Short name	T73
Test name
Test status
Simulation time	28829985 ps
CPU time	0.4 seconds
Started	Sep 01 03:34:33 AM UTC 24
Finished	Sep 01 03:34:34 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037506472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1037506472
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3830962166
Short name	T75
Test name
Test status
Simulation time	29136290 ps
CPU time	0.4 seconds
Started	Sep 01 03:34:33 AM UTC 24
Finished	Sep 01 03:34:34 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830962166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3830962166
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2522686159
Short name	T77
Test name
Test status
Simulation time	27374305 ps
CPU time	0.4 seconds
Started	Sep 01 03:34:33 AM UTC 24
Finished	Sep 01 03:34:34 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522686159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2522686159
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.209020119
Short name	T76
Test name
Test status
Simulation time	27561368 ps
CPU time	0.41 seconds
Started	Sep 01 03:34:33 AM UTC 24
Finished	Sep 01 03:34:34 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209020119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.209020119
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3772713648
Short name	T78
Test name
Test status
Simulation time	30207045 ps
CPU time	0.38 seconds
Started	Sep 01 03:34:33 AM UTC 24
Finished	Sep 01 03:34:34 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772713648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3772713648
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3396741389
Short name	T79
Test name
Test status
Simulation time	26737705 ps
CPU time	0.41 seconds
Started	Sep 01 03:34:33 AM UTC 24
Finished	Sep 01 03:34:34 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396741389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3396741389
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1522342640
Short name	T63
Test name
Test status
Simulation time	27389045 ps
CPU time	0.38 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522342640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1522342640
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.518898856
Short name	T66
Test name
Test status
Simulation time	28116731 ps
CPU time	0.42 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518898856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.518898856
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1540054967
Short name	T67
Test name
Test status
Simulation time	27496708 ps
CPU time	0.39 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540054967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1540054967
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.536544237
Short name	T69
Test name
Test status
Simulation time	27395253 ps
CPU time	0.43 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536544237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.536544237
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2238435501
Short name	T68
Test name
Test status
Simulation time	28747504 ps
CPU time	0.41 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238435501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2238435501
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3886703261
Short name	T70
Test name
Test status
Simulation time	26964034 ps
CPU time	0.42 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886703261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3886703261
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1798617782
Short name	T65
Test name
Test status
Simulation time	27373052 ps
CPU time	0.38 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798617782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1798617782
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.173061541
Short name	T11
Test name
Test status
Simulation time	27763310 ps
CPU time	0.4 seconds
Started	Sep 01 03:34:31 AM UTC 24
Finished	Sep 01 03:34:33 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173061541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.173061541
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest