Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	100.00	100.00	89.29	95.83	86.05

Total tests in report: 80

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
88.42	88.42	100.00	100.00	95.83	95.83	96.43	96.43	75.00	75.00	95.83	95.83	67.44	67.44	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.743185126
92.15	3.72	100.00	0.00	95.83	0.00	96.43	0.00	85.71	10.71	95.83	0.00	79.07	11.63	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1532680317
93.90	1.76	100.00	0.00	95.83	0.00	100.00	3.57	85.71	0.00	95.83	0.00	86.05	6.98	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.354753650
94.50	0.60	100.00	0.00	95.83	0.00	100.00	0.00	89.29	3.57	95.83	0.00	86.05	0.00	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.4240638500
94.85	0.35	100.00	0.00	97.92	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.83962208
95.19	0.35	100.00	0.00	100.00	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3759939750

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.657886390
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.446210082
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.284953497
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1384448565
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.71132211
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.3555649309
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.3608360447
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.1783810350
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1628903586
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.637157172
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.1010028720
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.865017674
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.3873195243
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.3876695485
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.963872063
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1792883711
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.102914710
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1412604727
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.4198576948
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3539849713
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1463343183
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.1836992830
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.947426718
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.924460085
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.1203114915
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2215035947
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.1902776239
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.107357753
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.1142529907
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3589335102
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2882717090
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.928238701
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.3112509966
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.1442423517
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.96702502
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3617069306
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3657592856
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2258858647
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3569299060
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3666455853
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.4049541634
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1081583500
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2438179658
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.746836924
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3092726008
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.1387405911
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.673570252
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.4046437839
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2773384617
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2814147303
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.468226824
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2115729145
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.4102422312
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3830119246
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1890125269
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.326809813
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.440555110
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2463515639
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1895849713
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1441185700
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2929135496
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.942289622
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.30432579
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3939384330
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1157414168
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3632819158
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3317303561
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1064436190
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3281515663
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2382427905
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4109647990
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.458786891
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.743518849
/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4057373269

Total test records in report: 80

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.657886390	Sep 03 09:00:09 PM UTC 24	Sep 03 09:00:10 PM UTC 24	10853949 ps
T2	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.446210082	Sep 03 09:00:09 PM UTC 24	Sep 03 09:00:10 PM UTC 24	11854760 ps
T3	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.865017674	Sep 03 09:00:11 PM UTC 24	Sep 03 09:00:12 PM UTC 24	11558037 ps
T13	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.3873195243	Sep 03 09:00:11 PM UTC 24	Sep 03 09:00:12 PM UTC 24	10801026 ps
T7	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.743185126	Sep 03 09:00:13 PM UTC 24	Sep 03 09:00:14 PM UTC 24	12044882 ps
T11	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.3876695485	Sep 03 09:00:13 PM UTC 24	Sep 03 09:00:14 PM UTC 24	12358178 ps
T20	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.963872063	Sep 03 09:00:14 PM UTC 24	Sep 03 09:00:15 PM UTC 24	11029387 ps
T8	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1792883711	Sep 03 09:00:14 PM UTC 24	Sep 03 09:00:15 PM UTC 24	11525075 ps
T12	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.102914710	Sep 03 09:00:15 PM UTC 24	Sep 03 09:00:16 PM UTC 24	11914145 ps
T22	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1412604727	Sep 03 09:00:15 PM UTC 24	Sep 03 09:00:17 PM UTC 24	12403418 ps
T23	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1384448565	Sep 03 09:00:16 PM UTC 24	Sep 03 09:00:18 PM UTC 24	10677883 ps
T24	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.284953497	Sep 03 09:00:16 PM UTC 24	Sep 03 09:00:18 PM UTC 24	11162802 ps
T47	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.3555649309	Sep 03 09:00:17 PM UTC 24	Sep 03 09:00:19 PM UTC 24	11741225 ps
T25	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.71132211	Sep 03 09:00:17 PM UTC 24	Sep 03 09:00:19 PM UTC 24	11763647 ps
T48	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1628903586	Sep 03 09:00:18 PM UTC 24	Sep 03 09:00:20 PM UTC 24	11043603 ps
T17	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.1783810350	Sep 03 09:00:18 PM UTC 24	Sep 03 09:00:20 PM UTC 24	11353845 ps
T14	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.3608360447	Sep 03 09:00:18 PM UTC 24	Sep 03 09:00:20 PM UTC 24	11426134 ps
T15	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.4240638500	Sep 03 09:00:18 PM UTC 24	Sep 03 09:00:20 PM UTC 24	11964907 ps
T26	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.637157172	Sep 03 09:00:20 PM UTC 24	Sep 03 09:00:21 PM UTC 24	10529615 ps
T21	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.1010028720	Sep 03 09:00:20 PM UTC 24	Sep 03 09:00:21 PM UTC 24	10888467 ps
T39	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.354753650	Sep 03 09:00:20 PM UTC 24	Sep 03 09:00:21 PM UTC 24	30717509 ps
T40	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.4198576948	Sep 03 09:00:20 PM UTC 24	Sep 03 09:00:21 PM UTC 24	30127442 ps
T18	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.928238701	Sep 03 09:00:20 PM UTC 24	Sep 03 09:00:21 PM UTC 24	29584493 ps
T41	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3589335102	Sep 03 09:00:20 PM UTC 24	Sep 03 09:00:21 PM UTC 24	30000687 ps
T42	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2882717090	Sep 03 09:00:20 PM UTC 24	Sep 03 09:00:21 PM UTC 24	31064233 ps
T43	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.3112509966	Sep 03 09:00:20 PM UTC 24	Sep 03 09:00:21 PM UTC 24	28335153 ps
T44	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.1442423517	Sep 03 09:00:20 PM UTC 24	Sep 03 09:00:21 PM UTC 24	29486348 ps
T38	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.96702502	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:22 PM UTC 24	29566359 ps
T45	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3617069306	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	30678034 ps
T46	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.1836992830	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	29901252 ps
T4	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.83962208	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	29435613 ps
T49	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3539849713	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	30608542 ps
T19	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.924460085	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	29098261 ps
T50	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.1203114915	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	29803597 ps
T51	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1463343183	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	28951410 ps
T52	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.947426718	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	32558617 ps
T53	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2215035947	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	30753903 ps
T54	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.1902776239	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	31081867 ps
T55	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.1142529907	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	30822953 ps
T56	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.107357753	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	28780837 ps
T16	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.4046437839	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	9000796 ps
T35	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3657592856	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	8422113 ps
T27	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2814147303	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	10227178 ps
T36	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2258858647	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	9530585 ps
T28	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.468226824	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	9001814 ps
T29	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2773384617	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	9592765 ps
T9	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3759939750	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	9701141 ps
T30	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2115729145	Sep 03 09:00:21 PM UTC 24	Sep 03 09:00:23 PM UTC 24	9204248 ps
T37	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.4102422312	Sep 03 09:00:22 PM UTC 24	Sep 03 09:00:23 PM UTC 24	8497684 ps
T31	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1532680317	Sep 03 09:00:23 PM UTC 24	Sep 03 09:00:25 PM UTC 24	9247150 ps
T32	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3666455853	Sep 03 09:00:23 PM UTC 24	Sep 03 09:00:25 PM UTC 24	8447817 ps
T33	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3830119246	Sep 03 09:00:23 PM UTC 24	Sep 03 09:00:25 PM UTC 24	9273902 ps
T34	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3569299060	Sep 03 09:00:23 PM UTC 24	Sep 03 09:00:25 PM UTC 24	11059278 ps
T57	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.4049541634	Sep 03 09:00:23 PM UTC 24	Sep 03 09:00:25 PM UTC 24	8730772 ps
T58	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1081583500	Sep 03 09:00:23 PM UTC 24	Sep 03 09:00:25 PM UTC 24	10201318 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.746836924	Sep 03 09:00:23 PM UTC 24	Sep 03 09:00:25 PM UTC 24	8417900 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2438179658	Sep 03 09:00:23 PM UTC 24	Sep 03 09:00:25 PM UTC 24	9970700 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3092726008	Sep 03 09:00:23 PM UTC 24	Sep 03 09:00:25 PM UTC 24	10569657 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.1387405911	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	9214272 ps
T63	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.673570252	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	9349468 ps
T64	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1064436190	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	25745295 ps
T65	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4109647990	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	26804327 ps
T66	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2382427905	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	27649048 ps
T67	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3281515663	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	28948325 ps
T68	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.458786891	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	25690797 ps
T10	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.326809813	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	26449961 ps
T69	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3317303561	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	26333675 ps
T70	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1890125269	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	28164349 ps
T71	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2463515639	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	27274735 ps
T72	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4057373269	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	26722774 ps
T73	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.743518849	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	27797588 ps
T5	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.440555110	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	30241351 ps
T6	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.942289622	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	28815080 ps
T74	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3939384330	Sep 03 09:00:25 PM UTC 24	Sep 03 09:00:26 PM UTC 24	29981193 ps
T75	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1895849713	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	27012067 ps
T76	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.30432579	Sep 03 09:00:25 PM UTC 24	Sep 03 09:00:26 PM UTC 24	28458831 ps
T77	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1441185700	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	26675123 ps
T78	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2929135496	Sep 03 09:00:24 PM UTC 24	Sep 03 09:00:26 PM UTC 24	27760158 ps
T79	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1157414168	Sep 03 09:00:25 PM UTC 24	Sep 03 09:00:26 PM UTC 24	27733540 ps
T80	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3632819158	Sep 03 09:00:25 PM UTC 24	Sep 03 09:00:26 PM UTC 24	28934381 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.743185126
Short name	T7
Test name
Test status
Simulation time	12044882 ps
CPU time	0.33 seconds
Started	Sep 03 09:00:13 PM UTC 24
Finished	Sep 03 09:00:14 PM UTC 24
Peak memory	155156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743185126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 4.prim_async_alert.743185126
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/4.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1532680317
Short name	T31
Test name
Test status
Simulation time	9247150 ps
CPU time	0.33 seconds
Started	Sep 03 09:00:23 PM UTC 24
Finished	Sep 03 09:00:25 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532680317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.1532680317
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/10.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.354753650
Short name	T39
Test name
Test status
Simulation time	30717509 ps
CPU time	0.36 seconds
Started	Sep 03 09:00:20 PM UTC 24
Finished	Sep 03 09:00:21 PM UTC 24
Peak memory	155084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354753650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 0.prim_async_fatal_alert.354753650
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.4240638500
Short name	T15
Test name
Test status
Simulation time	11964907 ps
CPU time	0.42 seconds
Started	Sep 03 09:00:18 PM UTC 24
Finished	Sep 03 09:00:20 PM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240638500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.4240638500
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/14.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.83962208
Short name	T4
Test name
Test status
Simulation time	29435613 ps
CPU time	0.41 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	155024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83962208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 9.prim_async_fatal_alert.83962208
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3759939750
Short name	T9
Test name
Test status
Simulation time	9701141 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759939750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.3759939750
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/7.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.657886390
Short name	T1
Test name
Test status
Simulation time	10853949 ps
CPU time	0.51 seconds
Started	Sep 03 09:00:09 PM UTC 24
Finished	Sep 03 09:00:10 PM UTC 24
Peak memory	155228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657886390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.prim_async_alert.657886390
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/0.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.446210082
Short name	T2
Test name
Test status
Simulation time	11854760 ps
CPU time	0.41 seconds
Started	Sep 03 09:00:09 PM UTC 24
Finished	Sep 03 09:00:10 PM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446210082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.prim_async_alert.446210082
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/1.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.284953497
Short name	T24
Test name
Test status
Simulation time	11162802 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:16 PM UTC 24
Finished	Sep 03 09:00:18 PM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284953497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 10.prim_async_alert.284953497
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/10.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1384448565
Short name	T23
Test name
Test status
Simulation time	10677883 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:16 PM UTC 24
Finished	Sep 03 09:00:18 PM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384448565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 11.prim_async_alert.1384448565
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/11.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.71132211
Short name	T25
Test name
Test status
Simulation time	11763647 ps
CPU time	0.34 seconds
Started	Sep 03 09:00:17 PM UTC 24
Finished	Sep 03 09:00:19 PM UTC 24
Peak memory	155168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71132211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 12.prim_async_alert.71132211
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/12.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.3555649309
Short name	T47
Test name
Test status
Simulation time	11741225 ps
CPU time	0.33 seconds
Started	Sep 03 09:00:17 PM UTC 24
Finished	Sep 03 09:00:19 PM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555649309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.prim_async_alert.3555649309
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/13.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.3608360447
Short name	T14
Test name
Test status
Simulation time	11426134 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:18 PM UTC 24
Finished	Sep 03 09:00:20 PM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608360447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.3608360447
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/15.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.1783810350
Short name	T17
Test name
Test status
Simulation time	11353845 ps
CPU time	0.34 seconds
Started	Sep 03 09:00:18 PM UTC 24
Finished	Sep 03 09:00:20 PM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783810350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 16.prim_async_alert.1783810350
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/16.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1628903586
Short name	T48
Test name
Test status
Simulation time	11043603 ps
CPU time	0.33 seconds
Started	Sep 03 09:00:18 PM UTC 24
Finished	Sep 03 09:00:20 PM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628903586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.1628903586
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/17.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.637157172
Short name	T26
Test name
Test status
Simulation time	10529615 ps
CPU time	0.42 seconds
Started	Sep 03 09:00:20 PM UTC 24
Finished	Sep 03 09:00:21 PM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637157172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 18.prim_async_alert.637157172
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/18.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.1010028720
Short name	T21
Test name
Test status
Simulation time	10888467 ps
CPU time	0.4 seconds
Started	Sep 03 09:00:20 PM UTC 24
Finished	Sep 03 09:00:21 PM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010028720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 19.prim_async_alert.1010028720
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/19.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.865017674
Short name	T3
Test name
Test status
Simulation time	11558037 ps
CPU time	0.32 seconds
Started	Sep 03 09:00:11 PM UTC 24
Finished	Sep 03 09:00:12 PM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865017674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.prim_async_alert.865017674
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/2.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.3873195243
Short name	T13
Test name
Test status
Simulation time	10801026 ps
CPU time	0.32 seconds
Started	Sep 03 09:00:11 PM UTC 24
Finished	Sep 03 09:00:12 PM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873195243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 3.prim_async_alert.3873195243
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/3.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.3876695485
Short name	T11
Test name
Test status
Simulation time	12358178 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:13 PM UTC 24
Finished	Sep 03 09:00:14 PM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876695485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 5.prim_async_alert.3876695485
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/5.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.963872063
Short name	T20
Test name
Test status
Simulation time	11029387 ps
CPU time	0.32 seconds
Started	Sep 03 09:00:14 PM UTC 24
Finished	Sep 03 09:00:15 PM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963872063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 6.prim_async_alert.963872063
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/6.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1792883711
Short name	T8
Test name
Test status
Simulation time	11525075 ps
CPU time	0.33 seconds
Started	Sep 03 09:00:14 PM UTC 24
Finished	Sep 03 09:00:15 PM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792883711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 7.prim_async_alert.1792883711
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/7.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.102914710
Short name	T12
Test name
Test status
Simulation time	11914145 ps
CPU time	0.33 seconds
Started	Sep 03 09:00:15 PM UTC 24
Finished	Sep 03 09:00:16 PM UTC 24
Peak memory	155156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102914710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 8.prim_async_alert.102914710
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/8.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1412604727
Short name	T22
Test name
Test status
Simulation time	12403418 ps
CPU time	0.36 seconds
Started	Sep 03 09:00:15 PM UTC 24
Finished	Sep 03 09:00:17 PM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412604727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.1412604727
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/9.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.4198576948
Short name	T40
Test name
Test status
Simulation time	30127442 ps
CPU time	0.42 seconds
Started	Sep 03 09:00:20 PM UTC 24
Finished	Sep 03 09:00:21 PM UTC 24
Peak memory	154904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198576948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.4198576948
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3539849713
Short name	T49
Test name
Test status
Simulation time	30608542 ps
CPU time	0.44 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539849713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.3539849713
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1463343183
Short name	T51
Test name
Test status
Simulation time	28951410 ps
CPU time	0.45 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463343183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.1463343183
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.1836992830
Short name	T46
Test name
Test status
Simulation time	29901252 ps
CPU time	0.34 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836992830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 12.prim_async_fatal_alert.1836992830
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.947426718
Short name	T52
Test name
Test status
Simulation time	32558617 ps
CPU time	0.4 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947426718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 13.prim_async_fatal_alert.947426718
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.924460085
Short name	T19
Test name
Test status
Simulation time	29098261 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924460085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 14.prim_async_fatal_alert.924460085
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.1203114915
Short name	T50
Test name
Test status
Simulation time	29803597 ps
CPU time	0.36 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203114915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.1203114915
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2215035947
Short name	T53
Test name
Test status
Simulation time	30753903 ps
CPU time	0.41 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215035947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 16.prim_async_fatal_alert.2215035947
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.1902776239
Short name	T54
Test name
Test status
Simulation time	31081867 ps
CPU time	0.4 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902776239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 17.prim_async_fatal_alert.1902776239
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.107357753
Short name	T56
Test name
Test status
Simulation time	28780837 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107357753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 18.prim_async_fatal_alert.107357753
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.1142529907
Short name	T55
Test name
Test status
Simulation time	30822953 ps
CPU time	0.38 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142529907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 19.prim_async_fatal_alert.1142529907
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3589335102
Short name	T41
Test name
Test status
Simulation time	30000687 ps
CPU time	0.4 seconds
Started	Sep 03 09:00:20 PM UTC 24
Finished	Sep 03 09:00:21 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589335102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.3589335102
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2882717090
Short name	T42
Test name
Test status
Simulation time	31064233 ps
CPU time	0.41 seconds
Started	Sep 03 09:00:20 PM UTC 24
Finished	Sep 03 09:00:21 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882717090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 3.prim_async_fatal_alert.2882717090
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.928238701
Short name	T18
Test name
Test status
Simulation time	29584493 ps
CPU time	0.36 seconds
Started	Sep 03 09:00:20 PM UTC 24
Finished	Sep 03 09:00:21 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928238701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 4.prim_async_fatal_alert.928238701
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.3112509966
Short name	T43
Test name
Test status
Simulation time	28335153 ps
CPU time	0.37 seconds
Started	Sep 03 09:00:20 PM UTC 24
Finished	Sep 03 09:00:21 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112509966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 5.prim_async_fatal_alert.3112509966
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.1442423517
Short name	T44
Test name
Test status
Simulation time	29486348 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:20 PM UTC 24
Finished	Sep 03 09:00:21 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442423517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 6.prim_async_fatal_alert.1442423517
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.96702502
Short name	T38
Test name
Test status
Simulation time	29566359 ps
CPU time	0.4 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:22 PM UTC 24
Peak memory	155024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96702502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 7.prim_async_fatal_alert.96702502
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3617069306
Short name	T45
Test name
Test status
Simulation time	30678034 ps
CPU time	0.36 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617069306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 8.prim_async_fatal_alert.3617069306
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3657592856
Short name	T35
Test name
Test status
Simulation time	8422113 ps
CPU time	0.38 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657592856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.3657592856
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/0.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2258858647
Short name	T36
Test name
Test status
Simulation time	9530585 ps
CPU time	0.37 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258858647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 1.prim_sync_alert.2258858647
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/1.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3569299060
Short name	T34
Test name
Test status
Simulation time	11059278 ps
CPU time	0.36 seconds
Started	Sep 03 09:00:23 PM UTC 24
Finished	Sep 03 09:00:25 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569299060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.3569299060
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/11.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3666455853
Short name	T32
Test name
Test status
Simulation time	8447817 ps
CPU time	0.34 seconds
Started	Sep 03 09:00:23 PM UTC 24
Finished	Sep 03 09:00:25 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666455853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.3666455853
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/12.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.4049541634
Short name	T57
Test name
Test status
Simulation time	8730772 ps
CPU time	0.38 seconds
Started	Sep 03 09:00:23 PM UTC 24
Finished	Sep 03 09:00:25 PM UTC 24
Peak memory	154260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049541634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 13.prim_sync_alert.4049541634
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/13.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1081583500
Short name	T58
Test name
Test status
Simulation time	10201318 ps
CPU time	0.34 seconds
Started	Sep 03 09:00:23 PM UTC 24
Finished	Sep 03 09:00:25 PM UTC 24
Peak memory	154232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081583500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.1081583500
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/14.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2438179658
Short name	T60
Test name
Test status
Simulation time	9970700 ps
CPU time	0.36 seconds
Started	Sep 03 09:00:23 PM UTC 24
Finished	Sep 03 09:00:25 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438179658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.2438179658
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/15.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.746836924
Short name	T59
Test name
Test status
Simulation time	8417900 ps
CPU time	0.34 seconds
Started	Sep 03 09:00:23 PM UTC 24
Finished	Sep 03 09:00:25 PM UTC 24
Peak memory	154552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746836924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 16.prim_sync_alert.746836924
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/16.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3092726008
Short name	T61
Test name
Test status
Simulation time	10569657 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:23 PM UTC 24
Finished	Sep 03 09:00:25 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092726008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 17.prim_sync_alert.3092726008
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/17.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.1387405911
Short name	T62
Test name
Test status
Simulation time	9214272 ps
CPU time	0.36 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387405911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 18.prim_sync_alert.1387405911
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/18.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.673570252
Short name	T63
Test name
Test status
Simulation time	9349468 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673570252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 19.prim_sync_alert.673570252
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/19.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.4046437839
Short name	T16
Test name
Test status
Simulation time	9000796 ps
CPU time	0.34 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046437839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 2.prim_sync_alert.4046437839
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/2.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2773384617
Short name	T29
Test name
Test status
Simulation time	9592765 ps
CPU time	0.38 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773384617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 3.prim_sync_alert.2773384617
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/3.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2814147303
Short name	T27
Test name
Test status
Simulation time	10227178 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814147303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.2814147303
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/4.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.468226824
Short name	T28
Test name
Test status
Simulation time	9001814 ps
CPU time	0.33 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468226824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 5.prim_sync_alert.468226824
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/5.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2115729145
Short name	T30
Test name
Test status
Simulation time	9204248 ps
CPU time	0.34 seconds
Started	Sep 03 09:00:21 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115729145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 6.prim_sync_alert.2115729145
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/6.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.4102422312
Short name	T37
Test name
Test status
Simulation time	8497684 ps
CPU time	0.34 seconds
Started	Sep 03 09:00:22 PM UTC 24
Finished	Sep 03 09:00:23 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102422312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.4102422312
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/8.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3830119246
Short name	T33
Test name
Test status
Simulation time	9273902 ps
CPU time	0.39 seconds
Started	Sep 03 09:00:23 PM UTC 24
Finished	Sep 03 09:00:25 PM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830119246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.3830119246
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/9.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1890125269
Short name	T70
Test name
Test status
Simulation time	28164349 ps
CPU time	0.36 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890125269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1890125269
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.326809813
Short name	T10
Test name
Test status
Simulation time	26449961 ps
CPU time	0.37 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326809813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.326809813
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.440555110
Short name	T5
Test name
Test status
Simulation time	30241351 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440555110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.440555110
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2463515639
Short name	T71
Test name
Test status
Simulation time	27274735 ps
CPU time	0.38 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	155288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463515639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2463515639
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1895849713
Short name	T75
Test name
Test status
Simulation time	27012067 ps
CPU time	0.43 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895849713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1895849713
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1441185700
Short name	T77
Test name
Test status
Simulation time	26675123 ps
CPU time	0.37 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	153816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441185700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1441185700
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2929135496
Short name	T78
Test name
Test status
Simulation time	27760158 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929135496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2929135496
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.942289622
Short name	T6
Test name
Test status
Simulation time	28815080 ps
CPU time	0.38 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942289622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.942289622
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.30432579
Short name	T76
Test name
Test status
Simulation time	28458831 ps
CPU time	0.4 seconds
Started	Sep 03 09:00:25 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	153860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30432579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert .vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.30432579
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3939384330
Short name	T74
Test name
Test status
Simulation time	29981193 ps
CPU time	0.41 seconds
Started	Sep 03 09:00:25 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939384330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3939384330
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1157414168
Short name	T79
Test name
Test status
Simulation time	27733540 ps
CPU time	0.37 seconds
Started	Sep 03 09:00:25 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157414168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1157414168
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3632819158
Short name	T80
Test name
Test status
Simulation time	28934381 ps
CPU time	0.39 seconds
Started	Sep 03 09:00:25 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632819158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3632819158
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3317303561
Short name	T69
Test name
Test status
Simulation time	26333675 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317303561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3317303561
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1064436190
Short name	T64
Test name
Test status
Simulation time	25745295 ps
CPU time	0.38 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064436190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1064436190
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3281515663
Short name	T67
Test name
Test status
Simulation time	28948325 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281515663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3281515663
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2382427905
Short name	T66
Test name
Test status
Simulation time	27649048 ps
CPU time	0.4 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382427905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2382427905
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4109647990
Short name	T65
Test name
Test status
Simulation time	26804327 ps
CPU time	0.36 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109647990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.4109647990
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.458786891
Short name	T68
Test name
Test status
Simulation time	25690797 ps
CPU time	0.39 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458786891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.458786891
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.743518849
Short name	T73
Test name
Test status
Simulation time	27797588 ps
CPU time	0.38 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	154176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743518849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.743518849
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4057373269
Short name	T72
Test name
Test status
Simulation time	26722774 ps
CPU time	0.35 seconds
Started	Sep 03 09:00:24 PM UTC 24
Finished	Sep 03 09:00:26 PM UTC 24
Peak memory	155276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057373269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.4057373269
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest