Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.85	100.00	97.92	100.00	89.29	95.83	86.05

Total tests in report: 79

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
89.23	89.23	100.00	100.00	95.83	95.83	100.00	100.00	78.57	78.57	95.83	95.83	65.12	65.12	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3326017400
92.35	3.13	100.00	0.00	95.83	0.00	100.00	0.00	85.71	7.14	95.83	0.00	76.74	11.63	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1614489445
94.11	1.76	100.00	0.00	95.83	0.00	100.00	0.00	89.29	3.57	95.83	0.00	83.72	6.98	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.4014927113
94.50	0.39	100.00	0.00	95.83	0.00	100.00	0.00	89.29	0.00	95.83	0.00	86.05	2.33	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3748106834
94.85	0.35	100.00	0.00	97.92	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1542348049

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.1113006650
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.1668932211
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1856280870
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1762277901
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.2239459498
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.538145661
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2760768329
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.4132598223
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1769098629
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.4258129350
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.2262221395
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.777785068
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.491898286
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.572313401
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2184907054
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.3530583750
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2935979654
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1971602322
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3694447365
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3691133088
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.3191694638
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.17290541
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.796802437
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.879750878
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.1147118582
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.884219252
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2378651157
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.3681677947
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.102071530
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2958414850
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1619736307
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1702698026
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.2015372490
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3210691377
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.4240804884
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.4259034962
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1007084029
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1908170648
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.119916553
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.3475916330
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1637597112
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2770293603
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.2068970314
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.236145951
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2815384113
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.3615099244
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2986903752
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2035144914
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.1861633487
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.2632931648
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.48838057
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3097707848
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.809829416
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1832637265
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2735510050
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2459402764
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2590266262
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.19816288
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3186089893
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3839433111
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.272461076
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3385382469
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3051466109
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3933470653
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2165243808
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3320031841
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.306093581
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.203376966
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1911730256
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1499413481
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4260776480
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.261845849
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4131037534
/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2353398473

Total test records in report: 79

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3748106834	Sep 09 03:09:01 AM UTC 24	Sep 09 03:09:02 AM UTC 24	10947938 ps
T2	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.1113006650	Sep 09 03:09:01 AM UTC 24	Sep 09 03:09:02 AM UTC 24	11222434 ps
T3	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.777785068	Sep 09 03:09:01 AM UTC 24	Sep 09 03:09:02 AM UTC 24	12399504 ps
T17	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.491898286	Sep 09 03:09:02 AM UTC 24	Sep 09 03:09:03 AM UTC 24	10787115 ps
T18	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.3530583750	Sep 09 03:09:03 AM UTC 24	Sep 09 03:09:04 AM UTC 24	10684223 ps
T7	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2184907054	Sep 09 03:09:03 AM UTC 24	Sep 09 03:09:04 AM UTC 24	11748684 ps
T8	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3326017400	Sep 09 03:09:03 AM UTC 24	Sep 09 03:09:04 AM UTC 24	11118633 ps
T19	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.572313401	Sep 09 03:09:03 AM UTC 24	Sep 09 03:09:04 AM UTC 24	10473391 ps
T20	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1971602322	Sep 09 03:09:03 AM UTC 24	Sep 09 03:09:04 AM UTC 24	11089538 ps
T21	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2935979654	Sep 09 03:09:03 AM UTC 24	Sep 09 03:09:04 AM UTC 24	10896486 ps
T9	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.1668932211	Sep 09 03:09:05 AM UTC 24	Sep 09 03:09:06 AM UTC 24	12337448 ps
T47	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1856280870	Sep 09 03:09:05 AM UTC 24	Sep 09 03:09:06 AM UTC 24	10935157 ps
T14	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1762277901	Sep 09 03:09:06 AM UTC 24	Sep 09 03:09:07 AM UTC 24	10758183 ps
T48	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.2239459498	Sep 09 03:09:06 AM UTC 24	Sep 09 03:09:07 AM UTC 24	11164164 ps
T49	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.538145661	Sep 09 03:09:06 AM UTC 24	Sep 09 03:09:07 AM UTC 24	11226067 ps
T22	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.2262221395	Sep 09 03:09:06 AM UTC 24	Sep 09 03:09:08 AM UTC 24	10727155 ps
T23	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.4132598223	Sep 09 03:09:06 AM UTC 24	Sep 09 03:09:08 AM UTC 24	10904418 ps
T50	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2760768329	Sep 09 03:09:06 AM UTC 24	Sep 09 03:09:08 AM UTC 24	11266366 ps
T51	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1769098629	Sep 09 03:09:06 AM UTC 24	Sep 09 03:09:08 AM UTC 24	10603825 ps
T52	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.4258129350	Sep 09 03:09:06 AM UTC 24	Sep 09 03:09:08 AM UTC 24	11475108 ps
T15	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.4014927113	Sep 09 02:54:49 AM UTC 24	Sep 09 02:54:50 AM UTC 24	30405906 ps
T39	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3694447365	Sep 09 02:54:49 AM UTC 24	Sep 09 02:54:50 AM UTC 24	30666396 ps
T40	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2958414850	Sep 09 02:54:49 AM UTC 24	Sep 09 02:54:51 AM UTC 24	29493271 ps
T41	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1702698026	Sep 09 02:54:51 AM UTC 24	Sep 09 02:54:52 AM UTC 24	29918375 ps
T42	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1619736307	Sep 09 02:54:51 AM UTC 24	Sep 09 02:54:52 AM UTC 24	32022482 ps
T4	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1542348049	Sep 09 02:54:52 AM UTC 24	Sep 09 02:54:53 AM UTC 24	28284358 ps
T43	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.2015372490	Sep 09 02:54:52 AM UTC 24	Sep 09 02:54:54 AM UTC 24	30271488 ps
T44	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3210691377	Sep 09 02:54:52 AM UTC 24	Sep 09 02:54:54 AM UTC 24	29690539 ps
T45	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.4240804884	Sep 09 02:54:53 AM UTC 24	Sep 09 02:54:55 AM UTC 24	30177133 ps
T46	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.3191694638	Sep 09 02:54:53 AM UTC 24	Sep 09 02:54:55 AM UTC 24	29109450 ps
T12	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3691133088	Sep 09 02:54:53 AM UTC 24	Sep 09 02:54:55 AM UTC 24	31948441 ps
T53	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.17290541	Sep 09 02:54:53 AM UTC 24	Sep 09 02:54:55 AM UTC 24	30553783 ps
T54	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.796802437	Sep 09 02:54:53 AM UTC 24	Sep 09 02:54:55 AM UTC 24	30761391 ps
T55	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.884219252	Sep 09 02:54:54 AM UTC 24	Sep 09 02:54:56 AM UTC 24	27693812 ps
T13	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.1147118582	Sep 09 02:54:54 AM UTC 24	Sep 09 02:54:56 AM UTC 24	29976004 ps
T10	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.879750878	Sep 09 02:54:54 AM UTC 24	Sep 09 02:54:56 AM UTC 24	30897958 ps
T56	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2378651157	Sep 09 02:54:54 AM UTC 24	Sep 09 02:54:56 AM UTC 24	30795211 ps
T16	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.102071530	Sep 09 02:54:55 AM UTC 24	Sep 09 02:54:56 AM UTC 24	31356189 ps
T57	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.3681677947	Sep 09 02:54:55 AM UTC 24	Sep 09 02:54:56 AM UTC 24	31018003 ps
T24	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.4259034962	Sep 09 03:09:06 AM UTC 24	Sep 09 03:09:08 AM UTC 24	9133227 ps
T34	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1007084029	Sep 09 03:09:06 AM UTC 24	Sep 09 03:09:08 AM UTC 24	8899280 ps
T35	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2986903752	Sep 09 03:09:08 AM UTC 24	Sep 09 03:09:10 AM UTC 24	8760471 ps
T36	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2035144914	Sep 09 03:09:08 AM UTC 24	Sep 09 03:09:10 AM UTC 24	9297132 ps
T25	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.2632931648	Sep 09 03:09:10 AM UTC 24	Sep 09 03:09:11 AM UTC 24	10112515 ps
T26	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.1861633487	Sep 09 03:09:10 AM UTC 24	Sep 09 03:09:11 AM UTC 24	9847845 ps
T27	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.48838057	Sep 09 03:09:10 AM UTC 24	Sep 09 03:09:11 AM UTC 24	9620396 ps
T37	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3097707848	Sep 09 03:09:10 AM UTC 24	Sep 09 03:09:11 AM UTC 24	10341524 ps
T28	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1832637265	Sep 09 03:09:10 AM UTC 24	Sep 09 03:09:11 AM UTC 24	8895077 ps
T38	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1614489445	Sep 09 03:09:10 AM UTC 24	Sep 09 03:09:11 AM UTC 24	10158425 ps
T58	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.809829416	Sep 09 03:09:10 AM UTC 24	Sep 09 03:09:11 AM UTC 24	9315330 ps
T29	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.3475916330	Sep 09 03:09:10 AM UTC 24	Sep 09 03:09:11 AM UTC 24	9455374 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1908170648	Sep 09 03:09:10 AM UTC 24	Sep 09 03:09:11 AM UTC 24	9968557 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.119916553	Sep 09 03:09:10 AM UTC 24	Sep 09 03:09:11 AM UTC 24	9809034 ps
T30	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1637597112	Sep 09 03:09:11 AM UTC 24	Sep 09 03:09:12 AM UTC 24	9248948 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2770293603	Sep 09 03:09:11 AM UTC 24	Sep 09 03:09:12 AM UTC 24	8928228 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.236145951	Sep 09 03:09:11 AM UTC 24	Sep 09 03:09:12 AM UTC 24	8769742 ps
T31	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.2068970314	Sep 09 03:09:11 AM UTC 24	Sep 09 03:09:12 AM UTC 24	7886063 ps
T32	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2815384113	Sep 09 03:09:11 AM UTC 24	Sep 09 03:09:12 AM UTC 24	9093908 ps
T33	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.3615099244	Sep 09 03:09:12 AM UTC 24	Sep 09 03:09:13 AM UTC 24	10168266 ps
T63	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2735510050	Sep 09 03:09:58 AM UTC 24	Sep 09 03:10:00 AM UTC 24	26418957 ps
T64	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2459402764	Sep 09 03:09:58 AM UTC 24	Sep 09 03:10:00 AM UTC 24	26047419 ps
T65	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.306093581	Sep 09 03:09:58 AM UTC 24	Sep 09 03:10:00 AM UTC 24	27104273 ps
T11	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.203376966	Sep 09 03:09:58 AM UTC 24	Sep 09 03:10:00 AM UTC 24	29087906 ps
T66	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1911730256	Sep 09 03:09:58 AM UTC 24	Sep 09 03:10:00 AM UTC 24	28910013 ps
T67	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1499413481	Sep 09 03:09:58 AM UTC 24	Sep 09 03:10:00 AM UTC 24	28233636 ps
T68	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4131037534	Sep 09 03:10:01 AM UTC 24	Sep 09 03:10:03 AM UTC 24	28380645 ps
T69	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4260776480	Sep 09 03:10:01 AM UTC 24	Sep 09 03:10:03 AM UTC 24	25412186 ps
T70	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.261845849	Sep 09 03:10:01 AM UTC 24	Sep 09 03:10:03 AM UTC 24	27655946 ps
T71	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2353398473	Sep 09 03:10:01 AM UTC 24	Sep 09 03:10:03 AM UTC 24	28556321 ps
T72	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.19816288	Sep 09 03:10:02 AM UTC 24	Sep 09 03:10:03 AM UTC 24	29854393 ps
T73	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2590266262	Sep 09 03:10:02 AM UTC 24	Sep 09 03:10:03 AM UTC 24	27789715 ps
T5	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3186089893	Sep 09 03:10:04 AM UTC 24	Sep 09 03:10:05 AM UTC 24	28637663 ps
T6	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.272461076	Sep 09 03:10:04 AM UTC 24	Sep 09 03:10:05 AM UTC 24	28405425 ps
T74	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3839433111	Sep 09 03:10:04 AM UTC 24	Sep 09 03:10:05 AM UTC 24	26132436 ps
T75	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3051466109	Sep 09 03:10:04 AM UTC 24	Sep 09 03:10:05 AM UTC 24	27154571 ps
T76	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3385382469	Sep 09 03:10:04 AM UTC 24	Sep 09 03:10:05 AM UTC 24	25829020 ps
T77	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3933470653	Sep 09 03:10:04 AM UTC 24	Sep 09 03:10:05 AM UTC 24	29303531 ps
T78	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2165243808	Sep 09 03:10:06 AM UTC 24	Sep 09 03:10:08 AM UTC 24	29811581 ps
T79	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3320031841	Sep 09 03:10:06 AM UTC 24	Sep 09 03:10:08 AM UTC 24	28765064 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3326017400
Short name	T8
Test name
Test status
Simulation time	11118633 ps
CPU time	0.36 seconds
Started	Sep 09 03:09:03 AM UTC 24
Finished	Sep 09 03:09:04 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326017400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 4.prim_async_alert.3326017400
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/4.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.1614489445
Short name	T38
Test name
Test status
Simulation time	10158425 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:10 AM UTC 24
Finished	Sep 09 03:09:11 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614489445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.1614489445
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/10.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.4014927113
Short name	T15
Test name
Test status
Simulation time	30405906 ps
CPU time	0.87 seconds
Started	Sep 09 02:54:49 AM UTC 24
Finished	Sep 09 02:54:50 AM UTC 24
Peak memory	154508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014927113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 0.prim_async_fatal_alert.4014927113
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3748106834
Short name	T1
Test name
Test status
Simulation time	10947938 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:01 AM UTC 24
Finished	Sep 09 03:09:02 AM UTC 24
Peak memory	155224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748106834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.prim_async_alert.3748106834
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/0.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1542348049
Short name	T4
Test name
Test status
Simulation time	28284358 ps
CPU time	0.64 seconds
Started	Sep 09 02:54:52 AM UTC 24
Finished	Sep 09 02:54:53 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542348049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 5.prim_async_fatal_alert.1542348049
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.1113006650
Short name	T2
Test name
Test status
Simulation time	11222434 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:01 AM UTC 24
Finished	Sep 09 03:09:02 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113006650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.prim_async_alert.1113006650
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/1.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.1668932211
Short name	T9
Test name
Test status
Simulation time	12337448 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:05 AM UTC 24
Finished	Sep 09 03:09:06 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668932211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 10.prim_async_alert.1668932211
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/10.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1856280870
Short name	T47
Test name
Test status
Simulation time	10935157 ps
CPU time	0.35 seconds
Started	Sep 09 03:09:05 AM UTC 24
Finished	Sep 09 03:09:06 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856280870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 11.prim_async_alert.1856280870
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/11.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1762277901
Short name	T14
Test name
Test status
Simulation time	10758183 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:06 AM UTC 24
Finished	Sep 09 03:09:07 AM UTC 24
Peak memory	155004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762277901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 12.prim_async_alert.1762277901
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/12.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.2239459498
Short name	T48
Test name
Test status
Simulation time	11164164 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:06 AM UTC 24
Finished	Sep 09 03:09:07 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239459498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.prim_async_alert.2239459498
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/13.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.538145661
Short name	T49
Test name
Test status
Simulation time	11226067 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:06 AM UTC 24
Finished	Sep 09 03:09:07 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538145661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 14.prim_async_alert.538145661
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/14.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2760768329
Short name	T50
Test name
Test status
Simulation time	11266366 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:06 AM UTC 24
Finished	Sep 09 03:09:08 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760768329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.2760768329
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/15.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.4132598223
Short name	T23
Test name
Test status
Simulation time	10904418 ps
CPU time	0.35 seconds
Started	Sep 09 03:09:06 AM UTC 24
Finished	Sep 09 03:09:08 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132598223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 16.prim_async_alert.4132598223
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/16.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1769098629
Short name	T51
Test name
Test status
Simulation time	10603825 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:06 AM UTC 24
Finished	Sep 09 03:09:08 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769098629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.1769098629
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/17.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.4258129350
Short name	T52
Test name
Test status
Simulation time	11475108 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:06 AM UTC 24
Finished	Sep 09 03:09:08 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258129350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.prim_async_alert.4258129350
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/18.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.2262221395
Short name	T22
Test name
Test status
Simulation time	10727155 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:06 AM UTC 24
Finished	Sep 09 03:09:08 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262221395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 19.prim_async_alert.2262221395
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/19.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.777785068
Short name	T3
Test name
Test status
Simulation time	12399504 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:01 AM UTC 24
Finished	Sep 09 03:09:02 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777785068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.prim_async_alert.777785068
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/2.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.491898286
Short name	T17
Test name
Test status
Simulation time	10787115 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:02 AM UTC 24
Finished	Sep 09 03:09:03 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491898286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 3.prim_async_alert.491898286
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/3.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.572313401
Short name	T19
Test name
Test status
Simulation time	10473391 ps
CPU time	0.37 seconds
Started	Sep 09 03:09:03 AM UTC 24
Finished	Sep 09 03:09:04 AM UTC 24
Peak memory	155164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572313401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 5.prim_async_alert.572313401
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/5.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2184907054
Short name	T7
Test name
Test status
Simulation time	11748684 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:03 AM UTC 24
Finished	Sep 09 03:09:04 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184907054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.prim_async_alert.2184907054
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/6.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.3530583750
Short name	T18
Test name
Test status
Simulation time	10684223 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:03 AM UTC 24
Finished	Sep 09 03:09:04 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530583750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 7.prim_async_alert.3530583750
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/7.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2935979654
Short name	T21
Test name
Test status
Simulation time	10896486 ps
CPU time	0.35 seconds
Started	Sep 09 03:09:03 AM UTC 24
Finished	Sep 09 03:09:04 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935979654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.prim_async_alert.2935979654
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/8.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1971602322
Short name	T20
Test name
Test status
Simulation time	11089538 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:03 AM UTC 24
Finished	Sep 09 03:09:04 AM UTC 24
Peak memory	155160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971602322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.1971602322
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/9.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3694447365
Short name	T39
Test name
Test status
Simulation time	30666396 ps
CPU time	0.74 seconds
Started	Sep 09 02:54:49 AM UTC 24
Finished	Sep 09 02:54:50 AM UTC 24
Peak memory	154508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694447365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.3694447365
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3691133088
Short name	T12
Test name
Test status
Simulation time	31948441 ps
CPU time	0.65 seconds
Started	Sep 09 02:54:53 AM UTC 24
Finished	Sep 09 02:54:55 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691133088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.3691133088
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.3191694638
Short name	T46
Test name
Test status
Simulation time	29109450 ps
CPU time	0.61 seconds
Started	Sep 09 02:54:53 AM UTC 24
Finished	Sep 09 02:54:55 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191694638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.3191694638
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.17290541
Short name	T53
Test name
Test status
Simulation time	30553783 ps
CPU time	0.62 seconds
Started	Sep 09 02:54:53 AM UTC 24
Finished	Sep 09 02:54:55 AM UTC 24
Peak memory	155016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17290541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 12.prim_async_fatal_alert.17290541
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.796802437
Short name	T54
Test name
Test status
Simulation time	30761391 ps
CPU time	0.69 seconds
Started	Sep 09 02:54:53 AM UTC 24
Finished	Sep 09 02:54:55 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796802437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 13.prim_async_fatal_alert.796802437
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.879750878
Short name	T10
Test name
Test status
Simulation time	30897958 ps
CPU time	0.67 seconds
Started	Sep 09 02:54:54 AM UTC 24
Finished	Sep 09 02:54:56 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879750878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 14.prim_async_fatal_alert.879750878
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.1147118582
Short name	T13
Test name
Test status
Simulation time	29976004 ps
CPU time	0.65 seconds
Started	Sep 09 02:54:54 AM UTC 24
Finished	Sep 09 02:54:56 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147118582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.1147118582
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.884219252
Short name	T55
Test name
Test status
Simulation time	27693812 ps
CPU time	0.61 seconds
Started	Sep 09 02:54:54 AM UTC 24
Finished	Sep 09 02:54:56 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884219252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 16.prim_async_fatal_alert.884219252
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2378651157
Short name	T56
Test name
Test status
Simulation time	30795211 ps
CPU time	0.64 seconds
Started	Sep 09 02:54:54 AM UTC 24
Finished	Sep 09 02:54:56 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378651157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 17.prim_async_fatal_alert.2378651157
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.3681677947
Short name	T57
Test name
Test status
Simulation time	31018003 ps
CPU time	0.69 seconds
Started	Sep 09 02:54:55 AM UTC 24
Finished	Sep 09 02:54:56 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681677947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 18.prim_async_fatal_alert.3681677947
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.102071530
Short name	T16
Test name
Test status
Simulation time	31356189 ps
CPU time	0.68 seconds
Started	Sep 09 02:54:55 AM UTC 24
Finished	Sep 09 02:54:56 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102071530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 19.prim_async_fatal_alert.102071530
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2958414850
Short name	T40
Test name
Test status
Simulation time	29493271 ps
CPU time	0.46 seconds
Started	Sep 09 02:54:49 AM UTC 24
Finished	Sep 09 02:54:51 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958414850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.2958414850
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1619736307
Short name	T42
Test name
Test status
Simulation time	32022482 ps
CPU time	0.67 seconds
Started	Sep 09 02:54:51 AM UTC 24
Finished	Sep 09 02:54:52 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619736307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 3.prim_async_fatal_alert.1619736307
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1702698026
Short name	T41
Test name
Test status
Simulation time	29918375 ps
CPU time	0.63 seconds
Started	Sep 09 02:54:51 AM UTC 24
Finished	Sep 09 02:54:52 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702698026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 4.prim_async_fatal_alert.1702698026
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.2015372490
Short name	T43
Test name
Test status
Simulation time	30271488 ps
CPU time	0.69 seconds
Started	Sep 09 02:54:52 AM UTC 24
Finished	Sep 09 02:54:54 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015372490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 7.prim_async_fatal_alert.2015372490
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3210691377
Short name	T44
Test name
Test status
Simulation time	29690539 ps
CPU time	0.68 seconds
Started	Sep 09 02:54:52 AM UTC 24
Finished	Sep 09 02:54:54 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210691377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 8.prim_async_fatal_alert.3210691377
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.4240804884
Short name	T45
Test name
Test status
Simulation time	30177133 ps
CPU time	0.64 seconds
Started	Sep 09 02:54:53 AM UTC 24
Finished	Sep 09 02:54:55 AM UTC 24
Peak memory	155020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240804884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 9.prim_async_fatal_alert.4240804884
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.4259034962
Short name	T24
Test name
Test status
Simulation time	9133227 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:06 AM UTC 24
Finished	Sep 09 03:09:08 AM UTC 24
Peak memory	154612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259034962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.4259034962
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/0.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1007084029
Short name	T34
Test name
Test status
Simulation time	8899280 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:06 AM UTC 24
Finished	Sep 09 03:09:08 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007084029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 1.prim_sync_alert.1007084029
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/1.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1908170648
Short name	T59
Test name
Test status
Simulation time	9968557 ps
CPU time	0.35 seconds
Started	Sep 09 03:09:10 AM UTC 24
Finished	Sep 09 03:09:11 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908170648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.1908170648
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/11.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.119916553
Short name	T60
Test name
Test status
Simulation time	9809034 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:10 AM UTC 24
Finished	Sep 09 03:09:11 AM UTC 24
Peak memory	154552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119916553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 12.prim_sync_alert.119916553
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/12.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.3475916330
Short name	T29
Test name
Test status
Simulation time	9455374 ps
CPU time	0.31 seconds
Started	Sep 09 03:09:10 AM UTC 24
Finished	Sep 09 03:09:11 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475916330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 13.prim_sync_alert.3475916330
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/13.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.1637597112
Short name	T30
Test name
Test status
Simulation time	9248948 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:11 AM UTC 24
Finished	Sep 09 03:09:12 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637597112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.1637597112
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/14.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2770293603
Short name	T61
Test name
Test status
Simulation time	8928228 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:11 AM UTC 24
Finished	Sep 09 03:09:12 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770293603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.2770293603
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/15.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.2068970314
Short name	T31
Test name
Test status
Simulation time	7886063 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:11 AM UTC 24
Finished	Sep 09 03:09:12 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068970314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 16.prim_sync_alert.2068970314
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/16.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.236145951
Short name	T62
Test name
Test status
Simulation time	8769742 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:11 AM UTC 24
Finished	Sep 09 03:09:12 AM UTC 24
Peak memory	154552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236145951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 17.prim_sync_alert.236145951
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/17.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2815384113
Short name	T32
Test name
Test status
Simulation time	9093908 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:11 AM UTC 24
Finished	Sep 09 03:09:12 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815384113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 18.prim_sync_alert.2815384113
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/18.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.3615099244
Short name	T33
Test name
Test status
Simulation time	10168266 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:12 AM UTC 24
Finished	Sep 09 03:09:13 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615099244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 19.prim_sync_alert.3615099244
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/19.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2986903752
Short name	T35
Test name
Test status
Simulation time	8760471 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:08 AM UTC 24
Finished	Sep 09 03:09:10 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986903752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 2.prim_sync_alert.2986903752
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/2.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2035144914
Short name	T36
Test name
Test status
Simulation time	9297132 ps
CPU time	0.34 seconds
Started	Sep 09 03:09:08 AM UTC 24
Finished	Sep 09 03:09:10 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035144914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 3.prim_sync_alert.2035144914
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/3.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.1861633487
Short name	T26
Test name
Test status
Simulation time	9847845 ps
CPU time	0.37 seconds
Started	Sep 09 03:09:10 AM UTC 24
Finished	Sep 09 03:09:11 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861633487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.1861633487
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/4.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.2632931648
Short name	T25
Test name
Test status
Simulation time	10112515 ps
CPU time	0.32 seconds
Started	Sep 09 03:09:10 AM UTC 24
Finished	Sep 09 03:09:11 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632931648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 5.prim_sync_alert.2632931648
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/5.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.48838057
Short name	T27
Test name
Test status
Simulation time	9620396 ps
CPU time	0.34 seconds
Started	Sep 09 03:09:10 AM UTC 24
Finished	Sep 09 03:09:11 AM UTC 24
Peak memory	154556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48838057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.48838057
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/6.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3097707848
Short name	T37
Test name
Test status
Simulation time	10341524 ps
CPU time	0.34 seconds
Started	Sep 09 03:09:10 AM UTC 24
Finished	Sep 09 03:09:11 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097707848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.3097707848
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/7.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.809829416
Short name	T58
Test name
Test status
Simulation time	9315330 ps
CPU time	0.37 seconds
Started	Sep 09 03:09:10 AM UTC 24
Finished	Sep 09 03:09:11 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809829416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 8.prim_sync_alert.809829416
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/8.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1832637265
Short name	T28
Test name
Test status
Simulation time	8895077 ps
CPU time	0.33 seconds
Started	Sep 09 03:09:10 AM UTC 24
Finished	Sep 09 03:09:11 AM UTC 24
Peak memory	154548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832637265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.1832637265
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/9.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2735510050
Short name	T63
Test name
Test status
Simulation time	26418957 ps
CPU time	0.48 seconds
Started	Sep 09 03:09:58 AM UTC 24
Finished	Sep 09 03:10:00 AM UTC 24
Peak memory	154252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735510050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2735510050
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2459402764
Short name	T64
Test name
Test status
Simulation time	26047419 ps
CPU time	0.52 seconds
Started	Sep 09 03:09:58 AM UTC 24
Finished	Sep 09 03:10:00 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459402764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2459402764
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2590266262
Short name	T73
Test name
Test status
Simulation time	27789715 ps
CPU time	0.52 seconds
Started	Sep 09 03:10:02 AM UTC 24
Finished	Sep 09 03:10:03 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590266262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2590266262
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.19816288
Short name	T72
Test name
Test status
Simulation time	29854393 ps
CPU time	0.49 seconds
Started	Sep 09 03:10:02 AM UTC 24
Finished	Sep 09 03:10:03 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19816288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert .vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.19816288
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3186089893
Short name	T5
Test name
Test status
Simulation time	28637663 ps
CPU time	0.5 seconds
Started	Sep 09 03:10:04 AM UTC 24
Finished	Sep 09 03:10:05 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186089893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3186089893
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3839433111
Short name	T74
Test name
Test status
Simulation time	26132436 ps
CPU time	0.51 seconds
Started	Sep 09 03:10:04 AM UTC 24
Finished	Sep 09 03:10:05 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839433111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3839433111
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.272461076
Short name	T6
Test name
Test status
Simulation time	28405425 ps
CPU time	0.51 seconds
Started	Sep 09 03:10:04 AM UTC 24
Finished	Sep 09 03:10:05 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272461076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.272461076
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3385382469
Short name	T76
Test name
Test status
Simulation time	25829020 ps
CPU time	0.48 seconds
Started	Sep 09 03:10:04 AM UTC 24
Finished	Sep 09 03:10:05 AM UTC 24
Peak memory	154112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385382469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3385382469
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3051466109
Short name	T75
Test name
Test status
Simulation time	27154571 ps
CPU time	0.52 seconds
Started	Sep 09 03:10:04 AM UTC 24
Finished	Sep 09 03:10:05 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051466109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3051466109
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3933470653
Short name	T77
Test name
Test status
Simulation time	29303531 ps
CPU time	0.47 seconds
Started	Sep 09 03:10:04 AM UTC 24
Finished	Sep 09 03:10:05 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933470653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3933470653
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2165243808
Short name	T78
Test name
Test status
Simulation time	29811581 ps
CPU time	0.5 seconds
Started	Sep 09 03:10:06 AM UTC 24
Finished	Sep 09 03:10:08 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165243808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2165243808
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3320031841
Short name	T79
Test name
Test status
Simulation time	28765064 ps
CPU time	0.52 seconds
Started	Sep 09 03:10:06 AM UTC 24
Finished	Sep 09 03:10:08 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320031841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3320031841
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.306093581
Short name	T65
Test name
Test status
Simulation time	27104273 ps
CPU time	0.49 seconds
Started	Sep 09 03:09:58 AM UTC 24
Finished	Sep 09 03:10:00 AM UTC 24
Peak memory	154172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306093581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.306093581
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.203376966
Short name	T11
Test name
Test status
Simulation time	29087906 ps
CPU time	0.52 seconds
Started	Sep 09 03:09:58 AM UTC 24
Finished	Sep 09 03:10:00 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203376966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.203376966
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1911730256
Short name	T66
Test name
Test status
Simulation time	28910013 ps
CPU time	0.52 seconds
Started	Sep 09 03:09:58 AM UTC 24
Finished	Sep 09 03:10:00 AM UTC 24
Peak memory	154184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911730256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1911730256
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1499413481
Short name	T67
Test name
Test status
Simulation time	28233636 ps
CPU time	0.51 seconds
Started	Sep 09 03:09:58 AM UTC 24
Finished	Sep 09 03:10:00 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499413481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1499413481
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4260776480
Short name	T69
Test name
Test status
Simulation time	25412186 ps
CPU time	0.5 seconds
Started	Sep 09 03:10:01 AM UTC 24
Finished	Sep 09 03:10:03 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260776480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.4260776480
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.261845849
Short name	T70
Test name
Test status
Simulation time	27655946 ps
CPU time	0.51 seconds
Started	Sep 09 03:10:01 AM UTC 24
Finished	Sep 09 03:10:03 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261845849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.261845849
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4131037534
Short name	T68
Test name
Test status
Simulation time	28380645 ps
CPU time	0.48 seconds
Started	Sep 09 03:10:01 AM UTC 24
Finished	Sep 09 03:10:03 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131037534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.4131037534
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2353398473
Short name	T71
Test name
Test status
Simulation time	28556321 ps
CPU time	0.48 seconds
Started	Sep 09 03:10:01 AM UTC 24
Finished	Sep 09 03:10:03 AM UTC 24
Peak memory	154188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353398473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2353398473
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest