Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	100.00	100.00	89.29	95.83	86.05

Total tests in report: 79

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
89.27	89.27	100.00	100.00	93.75	93.75	100.00	100.00	78.57	78.57	95.83	95.83	67.44	67.44	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3085197981
93.34	4.07	100.00	0.00	95.83	2.08	100.00	0.00	89.29	10.71	95.83	0.00	79.07	11.63	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.828669360
94.85	1.51	100.00	0.00	97.92	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	6.98	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.4024399114
95.19	0.35	100.00	0.00	100.00	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3000483386

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3768626346
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2112696640
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.775465164
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.2444924121
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.794787262
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2840379669
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.1749328108
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.96496245
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.2208200805
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.1611417917
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.2445103772
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2873848045
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.3478546208
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3281213653
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.158535438
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3743883153
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.2602218282
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3236921460
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3100358626
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.366544029
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1448153081
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2513543014
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.4127223893
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.2083916793
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.3018485673
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3193411539
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1681337913
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.3999328674
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.332204657
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.3140721693
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2637983832
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2261406768
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.51782800
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1166216200
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2144852989
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.1856614825
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.898434047
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3891514070
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2584831412
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3775122933
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.593542873
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3038676115
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2363868602
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3746340091
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3990720478
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.3760428245
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.2424469222
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.4240039919
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.3119117098
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.945297179
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.3007895152
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2482752460
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3547192147
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3176447064
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3465071167
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3294520846
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4034751246
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.856429704
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2368579191
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1836524892
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3907759663
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3277632635
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2560142600
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4083976278
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3868752705
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2787303740
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1561633825
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3956875974
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2226887152
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.706526856
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3947638238
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1412245072
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2551236573
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1534720334
/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1641337138

Total test records in report: 79

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3768626346	Sep 10 10:36:03 PM UTC 24	Sep 10 10:36:05 PM UTC 24	10701750 ps
T2	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3085197981	Sep 10 10:36:04 PM UTC 24	Sep 10 10:36:06 PM UTC 24	12681102 ps
T3	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2873848045	Sep 10 10:36:04 PM UTC 24	Sep 10 10:36:06 PM UTC 24	11897833 ps
T6	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.3478546208	Sep 10 10:36:05 PM UTC 24	Sep 10 10:36:07 PM UTC 24	11571779 ps
T7	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3743883153	Sep 10 10:36:05 PM UTC 24	Sep 10 10:36:07 PM UTC 24	12148281 ps
T18	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.158535438	Sep 10 10:36:05 PM UTC 24	Sep 10 10:36:07 PM UTC 24	11333639 ps
T19	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3281213653	Sep 10 10:36:05 PM UTC 24	Sep 10 10:36:07 PM UTC 24	11285214 ps
T8	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3100358626	Sep 10 10:36:06 PM UTC 24	Sep 10 10:36:08 PM UTC 24	10625436 ps
T20	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.2602218282	Sep 10 10:36:06 PM UTC 24	Sep 10 10:36:08 PM UTC 24	10917429 ps
T21	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.775465164	Sep 10 10:36:07 PM UTC 24	Sep 10 10:36:08 PM UTC 24	11078808 ps
T15	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3236921460	Sep 10 10:36:06 PM UTC 24	Sep 10 10:36:08 PM UTC 24	11131080 ps
T14	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2112696640	Sep 10 10:36:07 PM UTC 24	Sep 10 10:36:08 PM UTC 24	12002928 ps
T22	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.2444924121	Sep 10 10:36:08 PM UTC 24	Sep 10 10:36:09 PM UTC 24	10541687 ps
T23	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.794787262	Sep 10 10:36:08 PM UTC 24	Sep 10 10:36:09 PM UTC 24	11493482 ps
T9	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2840379669	Sep 10 10:36:08 PM UTC 24	Sep 10 10:36:09 PM UTC 24	12080133 ps
T10	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.2208200805	Sep 10 10:36:08 PM UTC 24	Sep 10 10:36:10 PM UTC 24	10768523 ps
T47	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.96496245	Sep 10 10:36:08 PM UTC 24	Sep 10 10:36:10 PM UTC 24	11660246 ps
T48	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.1749328108	Sep 10 10:36:08 PM UTC 24	Sep 10 10:36:10 PM UTC 24	11116489 ps
T17	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.1611417917	Sep 10 10:36:08 PM UTC 24	Sep 10 10:36:10 PM UTC 24	11793929 ps
T16	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.2445103772	Sep 10 10:36:08 PM UTC 24	Sep 10 10:36:10 PM UTC 24	12642467 ps
T38	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.4024399114	Sep 10 10:36:35 PM UTC 24	Sep 10 10:36:37 PM UTC 24	31116113 ps
T24	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2637983832	Sep 10 10:36:35 PM UTC 24	Sep 10 10:36:37 PM UTC 24	31545181 ps
T39	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.366544029	Sep 10 10:36:35 PM UTC 24	Sep 10 10:36:37 PM UTC 24	31463615 ps
T40	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2261406768	Sep 10 10:36:37 PM UTC 24	Sep 10 10:36:39 PM UTC 24	30099263 ps
T41	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.51782800	Sep 10 10:36:37 PM UTC 24	Sep 10 10:36:39 PM UTC 24	29735854 ps
T42	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1166216200	Sep 10 10:36:37 PM UTC 24	Sep 10 10:36:39 PM UTC 24	28426276 ps
T43	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2144852989	Sep 10 10:36:37 PM UTC 24	Sep 10 10:36:39 PM UTC 24	31204871 ps
T44	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.898434047	Sep 10 10:36:38 PM UTC 24	Sep 10 10:36:40 PM UTC 24	29659249 ps
T45	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.1856614825	Sep 10 10:36:38 PM UTC 24	Sep 10 10:36:40 PM UTC 24	32399492 ps
T46	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1448153081	Sep 10 10:36:39 PM UTC 24	Sep 10 10:36:41 PM UTC 24	29618716 ps
T49	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.2083916793	Sep 10 10:36:40 PM UTC 24	Sep 10 10:36:41 PM UTC 24	30146213 ps
T50	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2513543014	Sep 10 10:36:40 PM UTC 24	Sep 10 10:36:41 PM UTC 24	29550344 ps
T51	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.4127223893	Sep 10 10:36:40 PM UTC 24	Sep 10 10:36:41 PM UTC 24	29851016 ps
T52	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3193411539	Sep 10 10:36:40 PM UTC 24	Sep 10 10:36:41 PM UTC 24	31726308 ps
T53	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.3018485673	Sep 10 10:36:40 PM UTC 24	Sep 10 10:36:41 PM UTC 24	31560654 ps
T54	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1681337913	Sep 10 10:36:40 PM UTC 24	Sep 10 10:36:41 PM UTC 24	30565348 ps
T55	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.3999328674	Sep 10 10:36:41 PM UTC 24	Sep 10 10:36:42 PM UTC 24	29005515 ps
T56	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.332204657	Sep 10 10:36:41 PM UTC 24	Sep 10 10:36:43 PM UTC 24	30346578 ps
T57	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.3140721693	Sep 10 10:36:41 PM UTC 24	Sep 10 10:36:43 PM UTC 24	30380849 ps
T25	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3891514070	Sep 10 10:36:42 PM UTC 24	Sep 10 10:36:44 PM UTC 24	8136978 ps
T26	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2584831412	Sep 10 10:36:42 PM UTC 24	Sep 10 10:36:44 PM UTC 24	9527303 ps
T27	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.945297179	Sep 10 10:36:42 PM UTC 24	Sep 10 10:36:44 PM UTC 24	9073379 ps
T28	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.3007895152	Sep 10 10:36:42 PM UTC 24	Sep 10 10:36:44 PM UTC 24	10589684 ps
T29	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2482752460	Sep 10 10:36:42 PM UTC 24	Sep 10 10:36:44 PM UTC 24	9287949 ps
T30	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3547192147	Sep 10 10:36:42 PM UTC 24	Sep 10 10:36:44 PM UTC 24	10158877 ps
T11	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.828669360	Sep 10 10:36:42 PM UTC 24	Sep 10 10:36:44 PM UTC 24	9676837 ps
T35	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3176447064	Sep 10 10:36:42 PM UTC 24	Sep 10 10:36:44 PM UTC 24	10049931 ps
T36	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3465071167	Sep 10 10:36:43 PM UTC 24	Sep 10 10:36:44 PM UTC 24	9384944 ps
T37	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3294520846	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:45 PM UTC 24	9174590 ps
T58	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3775122933	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:45 PM UTC 24	9712192 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.593542873	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:45 PM UTC 24	9453146 ps
T31	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3038676115	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:45 PM UTC 24	10639348 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3746340091	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:45 PM UTC 24	8977713 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2363868602	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:45 PM UTC 24	9781211 ps
T32	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.3760428245	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:45 PM UTC 24	10759958 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3990720478	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:45 PM UTC 24	10318956 ps
T63	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.4240039919	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:45 PM UTC 24	8816074 ps
T64	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.3119117098	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:46 PM UTC 24	9876335 ps
T65	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.2424469222	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:46 PM UTC 24	8011471 ps
T33	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4034751246	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:46 PM UTC 24	26789982 ps
T34	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.856429704	Sep 10 10:36:44 PM UTC 24	Sep 10 10:36:46 PM UTC 24	27079025 ps
T66	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2226887152	Sep 10 10:36:45 PM UTC 24	Sep 10 10:36:47 PM UTC 24	27613272 ps
T4	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3956875974	Sep 10 10:36:45 PM UTC 24	Sep 10 10:36:47 PM UTC 24	28037246 ps
T67	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.706526856	Sep 10 10:36:45 PM UTC 24	Sep 10 10:36:47 PM UTC 24	26625082 ps
T68	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1412245072	Sep 10 10:36:45 PM UTC 24	Sep 10 10:36:47 PM UTC 24	27845387 ps
T12	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3947638238	Sep 10 10:36:45 PM UTC 24	Sep 10 10:36:47 PM UTC 24	29012778 ps
T69	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2551236573	Sep 10 10:36:45 PM UTC 24	Sep 10 10:36:47 PM UTC 24	27978207 ps
T13	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1534720334	Sep 10 10:36:45 PM UTC 24	Sep 10 10:36:47 PM UTC 24	27425059 ps
T5	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3000483386	Sep 10 10:36:46 PM UTC 24	Sep 10 10:36:47 PM UTC 24	28755468 ps
T70	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1641337138	Sep 10 10:36:45 PM UTC 24	Sep 10 10:36:47 PM UTC 24	27457011 ps
T71	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1836524892	Sep 10 10:36:46 PM UTC 24	Sep 10 10:36:47 PM UTC 24	28754922 ps
T72	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3907759663	Sep 10 10:36:46 PM UTC 24	Sep 10 10:36:47 PM UTC 24	27956666 ps
T73	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2368579191	Sep 10 10:36:45 PM UTC 24	Sep 10 10:36:47 PM UTC 24	24892787 ps
T74	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2560142600	Sep 10 10:36:46 PM UTC 24	Sep 10 10:36:47 PM UTC 24	30515073 ps
T75	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4083976278	Sep 10 10:36:46 PM UTC 24	Sep 10 10:36:47 PM UTC 24	28398802 ps
T76	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3277632635	Sep 10 10:36:46 PM UTC 24	Sep 10 10:36:47 PM UTC 24	26364223 ps
T77	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3868752705	Sep 10 10:36:46 PM UTC 24	Sep 10 10:36:48 PM UTC 24	27121007 ps
T78	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1561633825	Sep 10 10:36:46 PM UTC 24	Sep 10 10:36:48 PM UTC 24	26688863 ps
T79	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2787303740	Sep 10 10:36:46 PM UTC 24	Sep 10 10:36:48 PM UTC 24	27171927 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3085197981
Short name	T2
Test name
Test status
Simulation time	12681102 ps
CPU time	0.6 seconds
Started	Sep 10 10:36:04 PM UTC 24
Finished	Sep 10 10:36:06 PM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085197981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.prim_async_alert.3085197981
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/1.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.828669360
Short name	T11
Test name
Test status
Simulation time	9676837 ps
CPU time	0.5 seconds
Started	Sep 10 10:36:42 PM UTC 24
Finished	Sep 10 10:36:44 PM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828669360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 6.prim_sync_alert.828669360
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/6.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.4024399114
Short name	T38
Test name
Test status
Simulation time	31116113 ps
CPU time	0.55 seconds
Started	Sep 10 10:36:35 PM UTC 24
Finished	Sep 10 10:36:37 PM UTC 24
Peak memory	155076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024399114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 0.prim_async_fatal_alert.4024399114
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3000483386
Short name	T5
Test name
Test status
Simulation time	28755468 ps
CPU time	0.47 seconds
Started	Sep 10 10:36:46 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	153616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000483386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3000483386
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3768626346
Short name	T1
Test name
Test status
Simulation time	10701750 ps
CPU time	0.86 seconds
Started	Sep 10 10:36:03 PM UTC 24
Finished	Sep 10 10:36:05 PM UTC 24
Peak memory	155216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768626346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.prim_async_alert.3768626346
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/0.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2112696640
Short name	T14
Test name
Test status
Simulation time	12002928 ps
CPU time	0.6 seconds
Started	Sep 10 10:36:07 PM UTC 24
Finished	Sep 10 10:36:08 PM UTC 24
Peak memory	155136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112696640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 10.prim_async_alert.2112696640
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/10.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.775465164
Short name	T21
Test name
Test status
Simulation time	11078808 ps
CPU time	0.44 seconds
Started	Sep 10 10:36:07 PM UTC 24
Finished	Sep 10 10:36:08 PM UTC 24
Peak memory	155120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775465164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 11.prim_async_alert.775465164
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/11.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.2444924121
Short name	T22
Test name
Test status
Simulation time	10541687 ps
CPU time	0.51 seconds
Started	Sep 10 10:36:08 PM UTC 24
Finished	Sep 10 10:36:09 PM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444924121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 12.prim_async_alert.2444924121
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/12.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.794787262
Short name	T23
Test name
Test status
Simulation time	11493482 ps
CPU time	0.58 seconds
Started	Sep 10 10:36:08 PM UTC 24
Finished	Sep 10 10:36:09 PM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794787262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 13.prim_async_alert.794787262
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/13.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2840379669
Short name	T9
Test name
Test status
Simulation time	12080133 ps
CPU time	0.61 seconds
Started	Sep 10 10:36:08 PM UTC 24
Finished	Sep 10 10:36:09 PM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840379669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.2840379669
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/14.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.1749328108
Short name	T48
Test name
Test status
Simulation time	11116489 ps
CPU time	0.63 seconds
Started	Sep 10 10:36:08 PM UTC 24
Finished	Sep 10 10:36:10 PM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749328108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.1749328108
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/15.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.96496245
Short name	T47
Test name
Test status
Simulation time	11660246 ps
CPU time	0.61 seconds
Started	Sep 10 10:36:08 PM UTC 24
Finished	Sep 10 10:36:10 PM UTC 24
Peak memory	155160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96496245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 16.prim_async_alert.96496245
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/16.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.2208200805
Short name	T10
Test name
Test status
Simulation time	10768523 ps
CPU time	0.58 seconds
Started	Sep 10 10:36:08 PM UTC 24
Finished	Sep 10 10:36:10 PM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208200805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.2208200805
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/17.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.1611417917
Short name	T17
Test name
Test status
Simulation time	11793929 ps
CPU time	0.59 seconds
Started	Sep 10 10:36:08 PM UTC 24
Finished	Sep 10 10:36:10 PM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611417917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.prim_async_alert.1611417917
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/18.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.2445103772
Short name	T16
Test name
Test status
Simulation time	12642467 ps
CPU time	0.62 seconds
Started	Sep 10 10:36:08 PM UTC 24
Finished	Sep 10 10:36:10 PM UTC 24
Peak memory	155148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445103772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 19.prim_async_alert.2445103772
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/19.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2873848045
Short name	T3
Test name
Test status
Simulation time	11897833 ps
CPU time	0.58 seconds
Started	Sep 10 10:36:04 PM UTC 24
Finished	Sep 10 10:36:06 PM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873848045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.prim_async_alert.2873848045
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/2.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.3478546208
Short name	T6
Test name
Test status
Simulation time	11571779 ps
CPU time	0.6 seconds
Started	Sep 10 10:36:05 PM UTC 24
Finished	Sep 10 10:36:07 PM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478546208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 3.prim_async_alert.3478546208
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/3.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3281213653
Short name	T19
Test name
Test status
Simulation time	11285214 ps
CPU time	0.61 seconds
Started	Sep 10 10:36:05 PM UTC 24
Finished	Sep 10 10:36:07 PM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281213653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 4.prim_async_alert.3281213653
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/4.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.158535438
Short name	T18
Test name
Test status
Simulation time	11333639 ps
CPU time	0.59 seconds
Started	Sep 10 10:36:05 PM UTC 24
Finished	Sep 10 10:36:07 PM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158535438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 5.prim_async_alert.158535438
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/5.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3743883153
Short name	T7
Test name
Test status
Simulation time	12148281 ps
CPU time	0.51 seconds
Started	Sep 10 10:36:05 PM UTC 24
Finished	Sep 10 10:36:07 PM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743883153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.prim_async_alert.3743883153
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/6.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.2602218282
Short name	T20
Test name
Test status
Simulation time	10917429 ps
CPU time	0.61 seconds
Started	Sep 10 10:36:06 PM UTC 24
Finished	Sep 10 10:36:08 PM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602218282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 7.prim_async_alert.2602218282
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/7.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3236921460
Short name	T15
Test name
Test status
Simulation time	11131080 ps
CPU time	0.61 seconds
Started	Sep 10 10:36:06 PM UTC 24
Finished	Sep 10 10:36:08 PM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236921460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.prim_async_alert.3236921460
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/8.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3100358626
Short name	T8
Test name
Test status
Simulation time	10625436 ps
CPU time	0.48 seconds
Started	Sep 10 10:36:06 PM UTC 24
Finished	Sep 10 10:36:08 PM UTC 24
Peak memory	155148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100358626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.3100358626
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/9.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.366544029
Short name	T39
Test name
Test status
Simulation time	31463615 ps
CPU time	0.56 seconds
Started	Sep 10 10:36:35 PM UTC 24
Finished	Sep 10 10:36:37 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366544029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 1.prim_async_fatal_alert.366544029
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1448153081
Short name	T46
Test name
Test status
Simulation time	29618716 ps
CPU time	0.58 seconds
Started	Sep 10 10:36:39 PM UTC 24
Finished	Sep 10 10:36:41 PM UTC 24
Peak memory	154952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448153081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.1448153081
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2513543014
Short name	T50
Test name
Test status
Simulation time	29550344 ps
CPU time	0.54 seconds
Started	Sep 10 10:36:40 PM UTC 24
Finished	Sep 10 10:36:41 PM UTC 24
Peak memory	154968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513543014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.2513543014
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.4127223893
Short name	T51
Test name
Test status
Simulation time	29851016 ps
CPU time	0.53 seconds
Started	Sep 10 10:36:40 PM UTC 24
Finished	Sep 10 10:36:41 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127223893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 12.prim_async_fatal_alert.4127223893
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.2083916793
Short name	T49
Test name
Test status
Simulation time	30146213 ps
CPU time	0.54 seconds
Started	Sep 10 10:36:40 PM UTC 24
Finished	Sep 10 10:36:41 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083916793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 13.prim_async_fatal_alert.2083916793
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.3018485673
Short name	T53
Test name
Test status
Simulation time	31560654 ps
CPU time	0.54 seconds
Started	Sep 10 10:36:40 PM UTC 24
Finished	Sep 10 10:36:41 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018485673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 14.prim_async_fatal_alert.3018485673
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3193411539
Short name	T52
Test name
Test status
Simulation time	31726308 ps
CPU time	0.55 seconds
Started	Sep 10 10:36:40 PM UTC 24
Finished	Sep 10 10:36:41 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193411539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.3193411539
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1681337913
Short name	T54
Test name
Test status
Simulation time	30565348 ps
CPU time	0.53 seconds
Started	Sep 10 10:36:40 PM UTC 24
Finished	Sep 10 10:36:41 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681337913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 16.prim_async_fatal_alert.1681337913
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.3999328674
Short name	T55
Test name
Test status
Simulation time	29005515 ps
CPU time	0.5 seconds
Started	Sep 10 10:36:41 PM UTC 24
Finished	Sep 10 10:36:42 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999328674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 17.prim_async_fatal_alert.3999328674
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.332204657
Short name	T56
Test name
Test status
Simulation time	30346578 ps
CPU time	0.57 seconds
Started	Sep 10 10:36:41 PM UTC 24
Finished	Sep 10 10:36:43 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332204657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 18.prim_async_fatal_alert.332204657
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.3140721693
Short name	T57
Test name
Test status
Simulation time	30380849 ps
CPU time	0.52 seconds
Started	Sep 10 10:36:41 PM UTC 24
Finished	Sep 10 10:36:43 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140721693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 19.prim_async_fatal_alert.3140721693
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2637983832
Short name	T24
Test name
Test status
Simulation time	31545181 ps
CPU time	0.54 seconds
Started	Sep 10 10:36:35 PM UTC 24
Finished	Sep 10 10:36:37 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637983832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.2637983832
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2261406768
Short name	T40
Test name
Test status
Simulation time	30099263 ps
CPU time	0.55 seconds
Started	Sep 10 10:36:37 PM UTC 24
Finished	Sep 10 10:36:39 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261406768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 3.prim_async_fatal_alert.2261406768
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.51782800
Short name	T41
Test name
Test status
Simulation time	29735854 ps
CPU time	0.53 seconds
Started	Sep 10 10:36:37 PM UTC 24
Finished	Sep 10 10:36:39 PM UTC 24
Peak memory	155008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51782800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 4.prim_async_fatal_alert.51782800
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1166216200
Short name	T42
Test name
Test status
Simulation time	28426276 ps
CPU time	0.57 seconds
Started	Sep 10 10:36:37 PM UTC 24
Finished	Sep 10 10:36:39 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166216200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 5.prim_async_fatal_alert.1166216200
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2144852989
Short name	T43
Test name
Test status
Simulation time	31204871 ps
CPU time	0.52 seconds
Started	Sep 10 10:36:37 PM UTC 24
Finished	Sep 10 10:36:39 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144852989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 6.prim_async_fatal_alert.2144852989
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.1856614825
Short name	T45
Test name
Test status
Simulation time	32399492 ps
CPU time	0.62 seconds
Started	Sep 10 10:36:38 PM UTC 24
Finished	Sep 10 10:36:40 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856614825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 8.prim_async_fatal_alert.1856614825
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.898434047
Short name	T44
Test name
Test status
Simulation time	29659249 ps
CPU time	0.54 seconds
Started	Sep 10 10:36:38 PM UTC 24
Finished	Sep 10 10:36:40 PM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898434047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 9.prim_async_fatal_alert.898434047
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3891514070
Short name	T25
Test name
Test status
Simulation time	8136978 ps
CPU time	0.51 seconds
Started	Sep 10 10:36:42 PM UTC 24
Finished	Sep 10 10:36:44 PM UTC 24
Peak memory	154604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891514070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.3891514070
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/0.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2584831412
Short name	T26
Test name
Test status
Simulation time	9527303 ps
CPU time	0.49 seconds
Started	Sep 10 10:36:42 PM UTC 24
Finished	Sep 10 10:36:44 PM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584831412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 1.prim_sync_alert.2584831412
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/1.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3775122933
Short name	T58
Test name
Test status
Simulation time	9712192 ps
CPU time	0.43 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:45 PM UTC 24
Peak memory	154500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775122933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.3775122933
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/10.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.593542873
Short name	T59
Test name
Test status
Simulation time	9453146 ps
CPU time	0.46 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:45 PM UTC 24
Peak memory	154544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593542873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 11.prim_sync_alert.593542873
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/11.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3038676115
Short name	T31
Test name
Test status
Simulation time	10639348 ps
CPU time	0.44 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:45 PM UTC 24
Peak memory	154536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038676115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.3038676115
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/12.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2363868602
Short name	T61
Test name
Test status
Simulation time	9781211 ps
CPU time	0.45 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:45 PM UTC 24
Peak memory	154528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363868602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 13.prim_sync_alert.2363868602
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/13.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3746340091
Short name	T60
Test name
Test status
Simulation time	8977713 ps
CPU time	0.44 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:45 PM UTC 24
Peak memory	154536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746340091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.3746340091
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/14.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3990720478
Short name	T62
Test name
Test status
Simulation time	10318956 ps
CPU time	0.45 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:45 PM UTC 24
Peak memory	154536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990720478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.3990720478
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/15.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.3760428245
Short name	T32
Test name
Test status
Simulation time	10759958 ps
CPU time	0.44 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:45 PM UTC 24
Peak memory	154528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760428245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 16.prim_sync_alert.3760428245
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/16.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.2424469222
Short name	T65
Test name
Test status
Simulation time	8011471 ps
CPU time	0.55 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:46 PM UTC 24
Peak memory	154536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424469222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 17.prim_sync_alert.2424469222
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/17.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.4240039919
Short name	T63
Test name
Test status
Simulation time	8816074 ps
CPU time	0.42 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:45 PM UTC 24
Peak memory	154536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240039919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 18.prim_sync_alert.4240039919
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/18.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.3119117098
Short name	T64
Test name
Test status
Simulation time	9876335 ps
CPU time	0.42 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:46 PM UTC 24
Peak memory	154536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119117098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 19.prim_sync_alert.3119117098
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/19.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.945297179
Short name	T27
Test name
Test status
Simulation time	9073379 ps
CPU time	0.47 seconds
Started	Sep 10 10:36:42 PM UTC 24
Finished	Sep 10 10:36:44 PM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945297179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 2.prim_sync_alert.945297179
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/2.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.3007895152
Short name	T28
Test name
Test status
Simulation time	10589684 ps
CPU time	0.51 seconds
Started	Sep 10 10:36:42 PM UTC 24
Finished	Sep 10 10:36:44 PM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007895152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 3.prim_sync_alert.3007895152
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/3.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2482752460
Short name	T29
Test name
Test status
Simulation time	9287949 ps
CPU time	0.57 seconds
Started	Sep 10 10:36:42 PM UTC 24
Finished	Sep 10 10:36:44 PM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482752460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.2482752460
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/4.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3547192147
Short name	T30
Test name
Test status
Simulation time	10158877 ps
CPU time	0.45 seconds
Started	Sep 10 10:36:42 PM UTC 24
Finished	Sep 10 10:36:44 PM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547192147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 5.prim_sync_alert.3547192147
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/5.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3176447064
Short name	T35
Test name
Test status
Simulation time	10049931 ps
CPU time	0.46 seconds
Started	Sep 10 10:36:42 PM UTC 24
Finished	Sep 10 10:36:44 PM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176447064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.3176447064
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/7.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3465071167
Short name	T36
Test name
Test status
Simulation time	9384944 ps
CPU time	0.51 seconds
Started	Sep 10 10:36:43 PM UTC 24
Finished	Sep 10 10:36:44 PM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465071167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.3465071167
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/8.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3294520846
Short name	T37
Test name
Test status
Simulation time	9174590 ps
CPU time	0.46 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:45 PM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294520846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.3294520846
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/9.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4034751246
Short name	T33
Test name
Test status
Simulation time	26789982 ps
CPU time	0.44 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:46 PM UTC 24
Peak memory	154240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034751246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4034751246
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.856429704
Short name	T34
Test name
Test status
Simulation time	27079025 ps
CPU time	0.4 seconds
Started	Sep 10 10:36:44 PM UTC 24
Finished	Sep 10 10:36:46 PM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856429704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.856429704
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2368579191
Short name	T73
Test name
Test status
Simulation time	24892787 ps
CPU time	0.49 seconds
Started	Sep 10 10:36:45 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368579191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2368579191
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1836524892
Short name	T71
Test name
Test status
Simulation time	28754922 ps
CPU time	0.45 seconds
Started	Sep 10 10:36:46 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836524892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1836524892
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3907759663
Short name	T72
Test name
Test status
Simulation time	27956666 ps
CPU time	0.44 seconds
Started	Sep 10 10:36:46 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907759663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3907759663
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3277632635
Short name	T76
Test name
Test status
Simulation time	26364223 ps
CPU time	0.49 seconds
Started	Sep 10 10:36:46 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277632635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3277632635
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2560142600
Short name	T74
Test name
Test status
Simulation time	30515073 ps
CPU time	0.46 seconds
Started	Sep 10 10:36:46 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560142600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2560142600
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4083976278
Short name	T75
Test name
Test status
Simulation time	28398802 ps
CPU time	0.41 seconds
Started	Sep 10 10:36:46 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083976278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.4083976278
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3868752705
Short name	T77
Test name
Test status
Simulation time	27121007 ps
CPU time	0.45 seconds
Started	Sep 10 10:36:46 PM UTC 24
Finished	Sep 10 10:36:48 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868752705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3868752705
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2787303740
Short name	T79
Test name
Test status
Simulation time	27171927 ps
CPU time	0.38 seconds
Started	Sep 10 10:36:46 PM UTC 24
Finished	Sep 10 10:36:48 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787303740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2787303740
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1561633825
Short name	T78
Test name
Test status
Simulation time	26688863 ps
CPU time	0.37 seconds
Started	Sep 10 10:36:46 PM UTC 24
Finished	Sep 10 10:36:48 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561633825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1561633825
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3956875974
Short name	T4
Test name
Test status
Simulation time	28037246 ps
CPU time	0.45 seconds
Started	Sep 10 10:36:45 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	153944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956875974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3956875974
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2226887152
Short name	T66
Test name
Test status
Simulation time	27613272 ps
CPU time	0.4 seconds
Started	Sep 10 10:36:45 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226887152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2226887152
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.706526856
Short name	T67
Test name
Test status
Simulation time	26625082 ps
CPU time	0.41 seconds
Started	Sep 10 10:36:45 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706526856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.706526856
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.3947638238
Short name	T12
Test name
Test status
Simulation time	29012778 ps
CPU time	0.46 seconds
Started	Sep 10 10:36:45 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947638238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.3947638238
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1412245072
Short name	T68
Test name
Test status
Simulation time	27845387 ps
CPU time	0.47 seconds
Started	Sep 10 10:36:45 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412245072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1412245072
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2551236573
Short name	T69
Test name
Test status
Simulation time	27978207 ps
CPU time	0.43 seconds
Started	Sep 10 10:36:45 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	153556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551236573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2551236573
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1534720334
Short name	T13
Test name
Test status
Simulation time	27425059 ps
CPU time	0.46 seconds
Started	Sep 10 10:36:45 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534720334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1534720334
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1641337138
Short name	T70
Test name
Test status
Simulation time	27457011 ps
CPU time	0.45 seconds
Started	Sep 10 10:36:45 PM UTC 24
Finished	Sep 10 10:36:47 PM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641337138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1641337138
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest