Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.85	100.00	97.92	100.00	89.29	95.83	86.05

Total tests in report: 78

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
88.28	88.28	100.00	100.00	93.75	93.75	96.43	96.43	78.57	78.57	95.83	95.83	65.12	65.12	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1163337129
91.41	3.13	100.00	0.00	93.75	0.00	96.43	0.00	85.71	7.14	95.83	0.00	76.74	11.63	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.2785801256
94.11	2.70	100.00	0.00	95.83	2.08	100.00	3.57	89.29	3.57	95.83	0.00	83.72	6.98	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.758165291
94.50	0.39	100.00	0.00	95.83	0.00	100.00	0.00	89.29	0.00	95.83	0.00	86.05	2.33	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.827951274
94.85	0.35	100.00	0.00	97.92	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2462216026

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.773270872
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.1624210317
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1830592086
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3537244972
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.865418421
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.4289152484
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2894156408
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.2131437960
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1114830247
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.3511946253
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.4162312581
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.21061486
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.343918129
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1370940555
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2830261188
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3211831435
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.2872173872
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3829612117
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3470240751
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.64311155
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.1497159827
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.2303551297
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2459936141
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2820694336
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1252150196
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2296192479
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.1633161850
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.1185258548
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3709568262
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2188391317
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1234518565
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.231050453
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3627516060
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3992256445
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.48363371
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1552839949
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.23065271
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3307585500
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2268230875
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3053423176
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2781634588
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2869712518
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3296502065
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.330260890
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1890311063
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2313009436
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.2141749826
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.375635099
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.436136632
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.1430384505
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.1605782163
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3661327040
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3685611275
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.476888298
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.913354648
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2002382903
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.59024130
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1407772900
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1754262043
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3395913069
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3059563035
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.791872802
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1332345084
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1724522111
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.467635222
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.567646247
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.407669607
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3598118824
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2938076481
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3480365961
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2132650124
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1964410463
/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2548980372

Total test records in report: 78

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.343918129	Sep 18 03:35:59 AM UTC 24	Sep 18 03:36:00 AM UTC 24	11159999 ps
T2	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2830261188	Sep 18 03:35:59 AM UTC 24	Sep 18 03:36:00 AM UTC 24	10996054 ps
T3	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.21061486	Sep 18 03:35:59 AM UTC 24	Sep 18 03:36:00 AM UTC 24	11278530 ps
T6	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1370940555	Sep 18 03:35:59 AM UTC 24	Sep 18 03:36:00 AM UTC 24	11191637 ps
T7	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.773270872	Sep 18 03:35:59 AM UTC 24	Sep 18 03:36:00 AM UTC 24	11054786 ps
T8	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.827951274	Sep 18 03:35:59 AM UTC 24	Sep 18 03:36:00 AM UTC 24	11397353 ps
T15	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1163337129	Sep 18 03:36:00 AM UTC 24	Sep 18 03:36:01 AM UTC 24	11685367 ps
T17	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3211831435	Sep 18 03:36:00 AM UTC 24	Sep 18 03:36:01 AM UTC 24	11917721 ps
T18	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.2872173872	Sep 18 03:36:00 AM UTC 24	Sep 18 03:36:01 AM UTC 24	10206740 ps
T19	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1830592086	Sep 18 03:36:00 AM UTC 24	Sep 18 03:36:01 AM UTC 24	11068452 ps
T20	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.1624210317	Sep 18 03:36:00 AM UTC 24	Sep 18 03:36:01 AM UTC 24	12034940 ps
T45	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3537244972	Sep 18 03:36:00 AM UTC 24	Sep 18 03:36:01 AM UTC 24	10683986 ps
T39	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.4289152484	Sep 18 03:36:00 AM UTC 24	Sep 18 03:36:01 AM UTC 24	11740961 ps
T9	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.865418421	Sep 18 03:36:00 AM UTC 24	Sep 18 03:36:01 AM UTC 24	12308294 ps
T16	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2894156408	Sep 18 03:36:00 AM UTC 24	Sep 18 03:36:01 AM UTC 24	11193911 ps
T21	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1114830247	Sep 18 03:36:01 AM UTC 24	Sep 18 03:36:02 AM UTC 24	11102226 ps
T46	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.2131437960	Sep 18 03:36:01 AM UTC 24	Sep 18 03:36:02 AM UTC 24	10754441 ps
T47	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.3511946253	Sep 18 03:36:01 AM UTC 24	Sep 18 03:36:02 AM UTC 24	11171906 ps
T13	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.4162312581	Sep 18 03:36:01 AM UTC 24	Sep 18 03:36:02 AM UTC 24	10974440 ps
T10	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3829612117	Sep 18 01:19:49 AM UTC 24	Sep 18 01:19:50 AM UTC 24	27910396 ps
T11	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3709568262	Sep 18 01:19:50 AM UTC 24	Sep 18 01:19:51 AM UTC 24	29158237 ps
T40	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2188391317	Sep 18 01:19:50 AM UTC 24	Sep 18 01:19:51 AM UTC 24	29646245 ps
T22	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1234518565	Sep 18 01:19:51 AM UTC 24	Sep 18 01:19:53 AM UTC 24	28928058 ps
T12	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.758165291	Sep 18 01:19:51 AM UTC 24	Sep 18 01:19:53 AM UTC 24	30440428 ps
T41	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.231050453	Sep 18 01:19:51 AM UTC 24	Sep 18 01:19:53 AM UTC 24	31835866 ps
T14	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3992256445	Sep 18 01:19:52 AM UTC 24	Sep 18 01:19:54 AM UTC 24	31358032 ps
T42	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3627516060	Sep 18 01:19:52 AM UTC 24	Sep 18 01:19:54 AM UTC 24	29661511 ps
T43	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3470240751	Sep 18 01:19:52 AM UTC 24	Sep 18 01:19:54 AM UTC 24	31764899 ps
T44	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.48363371	Sep 18 01:19:52 AM UTC 24	Sep 18 01:19:54 AM UTC 24	30011434 ps
T48	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.64311155	Sep 18 01:19:52 AM UTC 24	Sep 18 01:19:54 AM UTC 24	28765893 ps
T49	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.1497159827	Sep 18 01:19:53 AM UTC 24	Sep 18 01:19:54 AM UTC 24	30391731 ps
T50	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2459936141	Sep 18 01:19:53 AM UTC 24	Sep 18 01:19:54 AM UTC 24	30649182 ps
T51	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.2303551297	Sep 18 01:19:53 AM UTC 24	Sep 18 01:19:54 AM UTC 24	29983504 ps
T52	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2820694336	Sep 18 01:19:53 AM UTC 24	Sep 18 01:19:54 AM UTC 24	29446933 ps
T53	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1252150196	Sep 18 01:19:53 AM UTC 24	Sep 18 01:19:54 AM UTC 24	30072676 ps
T54	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2296192479	Sep 18 01:19:53 AM UTC 24	Sep 18 01:19:54 AM UTC 24	29377303 ps
T55	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.1633161850	Sep 18 01:19:53 AM UTC 24	Sep 18 01:19:54 AM UTC 24	29968301 ps
T56	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.1185258548	Sep 18 01:19:53 AM UTC 24	Sep 18 01:19:54 AM UTC 24	29014558 ps
T32	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1552839949	Sep 18 01:19:54 AM UTC 24	Sep 18 01:19:55 AM UTC 24	8237153 ps
T23	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.23065271	Sep 18 01:19:55 AM UTC 24	Sep 18 01:19:56 AM UTC 24	9371538 ps
T33	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.375635099	Sep 18 01:19:55 AM UTC 24	Sep 18 01:19:56 AM UTC 24	8988018 ps
T34	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.1430384505	Sep 18 01:19:55 AM UTC 24	Sep 18 01:19:56 AM UTC 24	8611063 ps
T35	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.2785801256	Sep 18 01:19:55 AM UTC 24	Sep 18 01:19:57 AM UTC 24	9841889 ps
T36	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.436136632	Sep 18 01:19:55 AM UTC 24	Sep 18 01:19:57 AM UTC 24	8620095 ps
T37	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.1605782163	Sep 18 01:19:55 AM UTC 24	Sep 18 01:19:57 AM UTC 24	7709685 ps
T24	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3685611275	Sep 18 01:19:55 AM UTC 24	Sep 18 01:19:57 AM UTC 24	9349142 ps
T25	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3661327040	Sep 18 01:19:55 AM UTC 24	Sep 18 01:19:57 AM UTC 24	8935336 ps
T38	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.476888298	Sep 18 01:19:55 AM UTC 24	Sep 18 01:19:57 AM UTC 24	8217743 ps
T57	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3307585500	Sep 18 01:19:55 AM UTC 24	Sep 18 01:19:57 AM UTC 24	9106012 ps
T26	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2869712518	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	10029787 ps
T58	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2268230875	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	8191970 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3053423176	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	9204684 ps
T27	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2781634588	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	8228520 ps
T28	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3296502065	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	8406606 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.330260890	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	9249006 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.2141749826	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	9355030 ps
T29	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2313009436	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	8645512 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1890311063	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	10062860 ps
T30	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.567646247	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	28387730 ps
T31	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.913354648	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	26442576 ps
T63	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2002382903	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:58 AM UTC 24	26793025 ps
T64	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.407669607	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:59 AM UTC 24	27836154 ps
T65	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3480365961	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:59 AM UTC 24	26765240 ps
T66	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2132650124	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:59 AM UTC 24	27594709 ps
T67	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2938076481	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:59 AM UTC 24	28320079 ps
T4	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3598118824	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:59 AM UTC 24	27572212 ps
T68	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1964410463	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:59 AM UTC 24	28511941 ps
T69	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.59024130	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:59 AM UTC 24	28565556 ps
T70	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2548980372	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:59 AM UTC 24	26361617 ps
T71	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1407772900	Sep 18 01:19:57 AM UTC 24	Sep 18 01:19:59 AM UTC 24	26987400 ps
T72	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3395913069	Sep 18 01:19:58 AM UTC 24	Sep 18 01:20:00 AM UTC 24	28122678 ps
T73	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1754262043	Sep 18 01:19:58 AM UTC 24	Sep 18 01:20:00 AM UTC 24	26772309 ps
T74	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3059563035	Sep 18 01:20:00 AM UTC 24	Sep 18 01:20:01 AM UTC 24	28091302 ps
T75	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.791872802	Sep 18 01:20:00 AM UTC 24	Sep 18 01:20:01 AM UTC 24	27896811 ps
T76	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1332345084	Sep 18 01:20:00 AM UTC 24	Sep 18 01:20:01 AM UTC 24	29296392 ps
T77	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1724522111	Sep 18 01:20:00 AM UTC 24	Sep 18 01:20:01 AM UTC 24	27578743 ps
T5	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2462216026	Sep 18 01:20:00 AM UTC 24	Sep 18 01:20:01 AM UTC 24	28860243 ps
T78	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.467635222	Sep 18 01:20:00 AM UTC 24	Sep 18 01:20:01 AM UTC 24	27752339 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1163337129
Short name	T15
Test name
Test status
Simulation time	11685367 ps
CPU time	0.34 seconds
Started	Sep 18 03:36:00 AM UTC 24
Finished	Sep 18 03:36:01 AM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163337129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 7.prim_async_alert.1163337129
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/7.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.2785801256
Short name	T35
Test name
Test status
Simulation time	9841889 ps
CPU time	0.35 seconds
Started	Sep 18 01:19:55 AM UTC 24
Finished	Sep 18 01:19:57 AM UTC 24
Peak memory	154544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785801256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 5.prim_sync_alert.2785801256
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/5.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.758165291
Short name	T12
Test name
Test status
Simulation time	30440428 ps
CPU time	0.54 seconds
Started	Sep 18 01:19:51 AM UTC 24
Finished	Sep 18 01:19:53 AM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758165291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 6.prim_async_fatal_alert.758165291
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.827951274
Short name	T8
Test name
Test status
Simulation time	11397353 ps
CPU time	0.41 seconds
Started	Sep 18 03:35:59 AM UTC 24
Finished	Sep 18 03:36:00 AM UTC 24
Peak memory	153228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827951274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.prim_async_alert.827951274
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/1.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.2462216026
Short name	T5
Test name
Test status
Simulation time	28860243 ps
CPU time	0.41 seconds
Started	Sep 18 01:20:00 AM UTC 24
Finished	Sep 18 01:20:01 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462216026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.2462216026
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.773270872
Short name	T7
Test name
Test status
Simulation time	11054786 ps
CPU time	0.56 seconds
Started	Sep 18 03:35:59 AM UTC 24
Finished	Sep 18 03:36:00 AM UTC 24
Peak memory	154596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773270872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.prim_async_alert.773270872
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/0.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.1624210317
Short name	T20
Test name
Test status
Simulation time	12034940 ps
CPU time	0.35 seconds
Started	Sep 18 03:36:00 AM UTC 24
Finished	Sep 18 03:36:01 AM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624210317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 10.prim_async_alert.1624210317
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/10.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1830592086
Short name	T19
Test name
Test status
Simulation time	11068452 ps
CPU time	0.34 seconds
Started	Sep 18 03:36:00 AM UTC 24
Finished	Sep 18 03:36:01 AM UTC 24
Peak memory	155048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830592086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 11.prim_async_alert.1830592086
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/11.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3537244972
Short name	T45
Test name
Test status
Simulation time	10683986 ps
CPU time	0.34 seconds
Started	Sep 18 03:36:00 AM UTC 24
Finished	Sep 18 03:36:01 AM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537244972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 12.prim_async_alert.3537244972
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/12.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.865418421
Short name	T9
Test name
Test status
Simulation time	12308294 ps
CPU time	0.35 seconds
Started	Sep 18 03:36:00 AM UTC 24
Finished	Sep 18 03:36:01 AM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865418421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 13.prim_async_alert.865418421
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/13.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.4289152484
Short name	T39
Test name
Test status
Simulation time	11740961 ps
CPU time	0.34 seconds
Started	Sep 18 03:36:00 AM UTC 24
Finished	Sep 18 03:36:01 AM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289152484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.4289152484
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/14.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2894156408
Short name	T16
Test name
Test status
Simulation time	11193911 ps
CPU time	0.36 seconds
Started	Sep 18 03:36:00 AM UTC 24
Finished	Sep 18 03:36:01 AM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894156408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.2894156408
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/15.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.2131437960
Short name	T46
Test name
Test status
Simulation time	10754441 ps
CPU time	0.38 seconds
Started	Sep 18 03:36:01 AM UTC 24
Finished	Sep 18 03:36:02 AM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131437960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 16.prim_async_alert.2131437960
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/16.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1114830247
Short name	T21
Test name
Test status
Simulation time	11102226 ps
CPU time	0.35 seconds
Started	Sep 18 03:36:01 AM UTC 24
Finished	Sep 18 03:36:02 AM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114830247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.1114830247
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/17.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.3511946253
Short name	T47
Test name
Test status
Simulation time	11171906 ps
CPU time	0.38 seconds
Started	Sep 18 03:36:01 AM UTC 24
Finished	Sep 18 03:36:02 AM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511946253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.prim_async_alert.3511946253
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/18.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.4162312581
Short name	T13
Test name
Test status
Simulation time	10974440 ps
CPU time	0.35 seconds
Started	Sep 18 03:36:01 AM UTC 24
Finished	Sep 18 03:36:02 AM UTC 24
Peak memory	155156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162312581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 19.prim_async_alert.4162312581
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/19.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.21061486
Short name	T3
Test name
Test status
Simulation time	11278530 ps
CPU time	0.38 seconds
Started	Sep 18 03:35:59 AM UTC 24
Finished	Sep 18 03:36:00 AM UTC 24
Peak memory	154088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21061486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.prim_async_alert.21061486
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/2.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.343918129
Short name	T1
Test name
Test status
Simulation time	11159999 ps
CPU time	0.44 seconds
Started	Sep 18 03:35:59 AM UTC 24
Finished	Sep 18 03:36:00 AM UTC 24
Peak memory	153820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343918129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 3.prim_async_alert.343918129
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/3.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1370940555
Short name	T6
Test name
Test status
Simulation time	11191637 ps
CPU time	0.44 seconds
Started	Sep 18 03:35:59 AM UTC 24
Finished	Sep 18 03:36:00 AM UTC 24
Peak memory	155100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370940555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 5.prim_async_alert.1370940555
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/5.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2830261188
Short name	T2
Test name
Test status
Simulation time	10996054 ps
CPU time	0.39 seconds
Started	Sep 18 03:35:59 AM UTC 24
Finished	Sep 18 03:36:00 AM UTC 24
Peak memory	154420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830261188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.prim_async_alert.2830261188
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/6.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3211831435
Short name	T17
Test name
Test status
Simulation time	11917721 ps
CPU time	0.33 seconds
Started	Sep 18 03:36:00 AM UTC 24
Finished	Sep 18 03:36:01 AM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211831435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.prim_async_alert.3211831435
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/8.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.2872173872
Short name	T18
Test name
Test status
Simulation time	10206740 ps
CPU time	0.32 seconds
Started	Sep 18 03:36:00 AM UTC 24
Finished	Sep 18 03:36:01 AM UTC 24
Peak memory	155152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872173872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.2872173872
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/9.prim_async_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3829612117
Short name	T10
Test name
Test status
Simulation time	27910396 ps
CPU time	0.62 seconds
Started	Sep 18 01:19:49 AM UTC 24
Finished	Sep 18 01:19:50 AM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829612117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.3829612117
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.3470240751
Short name	T43
Test name
Test status
Simulation time	31764899 ps
CPU time	0.44 seconds
Started	Sep 18 01:19:52 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470240751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.3470240751
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.64311155
Short name	T48
Test name
Test status
Simulation time	28765893 ps
CPU time	0.49 seconds
Started	Sep 18 01:19:52 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64311155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 11.prim_async_fatal_alert.64311155
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.1497159827
Short name	T49
Test name
Test status
Simulation time	30391731 ps
CPU time	0.45 seconds
Started	Sep 18 01:19:53 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497159827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 12.prim_async_fatal_alert.1497159827
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.2303551297
Short name	T51
Test name
Test status
Simulation time	29983504 ps
CPU time	0.57 seconds
Started	Sep 18 01:19:53 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303551297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 13.prim_async_fatal_alert.2303551297
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2459936141
Short name	T50
Test name
Test status
Simulation time	30649182 ps
CPU time	0.49 seconds
Started	Sep 18 01:19:53 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459936141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 14.prim_async_fatal_alert.2459936141
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2820694336
Short name	T52
Test name
Test status
Simulation time	29446933 ps
CPU time	0.47 seconds
Started	Sep 18 01:19:53 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820694336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.2820694336
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1252150196
Short name	T53
Test name
Test status
Simulation time	30072676 ps
CPU time	0.63 seconds
Started	Sep 18 01:19:53 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252150196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 16.prim_async_fatal_alert.1252150196
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2296192479
Short name	T54
Test name
Test status
Simulation time	29377303 ps
CPU time	0.55 seconds
Started	Sep 18 01:19:53 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296192479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 17.prim_async_fatal_alert.2296192479
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.1633161850
Short name	T55
Test name
Test status
Simulation time	29968301 ps
CPU time	0.6 seconds
Started	Sep 18 01:19:53 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633161850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 18.prim_async_fatal_alert.1633161850
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.1185258548
Short name	T56
Test name
Test status
Simulation time	29014558 ps
CPU time	0.59 seconds
Started	Sep 18 01:19:53 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185258548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 19.prim_async_fatal_alert.1185258548
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3709568262
Short name	T11
Test name
Test status
Simulation time	29158237 ps
CPU time	0.56 seconds
Started	Sep 18 01:19:50 AM UTC 24
Finished	Sep 18 01:19:51 AM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709568262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.3709568262
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2188391317
Short name	T40
Test name
Test status
Simulation time	29646245 ps
CPU time	0.61 seconds
Started	Sep 18 01:19:50 AM UTC 24
Finished	Sep 18 01:19:51 AM UTC 24
Peak memory	155008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188391317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 3.prim_async_fatal_alert.2188391317
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1234518565
Short name	T22
Test name
Test status
Simulation time	28928058 ps
CPU time	0.56 seconds
Started	Sep 18 01:19:51 AM UTC 24
Finished	Sep 18 01:19:53 AM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234518565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 4.prim_async_fatal_alert.1234518565
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.231050453
Short name	T41
Test name
Test status
Simulation time	31835866 ps
CPU time	0.64 seconds
Started	Sep 18 01:19:51 AM UTC 24
Finished	Sep 18 01:19:53 AM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231050453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 5.prim_async_fatal_alert.231050453
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3627516060
Short name	T42
Test name
Test status
Simulation time	29661511 ps
CPU time	0.51 seconds
Started	Sep 18 01:19:52 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627516060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 7.prim_async_fatal_alert.3627516060
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3992256445
Short name	T14
Test name
Test status
Simulation time	31358032 ps
CPU time	0.49 seconds
Started	Sep 18 01:19:52 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992256445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 8.prim_async_fatal_alert.3992256445
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.48363371
Short name	T44
Test name
Test status
Simulation time	30011434 ps
CPU time	0.55 seconds
Started	Sep 18 01:19:52 AM UTC 24
Finished	Sep 18 01:19:54 AM UTC 24
Peak memory	155020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48363371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 9.prim_async_fatal_alert.48363371
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1552839949
Short name	T32
Test name
Test status
Simulation time	8237153 ps
CPU time	0.5 seconds
Started	Sep 18 01:19:54 AM UTC 24
Finished	Sep 18 01:19:55 AM UTC 24
Peak memory	154608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552839949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.1552839949
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/0.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.23065271
Short name	T23
Test name
Test status
Simulation time	9371538 ps
CPU time	0.39 seconds
Started	Sep 18 01:19:55 AM UTC 24
Finished	Sep 18 01:19:56 AM UTC 24
Peak memory	154544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23065271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.23065271
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/1.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3307585500
Short name	T57
Test name
Test status
Simulation time	9106012 ps
CPU time	0.4 seconds
Started	Sep 18 01:19:55 AM UTC 24
Finished	Sep 18 01:19:57 AM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307585500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.3307585500
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/10.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2268230875
Short name	T58
Test name
Test status
Simulation time	8191970 ps
CPU time	0.38 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	155280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268230875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.2268230875
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/11.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3053423176
Short name	T59
Test name
Test status
Simulation time	9204684 ps
CPU time	0.4 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053423176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.3053423176
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/12.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2781634588
Short name	T27
Test name
Test status
Simulation time	8228520 ps
CPU time	0.43 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781634588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 13.prim_sync_alert.2781634588
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/13.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2869712518
Short name	T26
Test name
Test status
Simulation time	10029787 ps
CPU time	0.36 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869712518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.2869712518
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/14.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3296502065
Short name	T28
Test name
Test status
Simulation time	8406606 ps
CPU time	0.4 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296502065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.3296502065
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/15.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.330260890
Short name	T60
Test name
Test status
Simulation time	9249006 ps
CPU time	0.43 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330260890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 16.prim_sync_alert.330260890
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/16.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1890311063
Short name	T62
Test name
Test status
Simulation time	10062860 ps
CPU time	0.4 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890311063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 17.prim_sync_alert.1890311063
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/17.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2313009436
Short name	T29
Test name
Test status
Simulation time	8645512 ps
CPU time	0.41 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313009436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 18.prim_sync_alert.2313009436
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/18.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.2141749826
Short name	T61
Test name
Test status
Simulation time	9355030 ps
CPU time	0.36 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141749826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 19.prim_sync_alert.2141749826
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/19.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.375635099
Short name	T33
Test name
Test status
Simulation time	8988018 ps
CPU time	0.38 seconds
Started	Sep 18 01:19:55 AM UTC 24
Finished	Sep 18 01:19:56 AM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375635099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 2.prim_sync_alert.375635099
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/2.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.436136632
Short name	T36
Test name
Test status
Simulation time	8620095 ps
CPU time	0.45 seconds
Started	Sep 18 01:19:55 AM UTC 24
Finished	Sep 18 01:19:57 AM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436136632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 3.prim_sync_alert.436136632
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/3.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.1430384505
Short name	T34
Test name
Test status
Simulation time	8611063 ps
CPU time	0.36 seconds
Started	Sep 18 01:19:55 AM UTC 24
Finished	Sep 18 01:19:56 AM UTC 24
Peak memory	154544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430384505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.1430384505
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/4.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.1605782163
Short name	T37
Test name
Test status
Simulation time	7709685 ps
CPU time	0.37 seconds
Started	Sep 18 01:19:55 AM UTC 24
Finished	Sep 18 01:19:57 AM UTC 24
Peak memory	154544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605782163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 6.prim_sync_alert.1605782163
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/6.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3661327040
Short name	T25
Test name
Test status
Simulation time	8935336 ps
CPU time	0.42 seconds
Started	Sep 18 01:19:55 AM UTC 24
Finished	Sep 18 01:19:57 AM UTC 24
Peak memory	154544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661327040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.3661327040
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/7.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3685611275
Short name	T24
Test name
Test status
Simulation time	9349142 ps
CPU time	0.37 seconds
Started	Sep 18 01:19:55 AM UTC 24
Finished	Sep 18 01:19:57 AM UTC 24
Peak memory	154544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685611275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.3685611275
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/8.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.476888298
Short name	T38
Test name
Test status
Simulation time	8217743 ps
CPU time	0.42 seconds
Started	Sep 18 01:19:55 AM UTC 24
Finished	Sep 18 01:19:57 AM UTC 24
Peak memory	154540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476888298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 9.prim_sync_alert.476888298
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/9.prim_sync_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.913354648
Short name	T31
Test name
Test status
Simulation time	26442576 ps
CPU time	0.48 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913354648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.913354648
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2002382903
Short name	T63
Test name
Test status
Simulation time	26793025 ps
CPU time	0.43 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002382903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2002382903
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.59024130
Short name	T69
Test name
Test status
Simulation time	28565556 ps
CPU time	0.35 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:59 AM UTC 24
Peak memory	154176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59024130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert .vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.59024130
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1407772900
Short name	T71
Test name
Test status
Simulation time	26987400 ps
CPU time	0.37 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:59 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407772900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1407772900
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1754262043
Short name	T73
Test name
Test status
Simulation time	26772309 ps
CPU time	0.44 seconds
Started	Sep 18 01:19:58 AM UTC 24
Finished	Sep 18 01:20:00 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754262043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1754262043
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3395913069
Short name	T72
Test name
Test status
Simulation time	28122678 ps
CPU time	0.36 seconds
Started	Sep 18 01:19:58 AM UTC 24
Finished	Sep 18 01:20:00 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395913069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3395913069
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3059563035
Short name	T74
Test name
Test status
Simulation time	28091302 ps
CPU time	0.38 seconds
Started	Sep 18 01:20:00 AM UTC 24
Finished	Sep 18 01:20:01 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059563035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3059563035
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.791872802
Short name	T75
Test name
Test status
Simulation time	27896811 ps
CPU time	0.36 seconds
Started	Sep 18 01:20:00 AM UTC 24
Finished	Sep 18 01:20:01 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791872802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.791872802
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1332345084
Short name	T76
Test name
Test status
Simulation time	29296392 ps
CPU time	0.44 seconds
Started	Sep 18 01:20:00 AM UTC 24
Finished	Sep 18 01:20:01 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332345084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1332345084
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1724522111
Short name	T77
Test name
Test status
Simulation time	27578743 ps
CPU time	0.37 seconds
Started	Sep 18 01:20:00 AM UTC 24
Finished	Sep 18 01:20:01 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724522111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1724522111
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.467635222
Short name	T78
Test name
Test status
Simulation time	27752339 ps
CPU time	0.41 seconds
Started	Sep 18 01:20:00 AM UTC 24
Finished	Sep 18 01:20:01 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467635222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.467635222
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.567646247
Short name	T30
Test name
Test status
Simulation time	28387730 ps
CPU time	0.4 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:58 AM UTC 24
Peak memory	154244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567646247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.567646247
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.407669607
Short name	T64
Test name
Test status
Simulation time	27836154 ps
CPU time	0.4 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:59 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407669607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.407669607
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3598118824
Short name	T4
Test name
Test status
Simulation time	27572212 ps
CPU time	0.43 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:59 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598118824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3598118824
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2938076481
Short name	T67
Test name
Test status
Simulation time	28320079 ps
CPU time	0.38 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:59 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938076481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2938076481
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3480365961
Short name	T65
Test name
Test status
Simulation time	26765240 ps
CPU time	0.38 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:59 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480365961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3480365961
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2132650124
Short name	T66
Test name
Test status
Simulation time	27594709 ps
CPU time	0.37 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:59 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132650124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2132650124
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1964410463
Short name	T68
Test name
Test status
Simulation time	28511941 ps
CPU time	0.41 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:59 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964410463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1964410463
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2548980372
Short name	T70
Test name
Test status
Simulation time	26361617 ps
CPU time	0.4 seconds
Started	Sep 18 01:19:57 AM UTC 24
Finished	Sep 18 01:19:59 AM UTC 24
Peak memory	154180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548980372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2548980372
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest