Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.86 89.86 100.00 100.00 93.75 93.75 100.00 100.00 82.14 82.14 95.83 95.83 67.44 67.44 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2006065302
92.99 3.13 100.00 0.00 93.75 0.00 100.00 0.00 89.29 7.14 95.83 0.00 79.07 11.63 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.3331687926
94.50 1.51 100.00 0.00 95.83 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 6.98 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3008480854
95.19 0.69 100.00 0.00 100.00 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4003579168

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2220374338
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.1392412969
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.882374491
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.3102125414
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.2235347157
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1352110586
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2735472628
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2779671940
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.1747314528
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3128915363
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.3709883497
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.611320633
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.133971682
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1404155787
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.43522894
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3739299534
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1236474341
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3688561032
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3290234072
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.64906354
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3042692571
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.2723702793
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.3508669367
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.249249641
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3363315863
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.419019365
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.741307746
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2802907219
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.3693903203
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.1700161758
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.334406881
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.4181172063
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.254741231
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.2491994697
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.1874217869
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3957231496
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2271951990
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.379978157
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3552848133
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1371431933
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.330984349
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2425489678
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3781397768
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.109151115
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.3028260966
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3463147219
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2525605877
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.3716382860
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.1376998013
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2741916871
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2308943626
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3989733851
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.4258830665
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.2128371886
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3131615026
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3475027720
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.224204699
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.959272652
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.257964725
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.133061333
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1401813933
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2473159894
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3278205056
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3128545999
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.946295772
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2261044643
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4148626339
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3371298760
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2997870584
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2511372383
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2099277851
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4151544524
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1321452286
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.444474859
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.827870479



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2220374338 Sep 24 03:48:14 AM UTC 24 Sep 24 03:48:15 AM UTC 24 12673242 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.1392412969 Sep 24 03:48:14 AM UTC 24 Sep 24 03:48:15 AM UTC 24 10475972 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2006065302 Sep 24 03:48:15 AM UTC 24 Sep 24 03:48:16 AM UTC 24 11699254 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1404155787 Sep 24 03:48:16 AM UTC 24 Sep 24 03:48:17 AM UTC 24 10694015 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.133971682 Sep 24 03:48:16 AM UTC 24 Sep 24 03:48:17 AM UTC 24 11514109 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.43522894 Sep 24 03:48:17 AM UTC 24 Sep 24 03:48:18 AM UTC 24 11057192 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3739299534 Sep 24 03:48:17 AM UTC 24 Sep 24 03:48:18 AM UTC 24 10769229 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1236474341 Sep 24 03:48:18 AM UTC 24 Sep 24 03:48:19 AM UTC 24 11789629 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3688561032 Sep 24 03:48:18 AM UTC 24 Sep 24 03:48:19 AM UTC 24 11950389 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3290234072 Sep 24 03:48:18 AM UTC 24 Sep 24 03:48:19 AM UTC 24 11288280 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.882374491 Sep 24 03:48:19 AM UTC 24 Sep 24 03:48:20 AM UTC 24 11297421 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.2235347157 Sep 24 03:48:19 AM UTC 24 Sep 24 03:48:20 AM UTC 24 10790789 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.3102125414 Sep 24 03:48:19 AM UTC 24 Sep 24 03:48:20 AM UTC 24 10907625 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1352110586 Sep 24 03:48:19 AM UTC 24 Sep 24 03:48:20 AM UTC 24 11042039 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3128915363 Sep 24 03:48:20 AM UTC 24 Sep 24 03:48:21 AM UTC 24 11110836 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2779671940 Sep 24 03:48:20 AM UTC 24 Sep 24 03:48:21 AM UTC 24 10745860 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2735472628 Sep 24 03:48:20 AM UTC 24 Sep 24 03:48:21 AM UTC 24 11783224 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.1747314528 Sep 24 03:48:20 AM UTC 24 Sep 24 03:48:21 AM UTC 24 10488889 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.3709883497 Sep 24 03:48:21 AM UTC 24 Sep 24 03:48:23 AM UTC 24 10239826 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.611320633 Sep 24 03:48:21 AM UTC 24 Sep 24 03:48:23 AM UTC 24 12556079 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.64906354 Sep 24 03:48:21 AM UTC 24 Sep 24 03:48:23 AM UTC 24 30125844 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3042692571 Sep 24 03:48:21 AM UTC 24 Sep 24 03:48:23 AM UTC 24 29580122 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3008480854 Sep 24 03:48:21 AM UTC 24 Sep 24 03:48:23 AM UTC 24 28999996 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.254741231 Sep 24 03:48:22 AM UTC 24 Sep 24 03:48:24 AM UTC 24 28137507 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.2491994697 Sep 24 03:48:22 AM UTC 24 Sep 24 03:48:24 AM UTC 24 27959022 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.1874217869 Sep 24 03:48:22 AM UTC 24 Sep 24 03:48:24 AM UTC 24 30820291 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.4181172063 Sep 24 03:48:22 AM UTC 24 Sep 24 03:48:24 AM UTC 24 31409856 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3957231496 Sep 24 03:48:22 AM UTC 24 Sep 24 03:48:24 AM UTC 24 28717532 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2271951990 Sep 24 03:48:22 AM UTC 24 Sep 24 03:48:24 AM UTC 24 30630452 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.2723702793 Sep 24 03:48:23 AM UTC 24 Sep 24 03:48:24 AM UTC 24 28201466 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.3508669367 Sep 24 03:48:23 AM UTC 24 Sep 24 03:48:24 AM UTC 24 32081121 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.249249641 Sep 24 03:48:23 AM UTC 24 Sep 24 03:48:24 AM UTC 24 30500590 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.419019365 Sep 24 03:48:23 AM UTC 24 Sep 24 03:48:24 AM UTC 24 31355449 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3363315863 Sep 24 03:48:23 AM UTC 24 Sep 24 03:48:24 AM UTC 24 29568367 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.3693903203 Sep 24 03:48:24 AM UTC 24 Sep 24 03:48:25 AM UTC 24 29025544 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.1700161758 Sep 24 03:48:24 AM UTC 24 Sep 24 03:48:25 AM UTC 24 30692639 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2802907219 Sep 24 03:48:24 AM UTC 24 Sep 24 03:48:25 AM UTC 24 30413668 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.741307746 Sep 24 03:48:24 AM UTC 24 Sep 24 03:48:25 AM UTC 24 30778106 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.334406881 Sep 24 03:48:24 AM UTC 24 Sep 24 03:48:25 AM UTC 24 29168303 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.2128371886 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:52 AM UTC 24 9350162 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.1376998013 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:52 AM UTC 24 9424581 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3475027720 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:52 AM UTC 24 9756480 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2308943626 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:52 AM UTC 24 10000882 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3552848133 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:52 AM UTC 24 10173583 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2741916871 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:52 AM UTC 24 8816369 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.4258830665 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:52 AM UTC 24 10226166 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3989733851 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:52 AM UTC 24 9386964 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3131615026 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:52 AM UTC 24 9232299 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.3331687926 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:52 AM UTC 24 9913877 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.330984349 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:53 AM UTC 24 9139597 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1371431933 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:53 AM UTC 24 10588611 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.379978157 Sep 24 01:50:51 AM UTC 24 Sep 24 01:50:53 AM UTC 24 8899839 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3781397768 Sep 24 01:50:52 AM UTC 24 Sep 24 01:50:54 AM UTC 24 10632481 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2425489678 Sep 24 01:50:52 AM UTC 24 Sep 24 01:50:54 AM UTC 24 9489625 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.109151115 Sep 24 01:50:52 AM UTC 24 Sep 24 01:50:54 AM UTC 24 9959680 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3463147219 Sep 24 01:50:53 AM UTC 24 Sep 24 01:50:54 AM UTC 24 9397216 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.3028260966 Sep 24 01:50:53 AM UTC 24 Sep 24 01:50:54 AM UTC 24 8284927 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.3716382860 Sep 24 01:50:53 AM UTC 24 Sep 24 01:50:54 AM UTC 24 7680299 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2525605877 Sep 24 01:50:53 AM UTC 24 Sep 24 01:50:54 AM UTC 24 8506739 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.224204699 Sep 24 01:50:53 AM UTC 24 Sep 24 01:50:54 AM UTC 24 26608851 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.959272652 Sep 24 01:50:53 AM UTC 24 Sep 24 01:50:54 AM UTC 24 27780030 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3371298760 Sep 24 01:50:53 AM UTC 24 Sep 24 01:50:54 AM UTC 24 27320444 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2511372383 Sep 24 01:50:53 AM UTC 24 Sep 24 01:50:55 AM UTC 24 27117253 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2997870584 Sep 24 01:50:53 AM UTC 24 Sep 24 01:50:55 AM UTC 24 27614852 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4151544524 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 26744096 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2099277851 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 25789936 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.827870479 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 27744476 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.444474859 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 28062749 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1321452286 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 25392285 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.257964725 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 29867309 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.133061333 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 28060385 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2473159894 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 26823363 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1401813933 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 27582605 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4003579168 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 26521855 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3128545999 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 27463864 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3278205056 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 26905858 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.946295772 Sep 24 01:50:54 AM UTC 24 Sep 24 01:50:56 AM UTC 24 29923162 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2261044643 Sep 24 01:50:55 AM UTC 24 Sep 24 01:50:57 AM UTC 24 25959594 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4148626339 Sep 24 01:50:55 AM UTC 24 Sep 24 01:50:57 AM UTC 24 27333394 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2006065302
Short name T3
Test name
Test status
Simulation time 11699254 ps
CPU time 0.34 seconds
Started Sep 24 03:48:15 AM UTC 24
Finished Sep 24 03:48:16 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006065302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 2.prim_async_alert.2006065302
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/2.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.3331687926
Short name T40
Test name
Test status
Simulation time 9913877 ps
CPU time 0.43 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:52 AM UTC 24
Peak memory 152544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331687926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 1.prim_sync_alert.3331687926
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/1.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3008480854
Short name T42
Test name
Test status
Simulation time 28999996 ps
CPU time 0.38 seconds
Started Sep 24 03:48:21 AM UTC 24
Finished Sep 24 03:48:23 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008480854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 2.prim_async_fatal_alert.3008480854
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.4003579168
Short name T6
Test name
Test status
Simulation time 26521855 ps
CPU time 0.36 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003579168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.4003579168
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2220374338
Short name T1
Test name
Test status
Simulation time 12673242 ps
CPU time 0.57 seconds
Started Sep 24 03:48:14 AM UTC 24
Finished Sep 24 03:48:15 AM UTC 24
Peak memory 155216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220374338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 0.prim_async_alert.2220374338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/0.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.1392412969
Short name T2
Test name
Test status
Simulation time 10475972 ps
CPU time 0.4 seconds
Started Sep 24 03:48:14 AM UTC 24
Finished Sep 24 03:48:15 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392412969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 1.prim_async_alert.1392412969
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/1.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.882374491
Short name T25
Test name
Test status
Simulation time 11297421 ps
CPU time 0.37 seconds
Started Sep 24 03:48:19 AM UTC 24
Finished Sep 24 03:48:20 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882374491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 10.prim_async_alert.882374491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/10.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.3102125414
Short name T13
Test name
Test status
Simulation time 10907625 ps
CPU time 0.34 seconds
Started Sep 24 03:48:19 AM UTC 24
Finished Sep 24 03:48:20 AM UTC 24
Peak memory 155156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102125414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 11.prim_async_alert.3102125414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/11.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.2235347157
Short name T26
Test name
Test status
Simulation time 10790789 ps
CPU time 0.35 seconds
Started Sep 24 03:48:19 AM UTC 24
Finished Sep 24 03:48:20 AM UTC 24
Peak memory 155156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235347157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 12.prim_async_alert.2235347157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/12.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1352110586
Short name T46
Test name
Test status
Simulation time 11042039 ps
CPU time 0.34 seconds
Started Sep 24 03:48:19 AM UTC 24
Finished Sep 24 03:48:20 AM UTC 24
Peak memory 155156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352110586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 13.prim_async_alert.1352110586
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/13.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2735472628
Short name T49
Test name
Test status
Simulation time 11783224 ps
CPU time 0.39 seconds
Started Sep 24 03:48:20 AM UTC 24
Finished Sep 24 03:48:21 AM UTC 24
Peak memory 155144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735472628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.prim_async_alert.2735472628
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/14.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2779671940
Short name T48
Test name
Test status
Simulation time 10745860 ps
CPU time 0.37 seconds
Started Sep 24 03:48:20 AM UTC 24
Finished Sep 24 03:48:21 AM UTC 24
Peak memory 155156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779671940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 15.prim_async_alert.2779671940
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/15.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.1747314528
Short name T50
Test name
Test status
Simulation time 10488889 ps
CPU time 0.35 seconds
Started Sep 24 03:48:20 AM UTC 24
Finished Sep 24 03:48:21 AM UTC 24
Peak memory 155156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747314528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 16.prim_async_alert.1747314528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/16.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3128915363
Short name T47
Test name
Test status
Simulation time 11110836 ps
CPU time 0.36 seconds
Started Sep 24 03:48:20 AM UTC 24
Finished Sep 24 03:48:21 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128915363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 17.prim_async_alert.3128915363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/17.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.3709883497
Short name T20
Test name
Test status
Simulation time 10239826 ps
CPU time 0.4 seconds
Started Sep 24 03:48:21 AM UTC 24
Finished Sep 24 03:48:23 AM UTC 24
Peak memory 155156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709883497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 18.prim_async_alert.3709883497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/18.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.611320633
Short name T14
Test name
Test status
Simulation time 12556079 ps
CPU time 0.38 seconds
Started Sep 24 03:48:21 AM UTC 24
Finished Sep 24 03:48:23 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611320633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 19.prim_async_alert.611320633
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/19.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.133971682
Short name T17
Test name
Test status
Simulation time 11514109 ps
CPU time 0.35 seconds
Started Sep 24 03:48:16 AM UTC 24
Finished Sep 24 03:48:17 AM UTC 24
Peak memory 155156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133971682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 3.prim_async_alert.133971682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/3.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1404155787
Short name T7
Test name
Test status
Simulation time 10694015 ps
CPU time 0.35 seconds
Started Sep 24 03:48:16 AM UTC 24
Finished Sep 24 03:48:17 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404155787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 4.prim_async_alert.1404155787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/4.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.43522894
Short name T18
Test name
Test status
Simulation time 11057192 ps
CPU time 0.37 seconds
Started Sep 24 03:48:17 AM UTC 24
Finished Sep 24 03:48:18 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43522894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 5.prim_async_alert.43522894
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/5.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3739299534
Short name T8
Test name
Test status
Simulation time 10769229 ps
CPU time 0.33 seconds
Started Sep 24 03:48:17 AM UTC 24
Finished Sep 24 03:48:18 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739299534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 6.prim_async_alert.3739299534
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/6.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1236474341
Short name T16
Test name
Test status
Simulation time 11789629 ps
CPU time 0.34 seconds
Started Sep 24 03:48:18 AM UTC 24
Finished Sep 24 03:48:19 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236474341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 7.prim_async_alert.1236474341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/7.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.3688561032
Short name T9
Test name
Test status
Simulation time 11950389 ps
CPU time 0.37 seconds
Started Sep 24 03:48:18 AM UTC 24
Finished Sep 24 03:48:19 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688561032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 8.prim_async_alert.3688561032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/8.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3290234072
Short name T19
Test name
Test status
Simulation time 11288280 ps
CPU time 0.36 seconds
Started Sep 24 03:48:18 AM UTC 24
Finished Sep 24 03:48:19 AM UTC 24
Peak memory 155152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290234072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 9.prim_async_alert.3290234072
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/9.prim_async_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.64906354
Short name T21
Test name
Test status
Simulation time 30125844 ps
CPU time 0.43 seconds
Started Sep 24 03:48:21 AM UTC 24
Finished Sep 24 03:48:23 AM UTC 24
Peak memory 155080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64906354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l
og /dev/null -cm_name 0.prim_async_fatal_alert.64906354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3042692571
Short name T15
Test name
Test status
Simulation time 29580122 ps
CPU time 0.37 seconds
Started Sep 24 03:48:21 AM UTC 24
Finished Sep 24 03:48:23 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042692571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 1.prim_async_fatal_alert.3042692571
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.2723702793
Short name T45
Test name
Test status
Simulation time 28201466 ps
CPU time 0.37 seconds
Started Sep 24 03:48:23 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723702793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 10.prim_async_fatal_alert.2723702793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.3508669367
Short name T12
Test name
Test status
Simulation time 32081121 ps
CPU time 0.35 seconds
Started Sep 24 03:48:23 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508669367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 11.prim_async_fatal_alert.3508669367
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.249249641
Short name T51
Test name
Test status
Simulation time 30500590 ps
CPU time 0.38 seconds
Started Sep 24 03:48:23 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 154676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249249641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_
log /dev/null -cm_name 12.prim_async_fatal_alert.249249641
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3363315863
Short name T41
Test name
Test status
Simulation time 29568367 ps
CPU time 0.39 seconds
Started Sep 24 03:48:23 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363315863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 13.prim_async_fatal_alert.3363315863
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.419019365
Short name T52
Test name
Test status
Simulation time 31355449 ps
CPU time 0.36 seconds
Started Sep 24 03:48:23 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419019365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_
log /dev/null -cm_name 14.prim_async_fatal_alert.419019365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.741307746
Short name T55
Test name
Test status
Simulation time 30778106 ps
CPU time 0.48 seconds
Started Sep 24 03:48:24 AM UTC 24
Finished Sep 24 03:48:25 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741307746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_
log /dev/null -cm_name 15.prim_async_fatal_alert.741307746
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2802907219
Short name T54
Test name
Test status
Simulation time 30413668 ps
CPU time 0.38 seconds
Started Sep 24 03:48:24 AM UTC 24
Finished Sep 24 03:48:25 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802907219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 16.prim_async_fatal_alert.2802907219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.3693903203
Short name T53
Test name
Test status
Simulation time 29025544 ps
CPU time 0.38 seconds
Started Sep 24 03:48:24 AM UTC 24
Finished Sep 24 03:48:25 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693903203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 17.prim_async_fatal_alert.3693903203
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.1700161758
Short name T4
Test name
Test status
Simulation time 30692639 ps
CPU time 0.38 seconds
Started Sep 24 03:48:24 AM UTC 24
Finished Sep 24 03:48:25 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700161758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 18.prim_async_fatal_alert.1700161758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.334406881
Short name T56
Test name
Test status
Simulation time 29168303 ps
CPU time 0.38 seconds
Started Sep 24 03:48:24 AM UTC 24
Finished Sep 24 03:48:25 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334406881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_
log /dev/null -cm_name 19.prim_async_fatal_alert.334406881
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.4181172063
Short name T24
Test name
Test status
Simulation time 31409856 ps
CPU time 0.47 seconds
Started Sep 24 03:48:22 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181172063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 3.prim_async_fatal_alert.4181172063
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.254741231
Short name T22
Test name
Test status
Simulation time 28137507 ps
CPU time 0.37 seconds
Started Sep 24 03:48:22 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254741231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_
log /dev/null -cm_name 4.prim_async_fatal_alert.254741231
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.2491994697
Short name T23
Test name
Test status
Simulation time 27959022 ps
CPU time 0.38 seconds
Started Sep 24 03:48:22 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491994697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 5.prim_async_fatal_alert.2491994697
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.1874217869
Short name T43
Test name
Test status
Simulation time 30820291 ps
CPU time 0.38 seconds
Started Sep 24 03:48:22 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 154876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874217869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 6.prim_async_fatal_alert.1874217869
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3957231496
Short name T44
Test name
Test status
Simulation time 28717532 ps
CPU time 0.42 seconds
Started Sep 24 03:48:22 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957231496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 7.prim_async_fatal_alert.3957231496
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2271951990
Short name T11
Test name
Test status
Simulation time 30630452 ps
CPU time 0.38 seconds
Started Sep 24 03:48:22 AM UTC 24
Finished Sep 24 03:48:24 AM UTC 24
Peak memory 155012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271951990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm
_log /dev/null -cm_name 8.prim_async_fatal_alert.2271951990
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.379978157
Short name T58
Test name
Test status
Simulation time 8899839 ps
CPU time 0.62 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:53 AM UTC 24
Peak memory 154520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379978157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo
g /dev/null -cm_name 0.prim_sync_alert.379978157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/0.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3552848133
Short name T38
Test name
Test status
Simulation time 10173583 ps
CPU time 0.36 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:52 AM UTC 24
Peak memory 154484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552848133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 10.prim_sync_alert.3552848133
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/10.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.1371431933
Short name T33
Test name
Test status
Simulation time 10588611 ps
CPU time 0.34 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:53 AM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371431933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 11.prim_sync_alert.1371431933
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/11.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.330984349
Short name T57
Test name
Test status
Simulation time 9139597 ps
CPU time 0.35 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:53 AM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330984349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo
g /dev/null -cm_name 12.prim_sync_alert.330984349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/12.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2425489678
Short name T34
Test name
Test status
Simulation time 9489625 ps
CPU time 0.36 seconds
Started Sep 24 01:50:52 AM UTC 24
Finished Sep 24 01:50:54 AM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425489678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 13.prim_sync_alert.2425489678
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/13.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3781397768
Short name T59
Test name
Test status
Simulation time 10632481 ps
CPU time 0.36 seconds
Started Sep 24 01:50:52 AM UTC 24
Finished Sep 24 01:50:54 AM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781397768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 14.prim_sync_alert.3781397768
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/14.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.109151115
Short name T60
Test name
Test status
Simulation time 9959680 ps
CPU time 0.33 seconds
Started Sep 24 01:50:52 AM UTC 24
Finished Sep 24 01:50:54 AM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109151115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo
g /dev/null -cm_name 15.prim_sync_alert.109151115
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/15.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.3028260966
Short name T62
Test name
Test status
Simulation time 8284927 ps
CPU time 0.39 seconds
Started Sep 24 01:50:53 AM UTC 24
Finished Sep 24 01:50:54 AM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028260966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 16.prim_sync_alert.3028260966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/16.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3463147219
Short name T61
Test name
Test status
Simulation time 9397216 ps
CPU time 0.35 seconds
Started Sep 24 01:50:53 AM UTC 24
Finished Sep 24 01:50:54 AM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463147219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 17.prim_sync_alert.3463147219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/17.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2525605877
Short name T35
Test name
Test status
Simulation time 8506739 ps
CPU time 0.34 seconds
Started Sep 24 01:50:53 AM UTC 24
Finished Sep 24 01:50:54 AM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525605877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 18.prim_sync_alert.2525605877
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/18.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.3716382860
Short name T63
Test name
Test status
Simulation time 7680299 ps
CPU time 0.35 seconds
Started Sep 24 01:50:53 AM UTC 24
Finished Sep 24 01:50:54 AM UTC 24
Peak memory 154540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716382860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 19.prim_sync_alert.3716382860
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/19.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.1376998013
Short name T28
Test name
Test status
Simulation time 9424581 ps
CPU time 0.42 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:52 AM UTC 24
Peak memory 154436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376998013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 2.prim_sync_alert.1376998013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/2.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2741916871
Short name T30
Test name
Test status
Simulation time 8816369 ps
CPU time 0.43 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:52 AM UTC 24
Peak memory 153876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741916871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 3.prim_sync_alert.2741916871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/3.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.2308943626
Short name T37
Test name
Test status
Simulation time 10000882 ps
CPU time 0.44 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:52 AM UTC 24
Peak memory 151740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308943626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 4.prim_sync_alert.2308943626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/4.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3989733851
Short name T32
Test name
Test status
Simulation time 9386964 ps
CPU time 0.41 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:52 AM UTC 24
Peak memory 151464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989733851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 5.prim_sync_alert.3989733851
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/5.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.4258830665
Short name T31
Test name
Test status
Simulation time 10226166 ps
CPU time 0.42 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:52 AM UTC 24
Peak memory 153716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258830665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 6.prim_sync_alert.4258830665
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/6.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.2128371886
Short name T27
Test name
Test status
Simulation time 9350162 ps
CPU time 0.38 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:52 AM UTC 24
Peak memory 154436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128371886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 7.prim_sync_alert.2128371886
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/7.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.3131615026
Short name T39
Test name
Test status
Simulation time 9232299 ps
CPU time 0.35 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:52 AM UTC 24
Peak memory 153864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131615026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 8.prim_sync_alert.3131615026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/8.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.3475027720
Short name T29
Test name
Test status
Simulation time 9756480 ps
CPU time 0.36 seconds
Started Sep 24 01:50:51 AM UTC 24
Finished Sep 24 01:50:52 AM UTC 24
Peak memory 154608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475027720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l
og /dev/null -cm_name 9.prim_sync_alert.3475027720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/9.prim_sync_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.224204699
Short name T64
Test name
Test status
Simulation time 26608851 ps
CPU time 0.36 seconds
Started Sep 24 01:50:53 AM UTC 24
Finished Sep 24 01:50:54 AM UTC 24
Peak memory 154240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224204699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_aler
t.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.224204699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.959272652
Short name T65
Test name
Test status
Simulation time 27780030 ps
CPU time 0.34 seconds
Started Sep 24 01:50:53 AM UTC 24
Finished Sep 24 01:50:54 AM UTC 24
Peak memory 154176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959272652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_aler
t.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.959272652
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.257964725
Short name T72
Test name
Test status
Simulation time 29867309 ps
CPU time 0.37 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257964725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_aler
t.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.257964725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.133061333
Short name T73
Test name
Test status
Simulation time 28060385 ps
CPU time 0.4 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133061333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_aler
t.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.133061333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1401813933
Short name T5
Test name
Test status
Simulation time 27582605 ps
CPU time 0.39 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401813933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1401813933
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2473159894
Short name T74
Test name
Test status
Simulation time 26823363 ps
CPU time 0.35 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473159894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2473159894
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3278205056
Short name T76
Test name
Test status
Simulation time 26905858 ps
CPU time 0.4 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278205056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3278205056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3128545999
Short name T75
Test name
Test status
Simulation time 27463864 ps
CPU time 0.37 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128545999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3128545999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.946295772
Short name T77
Test name
Test status
Simulation time 29923162 ps
CPU time 0.38 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946295772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_aler
t.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.946295772
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2261044643
Short name T78
Test name
Test status
Simulation time 25959594 ps
CPU time 0.38 seconds
Started Sep 24 01:50:55 AM UTC 24
Finished Sep 24 01:50:57 AM UTC 24
Peak memory 154176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261044643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2261044643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.4148626339
Short name T79
Test name
Test status
Simulation time 27333394 ps
CPU time 0.4 seconds
Started Sep 24 01:50:55 AM UTC 24
Finished Sep 24 01:50:57 AM UTC 24
Peak memory 154156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148626339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.4148626339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3371298760
Short name T10
Test name
Test status
Simulation time 27320444 ps
CPU time 0.34 seconds
Started Sep 24 01:50:53 AM UTC 24
Finished Sep 24 01:50:54 AM UTC 24
Peak memory 154180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371298760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3371298760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2997870584
Short name T66
Test name
Test status
Simulation time 27614852 ps
CPU time 0.35 seconds
Started Sep 24 01:50:53 AM UTC 24
Finished Sep 24 01:50:55 AM UTC 24
Peak memory 154180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997870584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2997870584
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2511372383
Short name T36
Test name
Test status
Simulation time 27117253 ps
CPU time 0.36 seconds
Started Sep 24 01:50:53 AM UTC 24
Finished Sep 24 01:50:55 AM UTC 24
Peak memory 154180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511372383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2511372383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2099277851
Short name T68
Test name
Test status
Simulation time 25789936 ps
CPU time 0.36 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099277851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2099277851
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.4151544524
Short name T67
Test name
Test status
Simulation time 26744096 ps
CPU time 0.35 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151544524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.4151544524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1321452286
Short name T71
Test name
Test status
Simulation time 25392285 ps
CPU time 0.39 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 153932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321452286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_ale
rt.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1321452286
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.444474859
Short name T70
Test name
Test status
Simulation time 28062749 ps
CPU time 0.39 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444474859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_aler
t.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.444474859
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.827870479
Short name T69
Test name
Test status
Simulation time 27744476 ps
CPU time 0.4 seconds
Started Sep 24 01:50:54 AM UTC 24
Finished Sep 24 01:50:56 AM UTC 24
Peak memory 154168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827870479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/coverage/sync_fatal_aler
t.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.827870479
Directory /workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest
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