| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 89.27 | 89.27 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3804439078 |
| 92.39 | 3.13 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2087416274 |
| 94.15 | 1.76 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1270397487 |
| 94.50 | 0.35 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2470061569 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3715577613 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.212400436 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.375709859 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2334666072 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.397956532 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3884994494 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.3054709771 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3492358169 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2372333002 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.467567986 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.2864764863 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.3973150282 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.4040647733 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.1489149823 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.2557616241 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3595044554 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.859423417 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.2807630733 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.49828622 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3310844792 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3747955574 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1772650143 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2826706053 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.286891866 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.4078382779 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2476244604 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2462043152 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.956714142 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2584146567 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.997542944 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2697929967 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1358330393 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.3347544210 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2702199831 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1395046358 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2276023808 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.853704093 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.4031020302 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3901878403 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2023112115 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3231970780 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2868441171 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3738248166 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2745837033 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.1632189842 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.2958060437 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.3151704770 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.1083331375 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2732749995 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.75446421 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.3633889754 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.337348351 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2219272017 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3302058602 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.902795769 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1777871493 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3075011159 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.840478500 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2102264050 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1494985565 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2421663194 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3925691223 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1451668612 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1871316344 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.459755057 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2683401619 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1692869051 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2275634570 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2608861110 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1574305916 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1629879925 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1089037138 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1964491465 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1146746844 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3224946701 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.1489149823 | Oct 02 04:06:37 PM UTC 24 | Oct 02 04:06:39 PM UTC 24 | 10791444 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.859423417 | Oct 02 04:06:37 PM UTC 24 | Oct 02 04:06:39 PM UTC 24 | 12475955 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2470061569 | Oct 02 04:06:37 PM UTC 24 | Oct 02 04:06:39 PM UTC 24 | 11913258 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3595044554 | Oct 02 04:06:37 PM UTC 24 | Oct 02 04:06:39 PM UTC 24 | 11526826 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.375709859 | Oct 02 04:06:37 PM UTC 24 | Oct 02 04:06:39 PM UTC 24 | 11760181 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.2557616241 | Oct 02 04:06:37 PM UTC 24 | Oct 02 04:06:39 PM UTC 24 | 10946121 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.49828622 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:41 PM UTC 24 | 11079859 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3804439078 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:41 PM UTC 24 | 11958122 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.2807630733 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:41 PM UTC 24 | 11269228 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3310844792 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:41 PM UTC 24 | 11671907 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.397956532 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:41 PM UTC 24 | 10600998 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2334666072 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:41 PM UTC 24 | 10907478 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3884994494 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:41 PM UTC 24 | 11174239 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.3054709771 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:41 PM UTC 24 | 10717092 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2372333002 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:41 PM UTC 24 | 10804684 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.467567986 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:41 PM UTC 24 | 10958757 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3492358169 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 10347085 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.2864764863 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 10510065 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.3973150282 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 11281695 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.4040647733 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 10413124 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2697929967 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 32274865 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1270397487 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 30398614 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3747955574 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 29196011 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1358330393 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 30360280 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.3347544210 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 30527237 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2702199831 | Oct 02 04:06:40 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 29501333 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2276023808 | Oct 02 04:06:41 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 30789232 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1772650143 | Oct 02 04:06:41 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 29593695 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1395046358 | Oct 02 04:06:41 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 31321110 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.853704093 | Oct 02 04:06:41 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 28312565 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2826706053 | Oct 02 04:06:41 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 29310431 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.286891866 | Oct 02 04:06:41 PM UTC 24 | Oct 02 04:06:42 PM UTC 24 | 30012632 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.4078382779 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:43 PM UTC 24 | 29119210 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2476244604 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 30400066 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3715577613 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 30012894 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.997542944 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 32207644 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2584146567 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 30534345 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2462043152 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 30925552 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.956714142 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 30785501 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.4031020302 | Oct 02 04:20:26 PM UTC 24 | Oct 02 04:20:27 PM UTC 24 | 8637717 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2087416274 | Oct 02 04:20:28 PM UTC 24 | Oct 02 04:20:29 PM UTC 24 | 9717941 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2732749995 | Oct 02 04:20:30 PM UTC 24 | Oct 02 04:20:31 PM UTC 24 | 9060656 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.75446421 | Oct 02 04:20:32 PM UTC 24 | Oct 02 04:20:33 PM UTC 24 | 8855661 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.3633889754 | Oct 02 04:20:34 PM UTC 24 | Oct 02 04:20:36 PM UTC 24 | 10102503 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.337348351 | Oct 02 04:20:37 PM UTC 24 | Oct 02 04:20:39 PM UTC 24 | 9456082 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2219272017 | Oct 02 04:20:40 PM UTC 24 | Oct 02 04:20:42 PM UTC 24 | 9825833 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3302058602 | Oct 02 04:20:42 PM UTC 24 | Oct 02 04:20:44 PM UTC 24 | 9752651 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.212400436 | Oct 02 04:20:44 PM UTC 24 | Oct 02 04:20:46 PM UTC 24 | 9631009 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.902795769 | Oct 02 04:20:46 PM UTC 24 | Oct 02 04:20:47 PM UTC 24 | 8398715 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2023112115 | Oct 02 04:20:47 PM UTC 24 | Oct 02 04:20:48 PM UTC 24 | 9041916 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3901878403 | Oct 02 04:20:47 PM UTC 24 | Oct 02 04:20:48 PM UTC 24 | 9949308 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3231970780 | Oct 02 04:20:47 PM UTC 24 | Oct 02 04:20:48 PM UTC 24 | 9350041 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2868441171 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:20:50 PM UTC 24 | 9067327 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2745837033 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:20:50 PM UTC 24 | 9111156 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3738248166 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:20:50 PM UTC 24 | 8040440 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.1632189842 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:20:50 PM UTC 24 | 8757922 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.1083331375 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:20:50 PM UTC 24 | 10274907 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.2958060437 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:20:50 PM UTC 24 | 8599352 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.3151704770 | Oct 02 04:20:48 PM UTC 24 | Oct 02 04:20:50 PM UTC 24 | 8430919 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1574305916 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 26878787 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1777871493 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 27232301 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2608861110 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 28025482 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3075011159 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 28546808 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2275634570 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 28656374 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1964491465 | Oct 02 04:06:43 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 27235306 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1089037138 | Oct 02 04:06:43 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 28183451 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1629879925 | Oct 02 04:06:42 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 28515740 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3224946701 | Oct 02 04:06:43 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 28953946 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.840478500 | Oct 02 04:06:43 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 26007566 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1146746844 | Oct 02 04:06:43 PM UTC 24 | Oct 02 04:06:44 PM UTC 24 | 26252372 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2102264050 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 25182079 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2421663194 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 28505355 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3925691223 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 28643813 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1494985565 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 28261475 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.459755057 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 29346618 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1871316344 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 28308321 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1451668612 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 26399669 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2683401619 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 26442988 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1692869051 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 27130901 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3804439078 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11958122 ps |
| CPU time | 0.47 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:41 PM UTC 24 |
| Peak memory | 155092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804439078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.prim_async_alert.3804439078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/6.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.2087416274 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9717941 ps |
| CPU time | 0.34 seconds |
| Started | Oct 02 04:20:28 PM UTC 24 |
| Finished | Oct 02 04:20:29 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087416274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 1.prim_sync_alert.2087416274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/1.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.1270397487 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 30398614 ps |
| CPU time | 0.48 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270397487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.1270397487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2470061569 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11913258 ps |
| CPU time | 0.77 seconds |
| Started | Oct 02 04:06:37 PM UTC 24 |
| Finished | Oct 02 04:06:39 PM UTC 24 |
| Peak memory | 154748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470061569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.prim_async_alert.2470061569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/0.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.3715577613 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30012894 ps |
| CPU time | 0.45 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715577613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.3715577613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.212400436 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9631009 ps |
| CPU time | 0.35 seconds |
| Started | Oct 02 04:20:44 PM UTC 24 |
| Finished | Oct 02 04:20:46 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212400436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 8.prim_sync_alert.212400436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/8.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.375709859 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11760181 ps |
| CPU time | 0.6 seconds |
| Started | Oct 02 04:06:37 PM UTC 24 |
| Finished | Oct 02 04:06:39 PM UTC 24 |
| Peak memory | 153380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375709859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.prim_async_alert.375709859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/1.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2334666072 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10907478 ps |
| CPU time | 0.51 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:41 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334666072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 10.prim_async_alert.2334666072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/10.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.397956532 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10600998 ps |
| CPU time | 0.41 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:41 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397956532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 11.prim_async_alert.397956532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/11.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3884994494 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11174239 ps |
| CPU time | 0.47 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:41 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884994494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 12.prim_async_alert.3884994494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/12.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.3054709771 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10717092 ps |
| CPU time | 0.43 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:41 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054709771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.prim_async_alert.3054709771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/13.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3492358169 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10347085 ps |
| CPU time | 0.55 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492358169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.3492358169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/14.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2372333002 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10804684 ps |
| CPU time | 0.43 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:41 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372333002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.2372333002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/15.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.467567986 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10958757 ps |
| CPU time | 0.4 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:41 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467567986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 16.prim_async_alert.467567986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/16.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.2864764863 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10510065 ps |
| CPU time | 0.43 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864764863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.2864764863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/17.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.3973150282 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11281695 ps |
| CPU time | 0.47 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973150282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.prim_async_alert.3973150282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/18.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.4040647733 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10413124 ps |
| CPU time | 0.4 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040647733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 19.prim_async_alert.4040647733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/19.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.1489149823 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10791444 ps |
| CPU time | 0.63 seconds |
| Started | Oct 02 04:06:37 PM UTC 24 |
| Finished | Oct 02 04:06:39 PM UTC 24 |
| Peak memory | 153956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489149823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.prim_async_alert.1489149823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/2.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.2557616241 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10946121 ps |
| CPU time | 0.67 seconds |
| Started | Oct 02 04:06:37 PM UTC 24 |
| Finished | Oct 02 04:06:39 PM UTC 24 |
| Peak memory | 153360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557616241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 3.prim_async_alert.2557616241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/3.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.3595044554 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11526826 ps |
| CPU time | 0.62 seconds |
| Started | Oct 02 04:06:37 PM UTC 24 |
| Finished | Oct 02 04:06:39 PM UTC 24 |
| Peak memory | 153492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595044554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 4.prim_async_alert.3595044554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/4.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.859423417 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12475955 ps |
| CPU time | 0.58 seconds |
| Started | Oct 02 04:06:37 PM UTC 24 |
| Finished | Oct 02 04:06:39 PM UTC 24 |
| Peak memory | 153668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859423417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 5.prim_async_alert.859423417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/5.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.2807630733 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11269228 ps |
| CPU time | 0.46 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:41 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807630733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 7.prim_async_alert.2807630733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/7.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.49828622 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11079859 ps |
| CPU time | 0.45 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:41 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49828622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 8.prim_async_alert.49828622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/8.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3310844792 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11671907 ps |
| CPU time | 0.46 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:41 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310844792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.3310844792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/9.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3747955574 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29196011 ps |
| CPU time | 0.49 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747955574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.3747955574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1772650143 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29593695 ps |
| CPU time | 0.46 seconds |
| Started | Oct 02 04:06:41 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772650143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.1772650143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2826706053 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 29310431 ps |
| CPU time | 0.46 seconds |
| Started | Oct 02 04:06:41 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 154916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826706053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.2826706053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.286891866 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30012632 ps |
| CPU time | 0.42 seconds |
| Started | Oct 02 04:06:41 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286891866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 12.prim_async_fatal_alert.286891866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.4078382779 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 29119210 ps |
| CPU time | 0.44 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:43 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078382779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 13.prim_async_fatal_alert.4078382779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2476244604 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30400066 ps |
| CPU time | 0.44 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476244604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 14.prim_async_fatal_alert.2476244604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.2462043152 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 30925552 ps |
| CPU time | 0.45 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462043152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 16.prim_async_fatal_alert.2462043152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.956714142 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30785501 ps |
| CPU time | 0.48 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956714142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 17.prim_async_fatal_alert.956714142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2584146567 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30534345 ps |
| CPU time | 0.44 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584146567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 18.prim_async_fatal_alert.2584146567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.997542944 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 32207644 ps |
| CPU time | 0.42 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997542944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 19.prim_async_fatal_alert.997542944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.2697929967 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 32274865 ps |
| CPU time | 0.46 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697929967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 3.prim_async_fatal_alert.2697929967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1358330393 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30360280 ps |
| CPU time | 0.42 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358330393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 4.prim_async_fatal_alert.1358330393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.3347544210 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30527237 ps |
| CPU time | 0.43 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347544210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 5.prim_async_fatal_alert.3347544210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2702199831 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 29501333 ps |
| CPU time | 0.47 seconds |
| Started | Oct 02 04:06:40 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702199831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 6.prim_async_fatal_alert.2702199831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1395046358 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 31321110 ps |
| CPU time | 0.52 seconds |
| Started | Oct 02 04:06:41 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395046358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 7.prim_async_fatal_alert.1395046358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.2276023808 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30789232 ps |
| CPU time | 0.41 seconds |
| Started | Oct 02 04:06:41 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276023808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 8.prim_async_fatal_alert.2276023808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.853704093 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 28312565 ps |
| CPU time | 0.44 seconds |
| Started | Oct 02 04:06:41 PM UTC 24 |
| Finished | Oct 02 04:06:42 PM UTC 24 |
| Peak memory | 154956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853704093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 9.prim_async_fatal_alert.853704093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.4031020302 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8637717 ps |
| CPU time | 0.58 seconds |
| Started | Oct 02 04:20:26 PM UTC 24 |
| Finished | Oct 02 04:20:27 PM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031020302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.4031020302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/0.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.3901878403 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9949308 ps |
| CPU time | 0.41 seconds |
| Started | Oct 02 04:20:47 PM UTC 24 |
| Finished | Oct 02 04:20:48 PM UTC 24 |
| Peak memory | 154352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901878403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.3901878403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/10.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2023112115 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9041916 ps |
| CPU time | 0.39 seconds |
| Started | Oct 02 04:20:47 PM UTC 24 |
| Finished | Oct 02 04:20:48 PM UTC 24 |
| Peak memory | 154436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023112115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.2023112115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/11.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3231970780 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9350041 ps |
| CPU time | 0.48 seconds |
| Started | Oct 02 04:20:47 PM UTC 24 |
| Finished | Oct 02 04:20:48 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231970780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.3231970780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/12.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.2868441171 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9067327 ps |
| CPU time | 0.4 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:20:50 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868441171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 13.prim_sync_alert.2868441171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/13.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.3738248166 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8040440 ps |
| CPU time | 0.35 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:20:50 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738248166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.3738248166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/14.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.2745837033 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9111156 ps |
| CPU time | 0.38 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:20:50 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745837033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.2745837033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/15.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.1632189842 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8757922 ps |
| CPU time | 0.37 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:20:50 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632189842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 16.prim_sync_alert.1632189842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/16.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.2958060437 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8599352 ps |
| CPU time | 0.37 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:20:50 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958060437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 17.prim_sync_alert.2958060437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/17.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.3151704770 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 8430919 ps |
| CPU time | 0.39 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:20:50 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151704770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 18.prim_sync_alert.3151704770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/18.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.1083331375 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 10274907 ps |
| CPU time | 0.36 seconds |
| Started | Oct 02 04:20:48 PM UTC 24 |
| Finished | Oct 02 04:20:50 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083331375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 19.prim_sync_alert.1083331375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/19.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2732749995 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9060656 ps |
| CPU time | 0.34 seconds |
| Started | Oct 02 04:20:30 PM UTC 24 |
| Finished | Oct 02 04:20:31 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732749995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 2.prim_sync_alert.2732749995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/2.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.75446421 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8855661 ps |
| CPU time | 0.35 seconds |
| Started | Oct 02 04:20:32 PM UTC 24 |
| Finished | Oct 02 04:20:33 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75446421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.75446421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/3.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.3633889754 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10102503 ps |
| CPU time | 0.34 seconds |
| Started | Oct 02 04:20:34 PM UTC 24 |
| Finished | Oct 02 04:20:36 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633889754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.3633889754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/4.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.337348351 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9456082 ps |
| CPU time | 0.34 seconds |
| Started | Oct 02 04:20:37 PM UTC 24 |
| Finished | Oct 02 04:20:39 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337348351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 5.prim_sync_alert.337348351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/5.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2219272017 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9825833 ps |
| CPU time | 0.35 seconds |
| Started | Oct 02 04:20:40 PM UTC 24 |
| Finished | Oct 02 04:20:42 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219272017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 6.prim_sync_alert.2219272017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/6.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.3302058602 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9752651 ps |
| CPU time | 0.34 seconds |
| Started | Oct 02 04:20:42 PM UTC 24 |
| Finished | Oct 02 04:20:44 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302058602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.3302058602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/7.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.902795769 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8398715 ps |
| CPU time | 0.36 seconds |
| Started | Oct 02 04:20:46 PM UTC 24 |
| Finished | Oct 02 04:20:47 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902795769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 9.prim_sync_alert.902795769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/9.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1777871493 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27232301 ps |
| CPU time | 0.44 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777871493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1777871493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3075011159 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 28546808 ps |
| CPU time | 0.46 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075011159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3075011159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.840478500 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26007566 ps |
| CPU time | 0.41 seconds |
| Started | Oct 02 04:06:43 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840478500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.840478500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2102264050 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 25182079 ps |
| CPU time | 0.42 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102264050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2102264050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1494985565 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28261475 ps |
| CPU time | 0.45 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494985565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1494985565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2421663194 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28505355 ps |
| CPU time | 0.39 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421663194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2421663194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3925691223 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 28643813 ps |
| CPU time | 0.39 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925691223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3925691223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1451668612 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 26399669 ps |
| CPU time | 0.51 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451668612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1451668612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1871316344 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 28308321 ps |
| CPU time | 0.46 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871316344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1871316344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.459755057 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 29346618 ps |
| CPU time | 0.45 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459755057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.459755057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2683401619 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26442988 ps |
| CPU time | 0.41 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 154012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683401619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2683401619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.1692869051 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27130901 ps |
| CPU time | 0.46 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692869051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.1692869051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2275634570 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 28656374 ps |
| CPU time | 0.41 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275634570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2275634570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2608861110 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 28025482 ps |
| CPU time | 0.48 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608861110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2608861110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1574305916 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26878787 ps |
| CPU time | 0.44 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574305916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1574305916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1629879925 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28515740 ps |
| CPU time | 0.44 seconds |
| Started | Oct 02 04:06:42 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629879925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1629879925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1089037138 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28183451 ps |
| CPU time | 0.45 seconds |
| Started | Oct 02 04:06:43 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089037138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1089037138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1964491465 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27235306 ps |
| CPU time | 0.39 seconds |
| Started | Oct 02 04:06:43 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964491465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1964491465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1146746844 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26252372 ps |
| CPU time | 0.5 seconds |
| Started | Oct 02 04:06:43 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146746844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1146746844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3224946701 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28953946 ps |
| CPU time | 0.4 seconds |
| Started | Oct 02 04:06:43 PM UTC 24 |
| Finished | Oct 02 04:06:44 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224946701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3224946701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |