| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.53 | 88.53 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.3934761984 |
| 91.66 | 3.13 | 100.00 | 0.00 | 91.67 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.3493435090 |
| 93.76 | 2.11 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 83.72 | 6.98 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1712101539 |
| 94.50 | 0.73 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 2.33 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3434620248 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3596299127 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3942724483 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.479084692 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2383826618 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1975497886 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1388550708 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1492233921 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.1557017520 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.3406633010 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1674918306 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2620922571 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.3845685782 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.4091878578 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.1960795165 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.4133740850 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1994259284 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3362047062 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.780967958 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1970357286 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.2930385045 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2144278980 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.2167450566 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2624621068 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.1592824918 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3807240181 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2963228367 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2536373143 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1569249716 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.1896205693 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2872699320 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2142424758 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3378640468 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.4222105490 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1889019379 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.3684117275 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3985003388 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3964303130 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.1909011374 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3783287744 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.175881640 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.2034479461 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.4174748027 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.3263649003 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.4033723147 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3753963933 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.1244027942 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.806483964 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.3937642476 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.2207433512 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3669280906 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.4068962322 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.2046060681 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.252961891 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.1923176057 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.4003749135 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1755377005 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1264134919 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.203106950 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3673617201 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2751147556 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2107312666 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2625544020 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2079940309 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.362868928 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.362586542 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1520048043 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2527796340 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3868415574 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.575464551 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.352087691 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2364183529 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3460726477 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2835291885 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3190303636 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.398076385 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.479084692 | Oct 09 10:23:37 AM UTC 24 | Oct 09 10:23:40 AM UTC 24 | 11741161 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.4091878578 | Oct 09 10:23:37 AM UTC 24 | Oct 09 10:23:40 AM UTC 24 | 11571285 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.1960795165 | Oct 09 10:23:37 AM UTC 24 | Oct 09 10:23:40 AM UTC 24 | 10940777 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3362047062 | Oct 09 10:23:38 AM UTC 24 | Oct 09 10:23:40 AM UTC 24 | 11532094 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1994259284 | Oct 09 10:23:37 AM UTC 24 | Oct 09 10:23:40 AM UTC 24 | 10840541 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.4133740850 | Oct 09 10:23:37 AM UTC 24 | Oct 09 10:23:40 AM UTC 24 | 11450514 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.3845685782 | Oct 09 10:23:42 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 10927720 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1674918306 | Oct 09 10:23:42 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 11813912 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.780967958 | Oct 09 10:23:41 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 10350652 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.3934761984 | Oct 09 10:23:41 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 11567407 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2383826618 | Oct 09 10:23:41 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 11442596 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1970357286 | Oct 09 10:23:41 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 11551755 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1492233921 | Oct 09 10:23:41 AM UTC 24 | Oct 09 10:23:46 AM UTC 24 | 12942758 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1975497886 | Oct 09 10:23:41 AM UTC 24 | Oct 09 10:23:46 AM UTC 24 | 10806021 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.1557017520 | Oct 09 10:23:41 AM UTC 24 | Oct 09 10:23:46 AM UTC 24 | 10033717 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1388550708 | Oct 09 10:23:41 AM UTC 24 | Oct 09 10:23:46 AM UTC 24 | 10566557 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.3406633010 | Oct 09 10:23:42 AM UTC 24 | Oct 09 10:23:50 AM UTC 24 | 10127495 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2620922571 | Oct 09 10:23:42 AM UTC 24 | Oct 09 10:23:50 AM UTC 24 | 10746168 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3434620248 | Oct 09 10:23:36 AM UTC 24 | Oct 09 10:23:51 AM UTC 24 | 11312457 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.2930385045 | Oct 09 10:23:42 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 30543198 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3378640468 | Oct 09 10:23:42 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 29289169 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2144278980 | Oct 09 10:23:42 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 27538601 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1712101539 | Oct 09 10:23:42 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 30443886 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.4222105490 | Oct 09 10:23:42 AM UTC 24 | Oct 09 10:23:45 AM UTC 24 | 29523992 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3985003388 | Oct 09 10:23:46 AM UTC 24 | Oct 09 10:23:50 AM UTC 24 | 30566485 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.3684117275 | Oct 09 10:23:45 AM UTC 24 | Oct 09 10:23:50 AM UTC 24 | 31611062 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1889019379 | Oct 09 10:23:45 AM UTC 24 | Oct 09 10:23:50 AM UTC 24 | 30719526 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.2167450566 | Oct 09 10:23:46 AM UTC 24 | Oct 09 10:23:50 AM UTC 24 | 30865712 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2624621068 | Oct 09 10:23:46 AM UTC 24 | Oct 09 10:23:50 AM UTC 24 | 30814798 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3964303130 | Oct 09 10:23:46 AM UTC 24 | Oct 09 10:23:51 AM UTC 24 | 33167200 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.1909011374 | Oct 09 10:23:46 AM UTC 24 | Oct 09 10:23:51 AM UTC 24 | 29275704 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2963228367 | Oct 09 10:23:47 AM UTC 24 | Oct 09 10:23:51 AM UTC 24 | 30812990 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.1592824918 | Oct 09 10:23:47 AM UTC 24 | Oct 09 10:23:51 AM UTC 24 | 30318331 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3807240181 | Oct 09 10:23:47 AM UTC 24 | Oct 09 10:23:52 AM UTC 24 | 30512669 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2536373143 | Oct 09 10:23:47 AM UTC 24 | Oct 09 10:23:52 AM UTC 24 | 31873114 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2142424758 | Oct 09 10:23:47 AM UTC 24 | Oct 09 10:23:52 AM UTC 24 | 31521169 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2872699320 | Oct 09 10:23:47 AM UTC 24 | Oct 09 10:23:52 AM UTC 24 | 28606801 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.1896205693 | Oct 09 10:23:47 AM UTC 24 | Oct 09 10:23:52 AM UTC 24 | 28974031 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1569249716 | Oct 09 10:23:47 AM UTC 24 | Oct 09 10:23:52 AM UTC 24 | 30338338 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3783287744 | Oct 09 02:32:40 PM UTC 24 | Oct 09 02:32:41 PM UTC 24 | 9765925 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3669280906 | Oct 09 02:32:40 PM UTC 24 | Oct 09 02:32:41 PM UTC 24 | 8682987 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.175881640 | Oct 09 02:32:40 PM UTC 24 | Oct 09 02:32:41 PM UTC 24 | 8437081 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.4068962322 | Oct 09 02:32:40 PM UTC 24 | Oct 09 02:32:41 PM UTC 24 | 9914238 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.3493435090 | Oct 09 02:32:42 PM UTC 24 | Oct 09 02:32:43 PM UTC 24 | 8698881 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.2046060681 | Oct 09 02:32:42 PM UTC 24 | Oct 09 02:32:43 PM UTC 24 | 9491464 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.252961891 | Oct 09 02:32:42 PM UTC 24 | Oct 09 02:32:43 PM UTC 24 | 8689183 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.1923176057 | Oct 09 02:32:42 PM UTC 24 | Oct 09 02:32:43 PM UTC 24 | 8294428 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1755377005 | Oct 09 02:32:42 PM UTC 24 | Oct 09 02:32:43 PM UTC 24 | 9115966 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.4003749135 | Oct 09 02:32:42 PM UTC 24 | Oct 09 02:32:44 PM UTC 24 | 8954144 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3596299127 | Oct 09 02:32:42 PM UTC 24 | Oct 09 02:32:44 PM UTC 24 | 9075366 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.4174748027 | Oct 09 02:32:42 PM UTC 24 | Oct 09 02:32:44 PM UTC 24 | 9064650 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.2034479461 | Oct 09 02:32:42 PM UTC 24 | Oct 09 02:32:44 PM UTC 24 | 9950602 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.3263649003 | Oct 09 02:32:44 PM UTC 24 | Oct 09 02:32:46 PM UTC 24 | 9396285 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.4033723147 | Oct 09 02:32:45 PM UTC 24 | Oct 09 02:32:47 PM UTC 24 | 8872581 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.1244027942 | Oct 09 02:32:45 PM UTC 24 | Oct 09 02:32:47 PM UTC 24 | 8960924 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3753963933 | Oct 09 02:32:45 PM UTC 24 | Oct 09 02:32:47 PM UTC 24 | 7749344 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.3937642476 | Oct 09 02:32:45 PM UTC 24 | Oct 09 02:32:47 PM UTC 24 | 8954693 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.806483964 | Oct 09 02:32:45 PM UTC 24 | Oct 09 02:32:47 PM UTC 24 | 8926143 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.2207433512 | Oct 09 02:32:45 PM UTC 24 | Oct 09 02:32:47 PM UTC 24 | 8935055 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.203106950 | Oct 09 02:32:46 PM UTC 24 | Oct 09 02:32:47 PM UTC 24 | 28005319 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1264134919 | Oct 09 02:32:46 PM UTC 24 | Oct 09 02:32:47 PM UTC 24 | 27447794 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3868415574 | Oct 09 02:32:46 PM UTC 24 | Oct 09 02:32:47 PM UTC 24 | 28930517 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.352087691 | Oct 09 02:32:47 PM UTC 24 | Oct 09 02:32:48 PM UTC 24 | 29462092 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.575464551 | Oct 09 02:32:47 PM UTC 24 | Oct 09 02:32:48 PM UTC 24 | 26429033 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2364183529 | Oct 09 02:32:47 PM UTC 24 | Oct 09 02:32:49 PM UTC 24 | 26427487 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3460726477 | Oct 09 02:32:49 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 28521950 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2835291885 | Oct 09 02:32:49 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 28712214 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3190303636 | Oct 09 02:32:49 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 25244537 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.398076385 | Oct 09 02:32:49 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 27979820 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3942724483 | Oct 09 02:32:49 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 29110294 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2751147556 | Oct 09 02:32:49 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 25735272 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3673617201 | Oct 09 02:32:49 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 27277036 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2107312666 | Oct 09 02:32:49 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 25978658 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2625544020 | Oct 09 02:32:50 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 27470854 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2079940309 | Oct 09 02:32:50 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 28402911 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.362586542 | Oct 09 02:32:50 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 27386173 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.362868928 | Oct 09 02:32:50 PM UTC 24 | Oct 09 02:32:51 PM UTC 24 | 26285040 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2527796340 | Oct 09 02:32:52 PM UTC 24 | Oct 09 02:32:54 PM UTC 24 | 28835662 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1520048043 | Oct 09 02:32:52 PM UTC 24 | Oct 09 02:32:54 PM UTC 24 | 27868120 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.3934761984 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11567407 ps |
| CPU time | 0.54 seconds |
| Started | Oct 09 10:23:41 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934761984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 7.prim_async_alert.3934761984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/7.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.3493435090 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8698881 ps |
| CPU time | 0.59 seconds |
| Started | Oct 09 02:32:42 PM UTC 24 |
| Finished | Oct 09 02:32:43 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493435090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.3493435090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/4.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1712101539 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30443886 ps |
| CPU time | 0.49 seconds |
| Started | Oct 09 10:23:42 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712101539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 4.prim_async_fatal_alert.1712101539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3434620248 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11312457 ps |
| CPU time | 0.4 seconds |
| Started | Oct 09 10:23:36 AM UTC 24 |
| Finished | Oct 09 10:23:51 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434620248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.prim_async_alert.3434620248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/0.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.3596299127 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9075366 ps |
| CPU time | 0.59 seconds |
| Started | Oct 09 02:32:42 PM UTC 24 |
| Finished | Oct 09 02:32:44 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596299127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.3596299127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/11.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3942724483 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 29110294 ps |
| CPU time | 0.57 seconds |
| Started | Oct 09 02:32:49 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942724483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3942724483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.479084692 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11741161 ps |
| CPU time | 0.42 seconds |
| Started | Oct 09 10:23:37 AM UTC 24 |
| Finished | Oct 09 10:23:40 AM UTC 24 |
| Peak memory | 155220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479084692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.prim_async_alert.479084692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/1.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.2383826618 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11442596 ps |
| CPU time | 0.45 seconds |
| Started | Oct 09 10:23:41 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383826618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 10.prim_async_alert.2383826618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/10.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1975497886 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10806021 ps |
| CPU time | 0.51 seconds |
| Started | Oct 09 10:23:41 AM UTC 24 |
| Finished | Oct 09 10:23:46 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975497886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 11.prim_async_alert.1975497886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/11.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.1388550708 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10566557 ps |
| CPU time | 0.5 seconds |
| Started | Oct 09 10:23:41 AM UTC 24 |
| Finished | Oct 09 10:23:46 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388550708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 12.prim_async_alert.1388550708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/12.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1492233921 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12942758 ps |
| CPU time | 0.5 seconds |
| Started | Oct 09 10:23:41 AM UTC 24 |
| Finished | Oct 09 10:23:46 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492233921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.prim_async_alert.1492233921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/13.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.1557017520 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10033717 ps |
| CPU time | 0.51 seconds |
| Started | Oct 09 10:23:41 AM UTC 24 |
| Finished | Oct 09 10:23:46 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557017520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.1557017520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/14.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.3406633010 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10127495 ps |
| CPU time | 0.51 seconds |
| Started | Oct 09 10:23:42 AM UTC 24 |
| Finished | Oct 09 10:23:50 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406633010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.3406633010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/15.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.1674918306 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11813912 ps |
| CPU time | 0.49 seconds |
| Started | Oct 09 10:23:42 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674918306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.1674918306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/17.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2620922571 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10746168 ps |
| CPU time | 0.48 seconds |
| Started | Oct 09 10:23:42 AM UTC 24 |
| Finished | Oct 09 10:23:50 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620922571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.prim_async_alert.2620922571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/18.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.3845685782 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 10927720 ps |
| CPU time | 0.39 seconds |
| Started | Oct 09 10:23:42 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845685782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 19.prim_async_alert.3845685782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/19.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.4091878578 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11571285 ps |
| CPU time | 0.4 seconds |
| Started | Oct 09 10:23:37 AM UTC 24 |
| Finished | Oct 09 10:23:40 AM UTC 24 |
| Peak memory | 155216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091878578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.prim_async_alert.4091878578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/2.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.1960795165 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10940777 ps |
| CPU time | 0.45 seconds |
| Started | Oct 09 10:23:37 AM UTC 24 |
| Finished | Oct 09 10:23:40 AM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960795165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 3.prim_async_alert.1960795165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/3.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.4133740850 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11450514 ps |
| CPU time | 0.43 seconds |
| Started | Oct 09 10:23:37 AM UTC 24 |
| Finished | Oct 09 10:23:40 AM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133740850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 4.prim_async_alert.4133740850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/4.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.1994259284 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10840541 ps |
| CPU time | 0.4 seconds |
| Started | Oct 09 10:23:37 AM UTC 24 |
| Finished | Oct 09 10:23:40 AM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994259284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 5.prim_async_alert.1994259284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/5.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.3362047062 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11532094 ps |
| CPU time | 0.36 seconds |
| Started | Oct 09 10:23:38 AM UTC 24 |
| Finished | Oct 09 10:23:40 AM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362047062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.prim_async_alert.3362047062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/6.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.780967958 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10350652 ps |
| CPU time | 0.54 seconds |
| Started | Oct 09 10:23:41 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780967958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 8.prim_async_alert.780967958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/8.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1970357286 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11551755 ps |
| CPU time | 0.57 seconds |
| Started | Oct 09 10:23:41 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970357286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.1970357286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/9.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.2930385045 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 30543198 ps |
| CPU time | 0.46 seconds |
| Started | Oct 09 10:23:42 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930385045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 0.prim_async_fatal_alert.2930385045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.2144278980 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 27538601 ps |
| CPU time | 0.41 seconds |
| Started | Oct 09 10:23:42 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144278980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.2144278980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.2167450566 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30865712 ps |
| CPU time | 0.36 seconds |
| Started | Oct 09 10:23:46 AM UTC 24 |
| Finished | Oct 09 10:23:50 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167450566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.2167450566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2624621068 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 30814798 ps |
| CPU time | 0.42 seconds |
| Started | Oct 09 10:23:46 AM UTC 24 |
| Finished | Oct 09 10:23:50 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624621068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.2624621068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.1592824918 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30318331 ps |
| CPU time | 0.53 seconds |
| Started | Oct 09 10:23:47 AM UTC 24 |
| Finished | Oct 09 10:23:51 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592824918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 12.prim_async_fatal_alert.1592824918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3807240181 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30512669 ps |
| CPU time | 0.5 seconds |
| Started | Oct 09 10:23:47 AM UTC 24 |
| Finished | Oct 09 10:23:52 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807240181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 13.prim_async_fatal_alert.3807240181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.2963228367 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30812990 ps |
| CPU time | 0.46 seconds |
| Started | Oct 09 10:23:47 AM UTC 24 |
| Finished | Oct 09 10:23:51 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963228367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 14.prim_async_fatal_alert.2963228367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2536373143 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 31873114 ps |
| CPU time | 0.51 seconds |
| Started | Oct 09 10:23:47 AM UTC 24 |
| Finished | Oct 09 10:23:52 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536373143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.2536373143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1569249716 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30338338 ps |
| CPU time | 0.53 seconds |
| Started | Oct 09 10:23:47 AM UTC 24 |
| Finished | Oct 09 10:23:52 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569249716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 16.prim_async_fatal_alert.1569249716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.1896205693 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 28974031 ps |
| CPU time | 0.49 seconds |
| Started | Oct 09 10:23:47 AM UTC 24 |
| Finished | Oct 09 10:23:52 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896205693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 17.prim_async_fatal_alert.1896205693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2872699320 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 28606801 ps |
| CPU time | 0.5 seconds |
| Started | Oct 09 10:23:47 AM UTC 24 |
| Finished | Oct 09 10:23:52 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872699320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 18.prim_async_fatal_alert.2872699320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2142424758 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 31521169 ps |
| CPU time | 0.44 seconds |
| Started | Oct 09 10:23:47 AM UTC 24 |
| Finished | Oct 09 10:23:52 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142424758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 19.prim_async_fatal_alert.2142424758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.3378640468 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29289169 ps |
| CPU time | 0.45 seconds |
| Started | Oct 09 10:23:42 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378640468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.3378640468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.4222105490 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 29523992 ps |
| CPU time | 0.44 seconds |
| Started | Oct 09 10:23:42 AM UTC 24 |
| Finished | Oct 09 10:23:45 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222105490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 3.prim_async_fatal_alert.4222105490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1889019379 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 30719526 ps |
| CPU time | 0.56 seconds |
| Started | Oct 09 10:23:45 AM UTC 24 |
| Finished | Oct 09 10:23:50 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889019379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 5.prim_async_fatal_alert.1889019379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.3684117275 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 31611062 ps |
| CPU time | 0.55 seconds |
| Started | Oct 09 10:23:45 AM UTC 24 |
| Finished | Oct 09 10:23:50 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684117275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 6.prim_async_fatal_alert.3684117275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3985003388 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 30566485 ps |
| CPU time | 0.48 seconds |
| Started | Oct 09 10:23:46 AM UTC 24 |
| Finished | Oct 09 10:23:50 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985003388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 7.prim_async_fatal_alert.3985003388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.3964303130 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 33167200 ps |
| CPU time | 0.53 seconds |
| Started | Oct 09 10:23:46 AM UTC 24 |
| Finished | Oct 09 10:23:51 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964303130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 8.prim_async_fatal_alert.3964303130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.1909011374 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29275704 ps |
| CPU time | 0.57 seconds |
| Started | Oct 09 10:23:46 AM UTC 24 |
| Finished | Oct 09 10:23:51 AM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909011374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 9.prim_async_fatal_alert.1909011374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.3783287744 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9765925 ps |
| CPU time | 0.64 seconds |
| Started | Oct 09 02:32:40 PM UTC 24 |
| Finished | Oct 09 02:32:41 PM UTC 24 |
| Peak memory | 154608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783287744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.3783287744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/0.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.175881640 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8437081 ps |
| CPU time | 0.59 seconds |
| Started | Oct 09 02:32:40 PM UTC 24 |
| Finished | Oct 09 02:32:41 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175881640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 1.prim_sync_alert.175881640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/1.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.2034479461 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9950602 ps |
| CPU time | 0.58 seconds |
| Started | Oct 09 02:32:42 PM UTC 24 |
| Finished | Oct 09 02:32:44 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034479461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.2034479461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/10.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.4174748027 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9064650 ps |
| CPU time | 0.46 seconds |
| Started | Oct 09 02:32:42 PM UTC 24 |
| Finished | Oct 09 02:32:44 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174748027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.4174748027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/12.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.3263649003 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9396285 ps |
| CPU time | 0.61 seconds |
| Started | Oct 09 02:32:44 PM UTC 24 |
| Finished | Oct 09 02:32:46 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263649003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 13.prim_sync_alert.3263649003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/13.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.4033723147 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8872581 ps |
| CPU time | 0.56 seconds |
| Started | Oct 09 02:32:45 PM UTC 24 |
| Finished | Oct 09 02:32:47 PM UTC 24 |
| Peak memory | 154536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033723147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.4033723147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/14.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3753963933 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 7749344 ps |
| CPU time | 0.59 seconds |
| Started | Oct 09 02:32:45 PM UTC 24 |
| Finished | Oct 09 02:32:47 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753963933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.3753963933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/15.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.1244027942 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8960924 ps |
| CPU time | 0.55 seconds |
| Started | Oct 09 02:32:45 PM UTC 24 |
| Finished | Oct 09 02:32:47 PM UTC 24 |
| Peak memory | 154536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244027942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 16.prim_sync_alert.1244027942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/16.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.806483964 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8926143 ps |
| CPU time | 0.62 seconds |
| Started | Oct 09 02:32:45 PM UTC 24 |
| Finished | Oct 09 02:32:47 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806483964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 17.prim_sync_alert.806483964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/17.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.3937642476 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8954693 ps |
| CPU time | 0.6 seconds |
| Started | Oct 09 02:32:45 PM UTC 24 |
| Finished | Oct 09 02:32:47 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937642476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 18.prim_sync_alert.3937642476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/18.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.2207433512 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8935055 ps |
| CPU time | 0.6 seconds |
| Started | Oct 09 02:32:45 PM UTC 24 |
| Finished | Oct 09 02:32:47 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207433512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 19.prim_sync_alert.2207433512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/19.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.3669280906 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8682987 ps |
| CPU time | 0.49 seconds |
| Started | Oct 09 02:32:40 PM UTC 24 |
| Finished | Oct 09 02:32:41 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669280906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 2.prim_sync_alert.3669280906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/2.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.4068962322 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9914238 ps |
| CPU time | 0.55 seconds |
| Started | Oct 09 02:32:40 PM UTC 24 |
| Finished | Oct 09 02:32:41 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068962322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 3.prim_sync_alert.4068962322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/3.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.2046060681 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9491464 ps |
| CPU time | 0.61 seconds |
| Started | Oct 09 02:32:42 PM UTC 24 |
| Finished | Oct 09 02:32:43 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046060681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 5.prim_sync_alert.2046060681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/5.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.252961891 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8689183 ps |
| CPU time | 0.63 seconds |
| Started | Oct 09 02:32:42 PM UTC 24 |
| Finished | Oct 09 02:32:43 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252961891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 6.prim_sync_alert.252961891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/6.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.1923176057 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8294428 ps |
| CPU time | 0.56 seconds |
| Started | Oct 09 02:32:42 PM UTC 24 |
| Finished | Oct 09 02:32:43 PM UTC 24 |
| Peak memory | 154476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923176057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.1923176057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/7.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.4003749135 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8954144 ps |
| CPU time | 0.62 seconds |
| Started | Oct 09 02:32:42 PM UTC 24 |
| Finished | Oct 09 02:32:44 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003749135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.4003749135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/8.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1755377005 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9115966 ps |
| CPU time | 0.61 seconds |
| Started | Oct 09 02:32:42 PM UTC 24 |
| Finished | Oct 09 02:32:43 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755377005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.1755377005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/9.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.1264134919 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27447794 ps |
| CPU time | 0.63 seconds |
| Started | Oct 09 02:32:46 PM UTC 24 |
| Finished | Oct 09 02:32:47 PM UTC 24 |
| Peak memory | 153908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264134919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.1264134919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.203106950 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 28005319 ps |
| CPU time | 0.57 seconds |
| Started | Oct 09 02:32:46 PM UTC 24 |
| Finished | Oct 09 02:32:47 PM UTC 24 |
| Peak memory | 154052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203106950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.203106950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3673617201 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27277036 ps |
| CPU time | 0.6 seconds |
| Started | Oct 09 02:32:49 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673617201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3673617201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2751147556 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 25735272 ps |
| CPU time | 0.59 seconds |
| Started | Oct 09 02:32:49 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751147556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2751147556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2107312666 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 25978658 ps |
| CPU time | 0.59 seconds |
| Started | Oct 09 02:32:49 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107312666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2107312666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2625544020 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27470854 ps |
| CPU time | 0.59 seconds |
| Started | Oct 09 02:32:50 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625544020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2625544020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2079940309 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28402911 ps |
| CPU time | 0.62 seconds |
| Started | Oct 09 02:32:50 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079940309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2079940309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.362868928 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 26285040 ps |
| CPU time | 0.67 seconds |
| Started | Oct 09 02:32:50 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362868928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.362868928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.362586542 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 27386173 ps |
| CPU time | 0.6 seconds |
| Started | Oct 09 02:32:50 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362586542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.362586542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1520048043 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27868120 ps |
| CPU time | 0.59 seconds |
| Started | Oct 09 02:32:52 PM UTC 24 |
| Finished | Oct 09 02:32:54 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520048043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1520048043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2527796340 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 28835662 ps |
| CPU time | 0.64 seconds |
| Started | Oct 09 02:32:52 PM UTC 24 |
| Finished | Oct 09 02:32:54 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527796340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2527796340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3868415574 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 28930517 ps |
| CPU time | 0.62 seconds |
| Started | Oct 09 02:32:46 PM UTC 24 |
| Finished | Oct 09 02:32:47 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868415574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3868415574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.575464551 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26429033 ps |
| CPU time | 0.64 seconds |
| Started | Oct 09 02:32:47 PM UTC 24 |
| Finished | Oct 09 02:32:48 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575464551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.575464551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.352087691 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 29462092 ps |
| CPU time | 0.56 seconds |
| Started | Oct 09 02:32:47 PM UTC 24 |
| Finished | Oct 09 02:32:48 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352087691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.352087691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2364183529 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26427487 ps |
| CPU time | 0.66 seconds |
| Started | Oct 09 02:32:47 PM UTC 24 |
| Finished | Oct 09 02:32:49 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364183529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2364183529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3460726477 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28521950 ps |
| CPU time | 0.61 seconds |
| Started | Oct 09 02:32:49 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460726477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3460726477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2835291885 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28712214 ps |
| CPU time | 0.6 seconds |
| Started | Oct 09 02:32:49 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835291885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2835291885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.3190303636 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 25244537 ps |
| CPU time | 0.61 seconds |
| Started | Oct 09 02:32:49 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190303636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3190303636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.398076385 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27979820 ps |
| CPU time | 0.64 seconds |
| Started | Oct 09 02:32:49 PM UTC 24 |
| Finished | Oct 09 02:32:51 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398076385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.398076385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |