| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.08 | 88.08 | 100.00 | 100.00 | 93.75 | 93.75 | 96.43 | 96.43 | 75.00 | 75.00 | 95.83 | 95.83 | 67.44 | 67.44 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2776245690 |
| 91.80 | 3.72 | 100.00 | 0.00 | 93.75 | 0.00 | 96.43 | 0.00 | 85.71 | 10.71 | 95.83 | 0.00 | 79.07 | 11.63 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.3973755161 |
| 94.25 | 2.45 | 100.00 | 0.00 | 97.92 | 4.17 | 100.00 | 3.57 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.2563490544 |
| 94.85 | 0.60 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2236407065 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2461162317 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3122606719 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.242214063 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1633203704 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.981315737 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.1099631218 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.2609116721 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.801560671 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2437182844 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.3904831411 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2744995224 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.1871267192 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1241839187 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.3053241705 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2214501917 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.518044966 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.3517925585 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3781920276 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1968064025 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1251789042 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.174437945 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.107079797 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.187711238 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2276827014 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1292129706 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2517906364 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.188292640 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2218574068 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1137960872 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1960856714 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1004108888 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.4158963691 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.354518390 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.16445894 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1879405700 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.771905749 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.569024883 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3557213898 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.953908314 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.234442445 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.311526789 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.4053636896 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1025596416 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2711475918 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.4036780553 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.1195805208 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.1650214715 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.1748922251 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.4289074827 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2698685895 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.1705450564 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2595230418 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.2683632374 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4120853547 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1185904592 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4010757864 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3336601520 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1825301937 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.587609557 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1107322008 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3668051246 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.231618718 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3238068356 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2859594947 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.671689129 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1786071512 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3395665470 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2218378203 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2924795888 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2401579593 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2955701023 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2578104525 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1954053465 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2461162317 | Oct 11 09:22:57 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 11009906 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3122606719 | Oct 11 09:22:57 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 10463142 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2744995224 | Oct 11 09:22:57 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 12243135 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.1871267192 | Oct 11 09:22:57 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 11556917 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.3053241705 | Oct 11 09:22:57 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 11391506 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2214501917 | Oct 11 09:22:57 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 10629960 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1241839187 | Oct 11 09:22:57 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 10920102 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.518044966 | Oct 11 09:22:57 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 11010417 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2776245690 | Oct 11 09:22:58 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 11219690 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.242214063 | Oct 11 09:22:58 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 11206862 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1633203704 | Oct 11 09:22:58 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 10498416 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.981315737 | Oct 11 09:22:58 PM UTC 24 | Oct 11 09:22:59 PM UTC 24 | 12815238 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.1099631218 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:00 PM UTC 24 | 10526409 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.801560671 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:00 PM UTC 24 | 10669461 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2236407065 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:00 PM UTC 24 | 11710844 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2437182844 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:00 PM UTC 24 | 11127673 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.2609116721 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:00 PM UTC 24 | 11026542 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.3904831411 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:00 PM UTC 24 | 10293198 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3781920276 | Oct 11 11:44:07 PM UTC 24 | Oct 11 11:44:08 PM UTC 24 | 30184351 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.3517925585 | Oct 11 11:44:07 PM UTC 24 | Oct 11 11:44:08 PM UTC 24 | 30340380 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1137960872 | Oct 11 11:44:07 PM UTC 24 | Oct 11 11:44:09 PM UTC 24 | 28941951 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1960856714 | Oct 11 11:44:09 PM UTC 24 | Oct 11 11:44:10 PM UTC 24 | 30505081 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1004108888 | Oct 11 11:44:09 PM UTC 24 | Oct 11 11:44:10 PM UTC 24 | 30277610 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.4158963691 | Oct 11 11:44:09 PM UTC 24 | Oct 11 11:44:10 PM UTC 24 | 27521064 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.2563490544 | Oct 11 11:44:09 PM UTC 24 | Oct 11 11:44:10 PM UTC 24 | 29509410 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.354518390 | Oct 11 11:44:10 PM UTC 24 | Oct 11 11:44:11 PM UTC 24 | 29868944 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.16445894 | Oct 11 11:44:10 PM UTC 24 | Oct 11 11:44:11 PM UTC 24 | 31801590 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1968064025 | Oct 11 11:44:10 PM UTC 24 | Oct 11 11:44:11 PM UTC 24 | 32304394 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1251789042 | Oct 11 11:44:10 PM UTC 24 | Oct 11 11:44:11 PM UTC 24 | 29111032 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.187711238 | Oct 11 11:44:11 PM UTC 24 | Oct 11 11:44:13 PM UTC 24 | 29840049 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.107079797 | Oct 11 11:44:11 PM UTC 24 | Oct 11 11:44:13 PM UTC 24 | 30801924 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2276827014 | Oct 11 11:44:11 PM UTC 24 | Oct 11 11:44:13 PM UTC 24 | 31116317 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.174437945 | Oct 11 11:44:11 PM UTC 24 | Oct 11 11:44:13 PM UTC 24 | 32936106 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1292129706 | Oct 11 11:44:11 PM UTC 24 | Oct 11 11:44:13 PM UTC 24 | 30112492 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2517906364 | Oct 11 11:44:11 PM UTC 24 | Oct 11 11:44:13 PM UTC 24 | 29934703 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.188292640 | Oct 11 11:44:13 PM UTC 24 | Oct 11 11:44:14 PM UTC 24 | 31031635 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2218574068 | Oct 11 11:44:13 PM UTC 24 | Oct 11 11:44:15 PM UTC 24 | 30724184 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.3973755161 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:00 PM UTC 24 | 9370782 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1879405700 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:00 PM UTC 24 | 8826648 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.1195805208 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:01 PM UTC 24 | 9299548 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.1650214715 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:01 PM UTC 24 | 9185291 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2698685895 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:01 PM UTC 24 | 9569237 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.1748922251 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:01 PM UTC 24 | 9119475 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.4289074827 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:01 PM UTC 24 | 9165347 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.1705450564 | Oct 11 09:22:59 PM UTC 24 | Oct 11 09:23:01 PM UTC 24 | 9792608 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.771905749 | Oct 11 09:23:00 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 9205885 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2595230418 | Oct 11 09:23:00 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 8677756 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.2683632374 | Oct 11 09:23:00 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 8859997 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.569024883 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 9695643 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.953908314 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 8694375 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3557213898 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 9355514 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.234442445 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 10042412 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.311526789 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 9978647 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1025596416 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 8252605 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.4053636896 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 8777852 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2711475918 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 9715376 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.4036780553 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 9630557 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1185904592 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 26104893 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4120853547 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 27057191 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1786071512 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 27426797 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3395665470 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:02 PM UTC 24 | 28277378 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2578104525 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 27965636 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2924795888 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 27738560 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2218378203 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 27975412 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2955701023 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 26973484 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2401579593 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 28592921 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4010757864 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 28210817 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1954053465 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 28391558 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1825301937 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 24995932 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3668051246 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 27886575 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.587609557 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 26295028 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3336601520 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 27507294 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2859594947 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 26730020 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1107322008 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 26905259 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3238068356 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 27445859 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.231618718 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 25758866 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.671689129 | Oct 11 09:23:01 PM UTC 24 | Oct 11 09:23:03 PM UTC 24 | 26707760 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2776245690 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11219690 ps |
| CPU time | 0.41 seconds |
| Started | Oct 11 09:22:58 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776245690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.prim_async_alert.2776245690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/8.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.3973755161 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9370782 ps |
| CPU time | 0.36 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:00 PM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973755161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 1.prim_sync_alert.3973755161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/1.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.2563490544 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 29509410 ps |
| CPU time | 0.5 seconds |
| Started | Oct 11 11:44:09 PM UTC 24 |
| Finished | Oct 11 11:44:10 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563490544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 7.prim_async_fatal_alert.2563490544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.2236407065 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11710844 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:00 PM UTC 24 |
| Peak memory | 155136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236407065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.prim_async_alert.2236407065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/15.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.2461162317 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11009906 ps |
| CPU time | 0.43 seconds |
| Started | Oct 11 09:22:57 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461162317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.prim_async_alert.2461162317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/0.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.3122606719 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10463142 ps |
| CPU time | 0.39 seconds |
| Started | Oct 11 09:22:57 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122606719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.prim_async_alert.3122606719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/1.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.242214063 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11206862 ps |
| CPU time | 0.39 seconds |
| Started | Oct 11 09:22:58 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242214063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 10.prim_async_alert.242214063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/10.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1633203704 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10498416 ps |
| CPU time | 0.39 seconds |
| Started | Oct 11 09:22:58 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633203704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 11.prim_async_alert.1633203704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/11.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.981315737 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12815238 ps |
| CPU time | 0.4 seconds |
| Started | Oct 11 09:22:58 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981315737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 12.prim_async_alert.981315737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/12.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.1099631218 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10526409 ps |
| CPU time | 0.36 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:00 PM UTC 24 |
| Peak memory | 155132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099631218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.1099631218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/14.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.2609116721 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11026542 ps |
| CPU time | 0.37 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:00 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609116721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 16.prim_async_alert.2609116721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/16.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.801560671 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10669461 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:00 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801560671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 17.prim_async_alert.801560671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/17.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2437182844 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11127673 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:00 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437182844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.prim_async_alert.2437182844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/18.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.3904831411 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10293198 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:00 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904831411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 19.prim_async_alert.3904831411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/19.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.2744995224 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12243135 ps |
| CPU time | 0.43 seconds |
| Started | Oct 11 09:22:57 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744995224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.prim_async_alert.2744995224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/2.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.1871267192 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11556917 ps |
| CPU time | 0.39 seconds |
| Started | Oct 11 09:22:57 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871267192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 3.prim_async_alert.1871267192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/3.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.1241839187 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10920102 ps |
| CPU time | 0.46 seconds |
| Started | Oct 11 09:22:57 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241839187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 4.prim_async_alert.1241839187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/4.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.3053241705 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11391506 ps |
| CPU time | 0.42 seconds |
| Started | Oct 11 09:22:57 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053241705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 5.prim_async_alert.3053241705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/5.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.2214501917 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10629960 ps |
| CPU time | 0.43 seconds |
| Started | Oct 11 09:22:57 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214501917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.prim_async_alert.2214501917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/6.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.518044966 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11010417 ps |
| CPU time | 0.39 seconds |
| Started | Oct 11 09:22:57 PM UTC 24 |
| Finished | Oct 11 09:22:59 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518044966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 7.prim_async_alert.518044966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/7.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.3517925585 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30340380 ps |
| CPU time | 0.5 seconds |
| Started | Oct 11 11:44:07 PM UTC 24 |
| Finished | Oct 11 11:44:08 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517925585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 0.prim_async_fatal_alert.3517925585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3781920276 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 30184351 ps |
| CPU time | 0.48 seconds |
| Started | Oct 11 11:44:07 PM UTC 24 |
| Finished | Oct 11 11:44:08 PM UTC 24 |
| Peak memory | 155076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781920276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 1.prim_async_fatal_alert.3781920276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1968064025 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 32304394 ps |
| CPU time | 0.54 seconds |
| Started | Oct 11 11:44:10 PM UTC 24 |
| Finished | Oct 11 11:44:11 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968064025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.1968064025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.1251789042 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29111032 ps |
| CPU time | 0.53 seconds |
| Started | Oct 11 11:44:10 PM UTC 24 |
| Finished | Oct 11 11:44:11 PM UTC 24 |
| Peak memory | 155016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251789042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.1251789042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.174437945 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 32936106 ps |
| CPU time | 0.53 seconds |
| Started | Oct 11 11:44:11 PM UTC 24 |
| Finished | Oct 11 11:44:13 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174437945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 12.prim_async_fatal_alert.174437945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.107079797 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30801924 ps |
| CPU time | 0.52 seconds |
| Started | Oct 11 11:44:11 PM UTC 24 |
| Finished | Oct 11 11:44:13 PM UTC 24 |
| Peak memory | 154956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107079797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 13.prim_async_fatal_alert.107079797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.187711238 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29840049 ps |
| CPU time | 0.51 seconds |
| Started | Oct 11 11:44:11 PM UTC 24 |
| Finished | Oct 11 11:44:13 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187711238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 14.prim_async_fatal_alert.187711238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.2276827014 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 31116317 ps |
| CPU time | 0.51 seconds |
| Started | Oct 11 11:44:11 PM UTC 24 |
| Finished | Oct 11 11:44:13 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276827014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 15.prim_async_fatal_alert.2276827014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1292129706 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 30112492 ps |
| CPU time | 0.54 seconds |
| Started | Oct 11 11:44:11 PM UTC 24 |
| Finished | Oct 11 11:44:13 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292129706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 16.prim_async_fatal_alert.1292129706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.2517906364 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29934703 ps |
| CPU time | 0.51 seconds |
| Started | Oct 11 11:44:11 PM UTC 24 |
| Finished | Oct 11 11:44:13 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517906364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 17.prim_async_fatal_alert.2517906364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.188292640 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31031635 ps |
| CPU time | 0.52 seconds |
| Started | Oct 11 11:44:13 PM UTC 24 |
| Finished | Oct 11 11:44:14 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188292640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 18.prim_async_fatal_alert.188292640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2218574068 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30724184 ps |
| CPU time | 0.5 seconds |
| Started | Oct 11 11:44:13 PM UTC 24 |
| Finished | Oct 11 11:44:15 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218574068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 19.prim_async_fatal_alert.2218574068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1137960872 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 28941951 ps |
| CPU time | 0.51 seconds |
| Started | Oct 11 11:44:07 PM UTC 24 |
| Finished | Oct 11 11:44:09 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137960872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 3.prim_async_fatal_alert.1137960872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.1960856714 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30505081 ps |
| CPU time | 0.52 seconds |
| Started | Oct 11 11:44:09 PM UTC 24 |
| Finished | Oct 11 11:44:10 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960856714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 4.prim_async_fatal_alert.1960856714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1004108888 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30277610 ps |
| CPU time | 0.52 seconds |
| Started | Oct 11 11:44:09 PM UTC 24 |
| Finished | Oct 11 11:44:10 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004108888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 5.prim_async_fatal_alert.1004108888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.4158963691 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 27521064 ps |
| CPU time | 0.54 seconds |
| Started | Oct 11 11:44:09 PM UTC 24 |
| Finished | Oct 11 11:44:10 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158963691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 6.prim_async_fatal_alert.4158963691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.354518390 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 29868944 ps |
| CPU time | 0.55 seconds |
| Started | Oct 11 11:44:10 PM UTC 24 |
| Finished | Oct 11 11:44:11 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354518390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 8.prim_async_fatal_alert.354518390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.16445894 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 31801590 ps |
| CPU time | 0.53 seconds |
| Started | Oct 11 11:44:10 PM UTC 24 |
| Finished | Oct 11 11:44:11 PM UTC 24 |
| Peak memory | 154736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16445894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_l og /dev/null -cm_name 9.prim_async_fatal_alert.16445894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.1879405700 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8826648 ps |
| CPU time | 0.38 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:00 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879405700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 0.prim_sync_alert.1879405700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/0.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.771905749 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9205885 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:23:00 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771905749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 10.prim_sync_alert.771905749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/10.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.569024883 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9695643 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569024883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 11.prim_sync_alert.569024883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/11.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3557213898 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9355514 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557213898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.3557213898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/12.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.953908314 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8694375 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953908314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 13.prim_sync_alert.953908314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/13.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.234442445 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10042412 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234442445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 14.prim_sync_alert.234442445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/14.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.311526789 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9978647 ps |
| CPU time | 0.33 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311526789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 15.prim_sync_alert.311526789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/15.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.4053636896 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8777852 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053636896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 16.prim_sync_alert.4053636896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/16.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1025596416 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8252605 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025596416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 17.prim_sync_alert.1025596416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/17.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2711475918 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9715376 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711475918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 18.prim_sync_alert.2711475918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/18.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.4036780553 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9630557 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036780553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 19.prim_sync_alert.4036780553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/19.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.1195805208 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9299548 ps |
| CPU time | 0.36 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:01 PM UTC 24 |
| Peak memory | 153676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195805208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 2.prim_sync_alert.1195805208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/2.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.1650214715 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9185291 ps |
| CPU time | 0.37 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:01 PM UTC 24 |
| Peak memory | 153676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650214715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 3.prim_sync_alert.1650214715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/3.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.1748922251 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9119475 ps |
| CPU time | 0.37 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:01 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748922251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.1748922251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/4.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.4289074827 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9165347 ps |
| CPU time | 0.37 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:01 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289074827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 5.prim_sync_alert.4289074827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/5.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.2698685895 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9569237 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:01 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698685895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 6.prim_sync_alert.2698685895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/6.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.1705450564 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9792608 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:22:59 PM UTC 24 |
| Finished | Oct 11 09:23:01 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705450564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.1705450564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/7.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2595230418 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8677756 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:23:00 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595230418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.2595230418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/8.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.2683632374 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 8859997 ps |
| CPU time | 0.36 seconds |
| Started | Oct 11 09:23:00 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683632374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.2683632374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/9.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.4120853547 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 27057191 ps |
| CPU time | 0.36 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120853547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.4120853547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1185904592 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 26104893 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185904592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1185904592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4010757864 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28210817 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010757864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.4010757864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3336601520 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27507294 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336601520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3336601520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1825301937 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 24995932 ps |
| CPU time | 0.36 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825301937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1825301937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.587609557 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 26295028 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587609557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.587609557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1107322008 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26905259 ps |
| CPU time | 0.36 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 155264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107322008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1107322008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3668051246 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27886575 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668051246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3668051246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.231618718 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 25758866 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231618718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.231618718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3238068356 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27445859 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238068356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3238068356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.2859594947 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 26730020 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859594947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.2859594947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.671689129 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 26707760 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671689129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.671689129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1786071512 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 27426797 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786071512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1786071512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3395665470 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 28277378 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:02 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395665470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3395665470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2218378203 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27975412 ps |
| CPU time | 0.37 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218378203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2218378203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2924795888 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 27738560 ps |
| CPU time | 0.34 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924795888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2924795888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2401579593 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28592921 ps |
| CPU time | 0.36 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401579593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2401579593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2955701023 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26973484 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955701023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2955701023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2578104525 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27965636 ps |
| CPU time | 0.35 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578104525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2578104525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1954053465 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 28391558 ps |
| CPU time | 0.37 seconds |
| Started | Oct 11 09:23:01 PM UTC 24 |
| Finished | Oct 11 09:23:03 PM UTC 24 |
| Peak memory | 153848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954053465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1954053465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |