| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.92 | 88.92 | 100.00 | 100.00 | 91.67 | 91.67 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.1276866499 |
| 91.45 | 2.53 | 100.00 | 0.00 | 91.67 | 0.00 | 100.00 | 0.00 | 82.14 | 3.57 | 95.83 | 0.00 | 79.07 | 11.63 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.243640425 |
| 93.56 | 2.11 | 100.00 | 0.00 | 93.75 | 2.08 | 100.00 | 0.00 | 85.71 | 3.57 | 95.83 | 0.00 | 86.05 | 6.98 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2577109438 |
| 94.50 | 0.94 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1832377171 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.3037299040 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2224998962 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.294621593 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.3795747467 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1862123137 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.2563560451 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1963381199 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3213743028 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.809863937 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.1407681640 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3920823739 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2972370706 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.133348450 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.498094783 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.2182898042 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.704651722 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.3249747904 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.1326191390 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.587797642 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.4051081661 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1602179081 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.318775398 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2510647101 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.300617249 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3708416718 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.1500529407 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.871926508 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.4181875073 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.247872726 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2097361957 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2315999294 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2045141848 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.214779283 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.2336953508 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1522378883 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1640559877 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.953911772 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.1721991793 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1222194471 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.2988297251 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2267954931 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3236420668 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.429965726 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2053125612 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3994459283 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.438874951 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1953841320 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2007563562 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.826001620 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.979002438 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2068843288 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.3452329599 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3908327415 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.1152685703 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.2467030061 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2914486491 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.2677007335 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.874744383 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3867731686 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3306373133 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3136077988 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3160637291 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1485241555 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.457017257 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.512650353 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.897166666 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3036416367 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.875193872 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.785796880 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1355643152 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1000598084 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.906538932 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3910610715 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.600912614 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2820745661 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4219866077 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.1326191390 | Oct 14 06:14:22 PM UTC 24 | Oct 14 06:14:23 PM UTC 24 | 11119957 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.704651722 | Oct 14 06:14:22 PM UTC 24 | Oct 14 06:14:23 PM UTC 24 | 11425741 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.1276866499 | Oct 14 06:14:22 PM UTC 24 | Oct 14 06:14:23 PM UTC 24 | 12851862 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.2182898042 | Oct 14 06:14:22 PM UTC 24 | Oct 14 06:14:23 PM UTC 24 | 10723682 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.3249747904 | Oct 14 06:14:22 PM UTC 24 | Oct 14 06:14:23 PM UTC 24 | 11109294 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.498094783 | Oct 14 06:14:22 PM UTC 24 | Oct 14 06:14:23 PM UTC 24 | 12796974 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.294621593 | Oct 14 06:14:22 PM UTC 24 | Oct 14 06:14:23 PM UTC 24 | 10540939 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.587797642 | Oct 14 06:14:23 PM UTC 24 | Oct 14 06:14:24 PM UTC 24 | 11440455 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.3795747467 | Oct 14 06:14:24 PM UTC 24 | Oct 14 06:14:25 PM UTC 24 | 12061534 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1602179081 | Oct 14 06:14:24 PM UTC 24 | Oct 14 06:14:25 PM UTC 24 | 11131178 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.4051081661 | Oct 14 06:14:24 PM UTC 24 | Oct 14 06:14:25 PM UTC 24 | 12645741 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1862123137 | Oct 14 06:14:24 PM UTC 24 | Oct 14 06:14:25 PM UTC 24 | 11410531 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.2563560451 | Oct 14 06:14:24 PM UTC 24 | Oct 14 06:14:25 PM UTC 24 | 10600294 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1963381199 | Oct 14 06:14:24 PM UTC 24 | Oct 14 06:14:25 PM UTC 24 | 12256458 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3213743028 | Oct 14 06:14:24 PM UTC 24 | Oct 14 06:14:26 PM UTC 24 | 11830984 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.809863937 | Oct 14 06:14:25 PM UTC 24 | Oct 14 06:14:27 PM UTC 24 | 10835811 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.1407681640 | Oct 14 06:14:26 PM UTC 24 | Oct 14 06:14:28 PM UTC 24 | 10794981 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3920823739 | Oct 14 06:14:26 PM UTC 24 | Oct 14 06:14:28 PM UTC 24 | 10469695 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2972370706 | Oct 14 06:14:26 PM UTC 24 | Oct 14 06:14:28 PM UTC 24 | 12327552 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.133348450 | Oct 14 06:14:26 PM UTC 24 | Oct 14 06:14:28 PM UTC 24 | 11302213 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.3037299040 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 28798712 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2045141848 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 30890778 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2577109438 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 29152348 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.318775398 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 31029745 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1522378883 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 29067069 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.2336953508 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 29047239 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.214779283 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 28854936 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1640559877 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 30431870 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.953911772 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 31873614 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.1721991793 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 30901080 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1832377171 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 31105017 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.300617249 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 29005915 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.871926508 | Oct 14 06:01:02 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 30326153 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.1500529407 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 30336330 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2510647101 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 31952071 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3708416718 | Oct 14 06:01:01 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 29463356 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.247872726 | Oct 14 06:01:02 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 31174945 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.4181875073 | Oct 14 06:01:02 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 31366514 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2097361957 | Oct 14 06:01:02 PM UTC 24 | Oct 14 06:01:03 PM UTC 24 | 29132124 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2315999294 | Oct 14 06:01:13 PM UTC 24 | Oct 14 06:01:15 PM UTC 24 | 32075556 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.243640425 | Oct 14 06:14:26 PM UTC 24 | Oct 14 06:14:28 PM UTC 24 | 8872217 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1222194471 | Oct 14 06:14:26 PM UTC 24 | Oct 14 06:14:28 PM UTC 24 | 9593137 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.979002438 | Oct 14 06:14:26 PM UTC 24 | Oct 14 06:14:28 PM UTC 24 | 8504447 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.3452329599 | Oct 14 06:14:28 PM UTC 24 | Oct 14 06:14:29 PM UTC 24 | 9427020 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2068843288 | Oct 14 06:14:28 PM UTC 24 | Oct 14 06:14:29 PM UTC 24 | 9706788 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3908327415 | Oct 14 06:14:28 PM UTC 24 | Oct 14 06:14:29 PM UTC 24 | 9254926 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.2677007335 | Oct 14 06:14:29 PM UTC 24 | Oct 14 06:14:30 PM UTC 24 | 10559592 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.2467030061 | Oct 14 06:14:29 PM UTC 24 | Oct 14 06:14:30 PM UTC 24 | 9661830 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2914486491 | Oct 14 06:14:29 PM UTC 24 | Oct 14 06:14:30 PM UTC 24 | 8908964 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.1152685703 | Oct 14 06:14:29 PM UTC 24 | Oct 14 06:14:30 PM UTC 24 | 10085153 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.2988297251 | Oct 14 06:14:29 PM UTC 24 | Oct 14 06:14:30 PM UTC 24 | 8599950 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2267954931 | Oct 14 06:14:29 PM UTC 24 | Oct 14 06:14:30 PM UTC 24 | 9377870 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3236420668 | Oct 14 06:14:29 PM UTC 24 | Oct 14 06:14:30 PM UTC 24 | 9279271 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2053125612 | Oct 14 06:14:30 PM UTC 24 | Oct 14 06:14:31 PM UTC 24 | 9157239 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.429965726 | Oct 14 06:14:30 PM UTC 24 | Oct 14 06:14:31 PM UTC 24 | 8498797 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3994459283 | Oct 14 06:14:30 PM UTC 24 | Oct 14 06:14:31 PM UTC 24 | 10291495 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1953841320 | Oct 14 06:14:31 PM UTC 24 | Oct 14 06:14:32 PM UTC 24 | 9304688 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2007563562 | Oct 14 06:14:31 PM UTC 24 | Oct 14 06:14:32 PM UTC 24 | 9074024 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.438874951 | Oct 14 06:14:31 PM UTC 24 | Oct 14 06:14:32 PM UTC 24 | 11008616 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.826001620 | Oct 14 06:14:31 PM UTC 24 | Oct 14 06:14:32 PM UTC 24 | 9728405 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.874744383 | Oct 14 06:14:31 PM UTC 24 | Oct 14 06:14:33 PM UTC 24 | 27966558 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3867731686 | Oct 14 06:14:31 PM UTC 24 | Oct 14 06:14:33 PM UTC 24 | 27739364 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1355643152 | Oct 14 06:14:31 PM UTC 24 | Oct 14 06:14:33 PM UTC 24 | 27050259 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2224998962 | Oct 14 06:14:32 PM UTC 24 | Oct 14 06:14:34 PM UTC 24 | 28258883 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.906538932 | Oct 14 06:14:32 PM UTC 24 | Oct 14 06:14:34 PM UTC 24 | 28756058 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1000598084 | Oct 14 06:14:32 PM UTC 24 | Oct 14 06:14:34 PM UTC 24 | 26527436 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3910610715 | Oct 14 06:14:33 PM UTC 24 | Oct 14 06:14:35 PM UTC 24 | 26497453 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.600912614 | Oct 14 06:14:33 PM UTC 24 | Oct 14 06:14:35 PM UTC 24 | 26856792 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4219866077 | Oct 14 06:14:33 PM UTC 24 | Oct 14 06:14:35 PM UTC 24 | 26868633 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2820745661 | Oct 14 06:14:33 PM UTC 24 | Oct 14 06:14:35 PM UTC 24 | 28109984 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3306373133 | Oct 14 06:14:33 PM UTC 24 | Oct 14 06:14:35 PM UTC 24 | 28080539 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3136077988 | Oct 14 06:14:34 PM UTC 24 | Oct 14 06:14:35 PM UTC 24 | 28673190 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3160637291 | Oct 14 06:14:34 PM UTC 24 | Oct 14 06:14:35 PM UTC 24 | 25370051 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1485241555 | Oct 14 06:14:35 PM UTC 24 | Oct 14 06:14:36 PM UTC 24 | 27169118 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.457017257 | Oct 14 06:14:35 PM UTC 24 | Oct 14 06:14:36 PM UTC 24 | 27007985 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.512650353 | Oct 14 06:14:35 PM UTC 24 | Oct 14 06:14:36 PM UTC 24 | 28205210 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.875193872 | Oct 14 06:14:36 PM UTC 24 | Oct 14 06:14:37 PM UTC 24 | 30241880 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.897166666 | Oct 14 06:14:36 PM UTC 24 | Oct 14 06:14:37 PM UTC 24 | 27523064 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3036416367 | Oct 14 06:14:36 PM UTC 24 | Oct 14 06:14:37 PM UTC 24 | 26726648 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.785796880 | Oct 14 06:14:36 PM UTC 24 | Oct 14 06:14:37 PM UTC 24 | 27318865 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.1276866499 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12851862 ps |
| CPU time | 0.41 seconds |
| Started | Oct 14 06:14:22 PM UTC 24 |
| Finished | Oct 14 06:14:23 PM UTC 24 |
| Peak memory | 154496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276866499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.prim_async_alert.1276866499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/1.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.243640425 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8872217 ps |
| CPU time | 0.35 seconds |
| Started | Oct 14 06:14:26 PM UTC 24 |
| Finished | Oct 14 06:14:28 PM UTC 24 |
| Peak memory | 154604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243640425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 0.prim_sync_alert.243640425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/0.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2577109438 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 29152348 ps |
| CPU time | 0.44 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577109438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 6.prim_async_fatal_alert.2577109438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.1832377171 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 31105017 ps |
| CPU time | 0.48 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832377171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 10.prim_async_fatal_alert.1832377171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.3037299040 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28798712 ps |
| CPU time | 0.7 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037299040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 0.prim_async_fatal_alert.3037299040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2224998962 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 28258883 ps |
| CPU time | 0.36 seconds |
| Started | Oct 14 06:14:32 PM UTC 24 |
| Finished | Oct 14 06:14:34 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224998962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2224998962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.294621593 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10540939 ps |
| CPU time | 0.55 seconds |
| Started | Oct 14 06:14:22 PM UTC 24 |
| Finished | Oct 14 06:14:23 PM UTC 24 |
| Peak memory | 152852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294621593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.prim_async_alert.294621593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/0.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.3795747467 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12061534 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:24 PM UTC 24 |
| Finished | Oct 14 06:14:25 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795747467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 10.prim_async_alert.3795747467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/10.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.1862123137 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11410531 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:24 PM UTC 24 |
| Finished | Oct 14 06:14:25 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862123137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 11.prim_async_alert.1862123137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/11.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.2563560451 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10600294 ps |
| CPU time | 0.35 seconds |
| Started | Oct 14 06:14:24 PM UTC 24 |
| Finished | Oct 14 06:14:25 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563560451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 12.prim_async_alert.2563560451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/12.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.1963381199 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12256458 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:24 PM UTC 24 |
| Finished | Oct 14 06:14:25 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963381199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.prim_async_alert.1963381199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/13.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.3213743028 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11830984 ps |
| CPU time | 0.36 seconds |
| Started | Oct 14 06:14:24 PM UTC 24 |
| Finished | Oct 14 06:14:26 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213743028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.prim_async_alert.3213743028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/14.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.809863937 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10835811 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:25 PM UTC 24 |
| Finished | Oct 14 06:14:27 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809863937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 15.prim_async_alert.809863937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/15.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.1407681640 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10794981 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:26 PM UTC 24 |
| Finished | Oct 14 06:14:28 PM UTC 24 |
| Peak memory | 154732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407681640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 16.prim_async_alert.1407681640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/16.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3920823739 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10469695 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:26 PM UTC 24 |
| Finished | Oct 14 06:14:28 PM UTC 24 |
| Peak memory | 154752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920823739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.prim_async_alert.3920823739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/17.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/18.prim_async_alert.2972370706 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12327552 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:26 PM UTC 24 |
| Finished | Oct 14 06:14:28 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972370706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.prim_async_alert.2972370706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/18.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.133348450 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11302213 ps |
| CPU time | 0.35 seconds |
| Started | Oct 14 06:14:26 PM UTC 24 |
| Finished | Oct 14 06:14:28 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133348450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 19.prim_async_alert.133348450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/19.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.498094783 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12796974 ps |
| CPU time | 0.41 seconds |
| Started | Oct 14 06:14:22 PM UTC 24 |
| Finished | Oct 14 06:14:23 PM UTC 24 |
| Peak memory | 153208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498094783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.prim_async_alert.498094783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/2.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.2182898042 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10723682 ps |
| CPU time | 0.38 seconds |
| Started | Oct 14 06:14:22 PM UTC 24 |
| Finished | Oct 14 06:14:23 PM UTC 24 |
| Peak memory | 153816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182898042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 3.prim_async_alert.2182898042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/3.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.704651722 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11425741 ps |
| CPU time | 0.41 seconds |
| Started | Oct 14 06:14:22 PM UTC 24 |
| Finished | Oct 14 06:14:23 PM UTC 24 |
| Peak memory | 153672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704651722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 4.prim_async_alert.704651722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/4.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.3249747904 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11109294 ps |
| CPU time | 0.38 seconds |
| Started | Oct 14 06:14:22 PM UTC 24 |
| Finished | Oct 14 06:14:23 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249747904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 5.prim_async_alert.3249747904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/5.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.1326191390 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11119957 ps |
| CPU time | 0.36 seconds |
| Started | Oct 14 06:14:22 PM UTC 24 |
| Finished | Oct 14 06:14:23 PM UTC 24 |
| Peak memory | 154536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326191390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.prim_async_alert.1326191390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/6.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.587797642 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11440455 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:23 PM UTC 24 |
| Finished | Oct 14 06:14:24 PM UTC 24 |
| Peak memory | 155156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587797642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 7.prim_async_alert.587797642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/7.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.4051081661 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12645741 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:24 PM UTC 24 |
| Finished | Oct 14 06:14:25 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051081661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.prim_async_alert.4051081661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/8.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.1602179081 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11131178 ps |
| CPU time | 0.36 seconds |
| Started | Oct 14 06:14:24 PM UTC 24 |
| Finished | Oct 14 06:14:25 PM UTC 24 |
| Peak memory | 155152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602179081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 9.prim_async_alert.1602179081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/9.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.318775398 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 31029745 ps |
| CPU time | 0.58 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 154964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318775398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 1.prim_async_fatal_alert.318775398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.2510647101 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 31952071 ps |
| CPU time | 0.51 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510647101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 11.prim_async_fatal_alert.2510647101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.300617249 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 29005915 ps |
| CPU time | 0.47 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300617249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 12.prim_async_fatal_alert.300617249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.3708416718 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29463356 ps |
| CPU time | 0.54 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708416718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 13.prim_async_fatal_alert.3708416718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.1500529407 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30336330 ps |
| CPU time | 0.41 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500529407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 14.prim_async_fatal_alert.1500529407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.871926508 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30326153 ps |
| CPU time | 0.45 seconds |
| Started | Oct 14 06:01:02 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871926508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 15.prim_async_fatal_alert.871926508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.4181875073 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 31366514 ps |
| CPU time | 0.45 seconds |
| Started | Oct 14 06:01:02 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181875073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 16.prim_async_fatal_alert.4181875073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.247872726 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 31174945 ps |
| CPU time | 0.41 seconds |
| Started | Oct 14 06:01:02 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247872726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 17.prim_async_fatal_alert.247872726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.2097361957 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 29132124 ps |
| CPU time | 0.44 seconds |
| Started | Oct 14 06:01:02 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097361957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 18.prim_async_fatal_alert.2097361957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.2315999294 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 32075556 ps |
| CPU time | 0.44 seconds |
| Started | Oct 14 06:01:13 PM UTC 24 |
| Finished | Oct 14 06:01:15 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315999294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 19.prim_async_fatal_alert.2315999294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.2045141848 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 30890778 ps |
| CPU time | 0.53 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045141848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 2.prim_async_fatal_alert.2045141848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.214779283 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 28854936 ps |
| CPU time | 0.58 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214779283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 3.prim_async_fatal_alert.214779283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.2336953508 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 29047239 ps |
| CPU time | 0.56 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336953508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 4.prim_async_fatal_alert.2336953508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.1522378883 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29067069 ps |
| CPU time | 0.47 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522378883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 5.prim_async_fatal_alert.1522378883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.1640559877 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 30431870 ps |
| CPU time | 0.56 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640559877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 7.prim_async_fatal_alert.1640559877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.953911772 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 31873614 ps |
| CPU time | 0.52 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953911772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_ log /dev/null -cm_name 8.prim_async_fatal_alert.953911772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.1721991793 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 30901080 ps |
| CPU time | 0.56 seconds |
| Started | Oct 14 06:01:01 PM UTC 24 |
| Finished | Oct 14 06:01:03 PM UTC 24 |
| Peak memory | 155012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721991793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm _log /dev/null -cm_name 9.prim_async_fatal_alert.1721991793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1222194471 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9593137 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:26 PM UTC 24 |
| Finished | Oct 14 06:14:28 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222194471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 1.prim_sync_alert.1222194471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/1.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.2988297251 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8599950 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:29 PM UTC 24 |
| Finished | Oct 14 06:14:30 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988297251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 10.prim_sync_alert.2988297251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/10.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.2267954931 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9377870 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:29 PM UTC 24 |
| Finished | Oct 14 06:14:30 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267954931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 11.prim_sync_alert.2267954931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/11.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3236420668 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9279271 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:29 PM UTC 24 |
| Finished | Oct 14 06:14:30 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236420668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 12.prim_sync_alert.3236420668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/12.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.429965726 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8498797 ps |
| CPU time | 0.35 seconds |
| Started | Oct 14 06:14:30 PM UTC 24 |
| Finished | Oct 14 06:14:31 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429965726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 13.prim_sync_alert.429965726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/13.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2053125612 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9157239 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:30 PM UTC 24 |
| Finished | Oct 14 06:14:31 PM UTC 24 |
| Peak memory | 154536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053125612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 14.prim_sync_alert.2053125612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/14.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.3994459283 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 10291495 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:30 PM UTC 24 |
| Finished | Oct 14 06:14:31 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994459283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 15.prim_sync_alert.3994459283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/15.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.438874951 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 11008616 ps |
| CPU time | 0.37 seconds |
| Started | Oct 14 06:14:31 PM UTC 24 |
| Finished | Oct 14 06:14:32 PM UTC 24 |
| Peak memory | 154444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438874951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 16.prim_sync_alert.438874951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/16.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.1953841320 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 9304688 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:31 PM UTC 24 |
| Finished | Oct 14 06:14:32 PM UTC 24 |
| Peak memory | 154384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953841320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 17.prim_sync_alert.1953841320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/17.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2007563562 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 9074024 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:31 PM UTC 24 |
| Finished | Oct 14 06:14:32 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007563562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 18.prim_sync_alert.2007563562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/18.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.826001620 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9728405 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:31 PM UTC 24 |
| Finished | Oct 14 06:14:32 PM UTC 24 |
| Peak memory | 154544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826001620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 19.prim_sync_alert.826001620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/19.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.979002438 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8504447 ps |
| CPU time | 0.32 seconds |
| Started | Oct 14 06:14:26 PM UTC 24 |
| Finished | Oct 14 06:14:28 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979002438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_lo g /dev/null -cm_name 2.prim_sync_alert.979002438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/2.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.2068843288 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9706788 ps |
| CPU time | 0.37 seconds |
| Started | Oct 14 06:14:28 PM UTC 24 |
| Finished | Oct 14 06:14:29 PM UTC 24 |
| Peak memory | 154056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068843288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 3.prim_sync_alert.2068843288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/3.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.3452329599 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9427020 ps |
| CPU time | 0.35 seconds |
| Started | Oct 14 06:14:28 PM UTC 24 |
| Finished | Oct 14 06:14:29 PM UTC 24 |
| Peak memory | 154188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452329599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 4.prim_sync_alert.3452329599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/4.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.3908327415 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9254926 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:28 PM UTC 24 |
| Finished | Oct 14 06:14:29 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908327415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 5.prim_sync_alert.3908327415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/5.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.1152685703 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10085153 ps |
| CPU time | 0.37 seconds |
| Started | Oct 14 06:14:29 PM UTC 24 |
| Finished | Oct 14 06:14:30 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152685703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 6.prim_sync_alert.1152685703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/6.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.2467030061 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9661830 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:29 PM UTC 24 |
| Finished | Oct 14 06:14:30 PM UTC 24 |
| Peak memory | 154480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467030061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 7.prim_sync_alert.2467030061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/7.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2914486491 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8908964 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:29 PM UTC 24 |
| Finished | Oct 14 06:14:30 PM UTC 24 |
| Peak memory | 154468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914486491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 8.prim_sync_alert.2914486491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/8.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.2677007335 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10559592 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:29 PM UTC 24 |
| Finished | Oct 14 06:14:30 PM UTC 24 |
| Peak memory | 154540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677007335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_l og /dev/null -cm_name 9.prim_sync_alert.2677007335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/9.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.874744383 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 27966558 ps |
| CPU time | 0.35 seconds |
| Started | Oct 14 06:14:31 PM UTC 24 |
| Finished | Oct 14 06:14:33 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874744383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.874744383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3867731686 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 27739364 ps |
| CPU time | 0.35 seconds |
| Started | Oct 14 06:14:31 PM UTC 24 |
| Finished | Oct 14 06:14:33 PM UTC 24 |
| Peak memory | 154240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867731686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3867731686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3306373133 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28080539 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:33 PM UTC 24 |
| Finished | Oct 14 06:14:35 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306373133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3306373133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3136077988 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 28673190 ps |
| CPU time | 0.36 seconds |
| Started | Oct 14 06:14:34 PM UTC 24 |
| Finished | Oct 14 06:14:35 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136077988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3136077988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3160637291 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 25370051 ps |
| CPU time | 0.37 seconds |
| Started | Oct 14 06:14:34 PM UTC 24 |
| Finished | Oct 14 06:14:35 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160637291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3160637291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1485241555 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27169118 ps |
| CPU time | 0.36 seconds |
| Started | Oct 14 06:14:35 PM UTC 24 |
| Finished | Oct 14 06:14:36 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485241555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1485241555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.457017257 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 27007985 ps |
| CPU time | 0.35 seconds |
| Started | Oct 14 06:14:35 PM UTC 24 |
| Finished | Oct 14 06:14:36 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457017257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.457017257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.512650353 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 28205210 ps |
| CPU time | 0.36 seconds |
| Started | Oct 14 06:14:35 PM UTC 24 |
| Finished | Oct 14 06:14:36 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512650353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.512650353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.897166666 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27523064 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:36 PM UTC 24 |
| Finished | Oct 14 06:14:37 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897166666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.897166666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3036416367 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26726648 ps |
| CPU time | 0.39 seconds |
| Started | Oct 14 06:14:36 PM UTC 24 |
| Finished | Oct 14 06:14:37 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036416367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3036416367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.875193872 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 30241880 ps |
| CPU time | 0.37 seconds |
| Started | Oct 14 06:14:36 PM UTC 24 |
| Finished | Oct 14 06:14:37 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875193872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.875193872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.785796880 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 27318865 ps |
| CPU time | 0.37 seconds |
| Started | Oct 14 06:14:36 PM UTC 24 |
| Finished | Oct 14 06:14:37 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785796880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.785796880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1355643152 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27050259 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:31 PM UTC 24 |
| Finished | Oct 14 06:14:33 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355643152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1355643152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1000598084 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26527436 ps |
| CPU time | 0.35 seconds |
| Started | Oct 14 06:14:32 PM UTC 24 |
| Finished | Oct 14 06:14:34 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000598084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1000598084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.906538932 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 28756058 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:32 PM UTC 24 |
| Finished | Oct 14 06:14:34 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906538932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.906538932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3910610715 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26497453 ps |
| CPU time | 0.36 seconds |
| Started | Oct 14 06:14:33 PM UTC 24 |
| Finished | Oct 14 06:14:35 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910610715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3910610715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.600912614 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26856792 ps |
| CPU time | 0.34 seconds |
| Started | Oct 14 06:14:33 PM UTC 24 |
| Finished | Oct 14 06:14:35 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600912614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_aler t.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.600912614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2820745661 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28109984 ps |
| CPU time | 0.33 seconds |
| Started | Oct 14 06:14:33 PM UTC 24 |
| Finished | Oct 14 06:14:35 PM UTC 24 |
| Peak memory | 154180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820745661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2820745661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.4219866077 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26868633 ps |
| CPU time | 0.36 seconds |
| Started | Oct 14 06:14:33 PM UTC 24 |
| Finished | Oct 14 06:14:35 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219866077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/coverage/sync_fatal_ale rt.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.4219866077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |