| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.60 | 100.00 | 100.00 | 100.00 | 85.71 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.88 | 88.88 | 100.00 | 100.00 | 93.75 | 93.75 | 100.00 | 100.00 | 78.57 | 78.57 | 95.83 | 95.83 | 65.12 | 65.12 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.285544787 |
| 91.41 | 2.53 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 82.14 | 3.57 | 95.83 | 0.00 | 76.74 | 11.63 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1172602059 |
| 92.96 | 1.55 | 100.00 | 0.00 | 93.75 | 0.00 | 100.00 | 0.00 | 82.14 | 0.00 | 95.83 | 0.00 | 86.05 | 9.30 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.849011954 |
| 93.90 | 0.94 | 100.00 | 0.00 | 95.83 | 2.08 | 100.00 | 0.00 | 85.71 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1188046870 |
| 94.25 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.3562874895 |
| 94.60 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.2465042220 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3251325556 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.2299892180 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.3024217634 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3755898979 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.3453023383 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2699091974 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.1836701371 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.2109271312 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3318763572 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.3396023815 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.614082745 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.154191613 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.660530486 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.1885045173 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1453082405 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2575679800 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3295273872 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3234316706 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.995722420 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.4005775338 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.2152011025 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.811102023 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.1137573326 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.4278834817 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1898360567 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.4223902337 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.809409799 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.4246985308 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1652550298 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3035061345 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.894287260 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2167463994 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3841399907 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.4243249276 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.3004351583 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.2552676829 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.2128165916 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.115703629 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3722912898 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.227102213 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2860275207 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.1503358610 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.166416548 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3201316588 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2934710161 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.2038449360 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2851388987 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.741443889 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.777784882 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.772549417 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.409119887 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.291915573 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2383743525 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1509890829 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.71298950 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.120672174 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.957910660 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.370309685 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.49389294 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1210686005 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1032297940 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.895867095 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.958827485 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1180392026 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1062721093 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2616526098 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.796507734 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3380314183 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1007949618 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2178928773 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3377139994 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.686916592 |
| /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2557346184 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.2299892180 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:16 AM UTC 25 | 11140395 ps | ||
| T2 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.285544787 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:16 AM UTC 25 | 12867274 ps | ||
| T3 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.154191613 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:16 AM UTC 25 | 11451851 ps | ||
| T8 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1453082405 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:16 AM UTC 25 | 11483889 ps | ||
| T12 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.1885045173 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:17 AM UTC 25 | 10356285 ps | ||
| T9 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.614082745 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:17 AM UTC 25 | 11292897 ps | ||
| T6 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.3562874895 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:17 AM UTC 25 | 11471990 ps | ||
| T13 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3251325556 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:17 AM UTC 25 | 11468514 ps | ||
| T16 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.660530486 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:17 AM UTC 25 | 10461605 ps | ||
| T14 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2575679800 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:17 AM UTC 25 | 11771951 ps | ||
| T15 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.3024217634 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:17 AM UTC 25 | 11567590 ps | ||
| T17 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3295273872 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:17 AM UTC 25 | 11111970 ps | ||
| T47 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3755898979 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:17 AM UTC 25 | 11627404 ps | ||
| T7 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.3453023383 | Feb 08 05:39:14 AM UTC 25 | Feb 08 05:39:17 AM UTC 25 | 11210687 ps | ||
| T18 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.2109271312 | Feb 08 05:39:20 AM UTC 25 | Feb 08 05:39:22 AM UTC 25 | 10985643 ps | ||
| T48 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.1836701371 | Feb 08 05:39:20 AM UTC 25 | Feb 08 05:39:23 AM UTC 25 | 10578073 ps | ||
| T19 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2699091974 | Feb 08 05:39:20 AM UTC 25 | Feb 08 05:39:23 AM UTC 25 | 11247754 ps | ||
| T49 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3318763572 | Feb 08 05:39:20 AM UTC 25 | Feb 08 05:39:23 AM UTC 25 | 11180522 ps | ||
| T50 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.3396023815 | Feb 08 05:39:21 AM UTC 25 | Feb 08 05:39:24 AM UTC 25 | 10878637 ps | ||
| T11 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.849011954 | Feb 08 07:33:28 AM UTC 25 | Feb 08 07:33:29 AM UTC 25 | 28302295 ps | ||
| T4 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.2465042220 | Feb 08 07:33:28 AM UTC 25 | Feb 08 07:33:29 AM UTC 25 | 31808891 ps | ||
| T39 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.894287260 | Feb 08 07:33:28 AM UTC 25 | Feb 08 07:33:29 AM UTC 25 | 28100446 ps | ||
| T40 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3234316706 | Feb 08 07:33:28 AM UTC 25 | Feb 08 07:33:29 AM UTC 25 | 30152651 ps | ||
| T41 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1652550298 | Feb 08 07:33:28 AM UTC 25 | Feb 08 07:33:29 AM UTC 25 | 30159071 ps | ||
| T42 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3035061345 | Feb 08 07:33:28 AM UTC 25 | Feb 08 07:33:29 AM UTC 25 | 31003301 ps | ||
| T43 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.4243249276 | Feb 08 07:33:30 AM UTC 25 | Feb 08 07:33:32 AM UTC 25 | 28025865 ps | ||
| T44 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2167463994 | Feb 08 07:33:30 AM UTC 25 | Feb 08 07:33:32 AM UTC 25 | 30722173 ps | ||
| T45 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3841399907 | Feb 08 07:33:30 AM UTC 25 | Feb 08 07:33:32 AM UTC 25 | 30711773 ps | ||
| T46 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.995722420 | Feb 08 07:33:31 AM UTC 25 | Feb 08 07:33:32 AM UTC 25 | 29570601 ps | ||
| T51 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.3004351583 | Feb 08 07:33:31 AM UTC 25 | Feb 08 07:33:32 AM UTC 25 | 30765505 ps | ||
| T52 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.4005775338 | Feb 08 07:33:31 AM UTC 25 | Feb 08 07:33:32 AM UTC 25 | 31560505 ps | ||
| T53 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.811102023 | Feb 08 07:33:33 AM UTC 25 | Feb 08 07:33:34 AM UTC 25 | 30308577 ps | ||
| T54 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.2152011025 | Feb 08 07:33:33 AM UTC 25 | Feb 08 07:33:34 AM UTC 25 | 29911957 ps | ||
| T55 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.1137573326 | Feb 08 07:33:34 AM UTC 25 | Feb 08 07:33:35 AM UTC 25 | 29686289 ps | ||
| T56 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.4223902337 | Feb 08 07:33:34 AM UTC 25 | Feb 08 07:33:36 AM UTC 25 | 31394743 ps | ||
| T57 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.4278834817 | Feb 08 07:33:34 AM UTC 25 | Feb 08 07:33:36 AM UTC 25 | 32125736 ps | ||
| T58 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.4246985308 | Feb 08 07:33:34 AM UTC 25 | Feb 08 07:33:36 AM UTC 25 | 30430609 ps | ||
| T5 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.809409799 | Feb 08 07:33:34 AM UTC 25 | Feb 08 07:33:36 AM UTC 25 | 30836700 ps | ||
| T59 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1898360567 | Feb 08 07:33:34 AM UTC 25 | Feb 08 07:33:36 AM UTC 25 | 29987848 ps | ||
| T29 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.2552676829 | Feb 08 07:33:34 AM UTC 25 | Feb 08 07:33:36 AM UTC 25 | 8662636 ps | ||
| T30 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2851388987 | Feb 08 07:33:34 AM UTC 25 | Feb 08 07:33:36 AM UTC 25 | 8450601 ps | ||
| T31 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1172602059 | Feb 08 07:33:34 AM UTC 25 | Feb 08 07:33:36 AM UTC 25 | 8540849 ps | ||
| T20 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.772549417 | Feb 08 07:33:35 AM UTC 25 | Feb 08 07:33:37 AM UTC 25 | 10166628 ps | ||
| T32 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.777784882 | Feb 08 07:33:35 AM UTC 25 | Feb 08 07:33:37 AM UTC 25 | 9038210 ps | ||
| T33 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.741443889 | Feb 08 07:33:35 AM UTC 25 | Feb 08 07:33:37 AM UTC 25 | 8533220 ps | ||
| T34 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2383743525 | Feb 08 07:33:35 AM UTC 25 | Feb 08 07:33:37 AM UTC 25 | 9536569 ps | ||
| T21 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.291915573 | Feb 08 07:33:35 AM UTC 25 | Feb 08 07:33:37 AM UTC 25 | 9587561 ps | ||
| T35 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1509890829 | Feb 08 07:33:35 AM UTC 25 | Feb 08 07:33:37 AM UTC 25 | 9330723 ps | ||
| T22 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.409119887 | Feb 08 07:33:35 AM UTC 25 | Feb 08 07:33:37 AM UTC 25 | 10737906 ps | ||
| T23 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.227102213 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:38 AM UTC 25 | 9366906 ps | ||
| T60 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.115703629 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:38 AM UTC 25 | 9067636 ps | ||
| T36 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3722912898 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:38 AM UTC 25 | 9646921 ps | ||
| T24 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2934710161 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:38 AM UTC 25 | 9459096 ps | ||
| T25 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2860275207 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:38 AM UTC 25 | 9570927 ps | ||
| T61 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.2128165916 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:38 AM UTC 25 | 9177008 ps | ||
| T37 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.166416548 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:39 AM UTC 25 | 9263368 ps | ||
| T38 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.1503358610 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:39 AM UTC 25 | 10039462 ps | ||
| T62 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3201316588 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:39 AM UTC 25 | 10170651 ps | ||
| T26 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.2038449360 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:39 AM UTC 25 | 9139430 ps | ||
| T63 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.796507734 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:39 AM UTC 25 | 29841035 ps | ||
| T27 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.120672174 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:39 AM UTC 25 | 27535799 ps | ||
| T28 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.71298950 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:39 AM UTC 25 | 26507335 ps | ||
| T64 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3380314183 | Feb 08 07:33:36 AM UTC 25 | Feb 08 07:33:39 AM UTC 25 | 29416460 ps | ||
| T65 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.957910660 | Feb 08 07:33:38 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 29015104 ps | ||
| T66 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2178928773 | Feb 08 07:33:37 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 26671785 ps | ||
| T67 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.49389294 | Feb 08 07:33:38 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 27267672 ps | ||
| T68 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1007949618 | Feb 08 07:33:37 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 28030299 ps | ||
| T69 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1210686005 | Feb 08 07:33:38 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 27850066 ps | ||
| T70 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.686916592 | Feb 08 07:33:38 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 26611365 ps | ||
| T10 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1188046870 | Feb 08 07:33:38 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 27809433 ps | ||
| T71 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.895867095 | Feb 08 07:33:38 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 27679953 ps | ||
| T72 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3377139994 | Feb 08 07:33:37 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 28006641 ps | ||
| T73 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.370309685 | Feb 08 07:33:38 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 27726478 ps | ||
| T74 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2557346184 | Feb 08 07:33:38 AM UTC 25 | Feb 08 07:33:40 AM UTC 25 | 28235395 ps | ||
| T75 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1032297940 | Feb 08 07:33:38 AM UTC 25 | Feb 08 07:33:41 AM UTC 25 | 27331795 ps | ||
| T76 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1180392026 | Feb 08 07:33:39 AM UTC 25 | Feb 08 07:33:41 AM UTC 25 | 28917584 ps | ||
| T77 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.958827485 | Feb 08 07:33:39 AM UTC 25 | Feb 08 07:33:41 AM UTC 25 | 23968858 ps | ||
| T78 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1062721093 | Feb 08 07:33:39 AM UTC 25 | Feb 08 07:33:41 AM UTC 25 | 27849197 ps | ||
| T79 | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2616526098 | Feb 08 07:33:39 AM UTC 25 | Feb 08 07:33:41 AM UTC 25 | 27146571 ps |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/3.prim_async_alert.285544787 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12867274 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:16 AM UTC 25 |
| Peak memory | 155152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285544787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_ async_alert.285544787 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/3.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/1.prim_sync_alert.1172602059 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8540849 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 07:33:34 AM UTC 25 |
| Finished | Feb 08 07:33:36 AM UTC 25 |
| Peak memory | 154536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172602059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1172602059 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/1.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/2.prim_async_fatal_alert.849011954 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 28302295 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 07:33:28 AM UTC 25 |
| Finished | Feb 08 07:33:29 AM UTC 25 |
| Peak memory | 155952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849011954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.849011954 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1188046870 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 27809433 ps |
| CPU time | 0.38 seconds |
| Started | Feb 08 07:33:38 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188046870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 8.prim_sync_fatal_alert.1188046870 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/10.prim_async_alert.3562874895 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11471990 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:17 AM UTC 25 |
| Peak memory | 155148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562874895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pri m_async_alert.3562874895 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/10.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/0.prim_async_fatal_alert.2465042220 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 31808891 ps |
| CPU time | 0.53 seconds |
| Started | Feb 08 07:33:28 AM UTC 25 |
| Finished | Feb 08 07:33:29 AM UTC 25 |
| Peak memory | 152932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465042220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 0.prim_async_fatal_alert.2465042220 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/0.prim_async_alert.3251325556 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11468514 ps |
| CPU time | 0.49 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:17 AM UTC 25 |
| Peak memory | 155152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251325556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim _async_alert.3251325556 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/0.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/1.prim_async_alert.2299892180 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11140395 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:16 AM UTC 25 |
| Peak memory | 155216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299892180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim _async_alert.2299892180 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/1.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/11.prim_async_alert.3024217634 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11567590 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:17 AM UTC 25 |
| Peak memory | 155148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024217634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pri m_async_alert.3024217634 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/11.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/12.prim_async_alert.3755898979 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11627404 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:17 AM UTC 25 |
| Peak memory | 155148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755898979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pri m_async_alert.3755898979 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/12.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/13.prim_async_alert.3453023383 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11210687 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:17 AM UTC 25 |
| Peak memory | 155148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453023383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pri m_async_alert.3453023383 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/13.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/14.prim_async_alert.2699091974 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11247754 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 05:39:20 AM UTC 25 |
| Finished | Feb 08 05:39:23 AM UTC 25 |
| Peak memory | 155148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699091974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pri m_async_alert.2699091974 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/14.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/15.prim_async_alert.1836701371 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10578073 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 05:39:20 AM UTC 25 |
| Finished | Feb 08 05:39:23 AM UTC 25 |
| Peak memory | 155148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836701371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pri m_async_alert.1836701371 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/15.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/16.prim_async_alert.2109271312 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10985643 ps |
| CPU time | 0.35 seconds |
| Started | Feb 08 05:39:20 AM UTC 25 |
| Finished | Feb 08 05:39:22 AM UTC 25 |
| Peak memory | 155148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109271312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pri m_async_alert.2109271312 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/16.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/17.prim_async_alert.3318763572 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11180522 ps |
| CPU time | 0.32 seconds |
| Started | Feb 08 05:39:20 AM UTC 25 |
| Finished | Feb 08 05:39:23 AM UTC 25 |
| Peak memory | 155148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318763572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pri m_async_alert.3318763572 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/17.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/19.prim_async_alert.3396023815 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10878637 ps |
| CPU time | 0.41 seconds |
| Started | Feb 08 05:39:21 AM UTC 25 |
| Finished | Feb 08 05:39:24 AM UTC 25 |
| Peak memory | 155148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396023815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pri m_async_alert.3396023815 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/19.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/2.prim_async_alert.614082745 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11292897 ps |
| CPU time | 0.41 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:17 AM UTC 25 |
| Peak memory | 155152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614082745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_ async_alert.614082745 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/2.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/4.prim_async_alert.154191613 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11451851 ps |
| CPU time | 0.38 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:16 AM UTC 25 |
| Peak memory | 155152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154191613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_ async_alert.154191613 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/4.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/5.prim_async_alert.660530486 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10461605 ps |
| CPU time | 0.4 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:17 AM UTC 25 |
| Peak memory | 155152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660530486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_ async_alert.660530486 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/5.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/6.prim_async_alert.1885045173 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10356285 ps |
| CPU time | 0.39 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:17 AM UTC 25 |
| Peak memory | 155152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885045173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim _async_alert.1885045173 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/6.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/7.prim_async_alert.1453082405 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11483889 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:16 AM UTC 25 |
| Peak memory | 155152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453082405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim _async_alert.1453082405 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/7.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/8.prim_async_alert.2575679800 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11771951 ps |
| CPU time | 0.4 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:17 AM UTC 25 |
| Peak memory | 155152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575679800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim _async_alert.2575679800 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/8.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default/9.prim_async_alert.3295273872 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11111970 ps |
| CPU time | 0.43 seconds |
| Started | Feb 08 05:39:14 AM UTC 25 |
| Finished | Feb 08 05:39:17 AM UTC 25 |
| Peak memory | 155152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295273872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim _async_alert.3295273872 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/9.prim_async_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/1.prim_async_fatal_alert.3234316706 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 30152651 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 07:33:28 AM UTC 25 |
| Finished | Feb 08 07:33:29 AM UTC 25 |
| Peak memory | 153444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234316706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 1.prim_async_fatal_alert.3234316706 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/10.prim_async_fatal_alert.995722420 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29570601 ps |
| CPU time | 0.35 seconds |
| Started | Feb 08 07:33:31 AM UTC 25 |
| Finished | Feb 08 07:33:32 AM UTC 25 |
| Peak memory | 155016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995722420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.995722420 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/10.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/11.prim_async_fatal_alert.4005775338 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 31560505 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 07:33:31 AM UTC 25 |
| Finished | Feb 08 07:33:32 AM UTC 25 |
| Peak memory | 155012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005775338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 11.prim_async_fatal_alert.4005775338 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/11.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/12.prim_async_fatal_alert.2152011025 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 29911957 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 07:33:33 AM UTC 25 |
| Finished | Feb 08 07:33:34 AM UTC 25 |
| Peak memory | 155012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152011025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 12.prim_async_fatal_alert.2152011025 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/12.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/13.prim_async_fatal_alert.811102023 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 30308577 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 07:33:33 AM UTC 25 |
| Finished | Feb 08 07:33:34 AM UTC 25 |
| Peak memory | 155016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811102023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.811102023 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/14.prim_async_fatal_alert.1137573326 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29686289 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:34 AM UTC 25 |
| Finished | Feb 08 07:33:35 AM UTC 25 |
| Peak memory | 155012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137573326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 14.prim_async_fatal_alert.1137573326 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/14.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/15.prim_async_fatal_alert.4278834817 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 32125736 ps |
| CPU time | 0.35 seconds |
| Started | Feb 08 07:33:34 AM UTC 25 |
| Finished | Feb 08 07:33:36 AM UTC 25 |
| Peak memory | 155012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278834817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 15.prim_async_fatal_alert.4278834817 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/15.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/16.prim_async_fatal_alert.1898360567 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 29987848 ps |
| CPU time | 0.42 seconds |
| Started | Feb 08 07:33:34 AM UTC 25 |
| Finished | Feb 08 07:33:36 AM UTC 25 |
| Peak memory | 155008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898360567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 16.prim_async_fatal_alert.1898360567 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/16.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/17.prim_async_fatal_alert.4223902337 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 31394743 ps |
| CPU time | 0.35 seconds |
| Started | Feb 08 07:33:34 AM UTC 25 |
| Finished | Feb 08 07:33:36 AM UTC 25 |
| Peak memory | 155012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223902337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 17.prim_async_fatal_alert.4223902337 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/17.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/18.prim_async_fatal_alert.809409799 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30836700 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 07:33:34 AM UTC 25 |
| Finished | Feb 08 07:33:36 AM UTC 25 |
| Peak memory | 155016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809409799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.809409799 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/18.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/19.prim_async_fatal_alert.4246985308 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 30430609 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:34 AM UTC 25 |
| Finished | Feb 08 07:33:36 AM UTC 25 |
| Peak memory | 155012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246985308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 19.prim_async_fatal_alert.4246985308 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/19.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/3.prim_async_fatal_alert.1652550298 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30159071 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 07:33:28 AM UTC 25 |
| Finished | Feb 08 07:33:29 AM UTC 25 |
| Peak memory | 153048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652550298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 3.prim_async_fatal_alert.1652550298 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/4.prim_async_fatal_alert.3035061345 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 31003301 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 07:33:28 AM UTC 25 |
| Finished | Feb 08 07:33:29 AM UTC 25 |
| Peak memory | 152560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035061345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 4.prim_async_fatal_alert.3035061345 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/5.prim_async_fatal_alert.894287260 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 28100446 ps |
| CPU time | 0.4 seconds |
| Started | Feb 08 07:33:28 AM UTC 25 |
| Finished | Feb 08 07:33:29 AM UTC 25 |
| Peak memory | 155000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894287260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.894287260 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/6.prim_async_fatal_alert.2167463994 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30722173 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:30 AM UTC 25 |
| Finished | Feb 08 07:33:32 AM UTC 25 |
| Peak memory | 155000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167463994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 6.prim_async_fatal_alert.2167463994 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/7.prim_async_fatal_alert.3841399907 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30711773 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:30 AM UTC 25 |
| Finished | Feb 08 07:33:32 AM UTC 25 |
| Peak memory | 155008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841399907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 7.prim_async_fatal_alert.3841399907 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/8.prim_async_fatal_alert.4243249276 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 28025865 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:30 AM UTC 25 |
| Finished | Feb 08 07:33:32 AM UTC 25 |
| Peak memory | 155008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243249276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 8.prim_async_fatal_alert.4243249276 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert/9.prim_async_fatal_alert.3004351583 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30765505 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 07:33:31 AM UTC 25 |
| Finished | Feb 08 07:33:32 AM UTC 25 |
| Peak memory | 155012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004351583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_nam e 9.prim_async_fatal_alert.3004351583 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/0.prim_sync_alert.2552676829 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8662636 ps |
| CPU time | 0.32 seconds |
| Started | Feb 08 07:33:34 AM UTC 25 |
| Finished | Feb 08 07:33:36 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552676829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2552676829 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/0.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/10.prim_sync_alert.2128165916 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9177008 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:38 AM UTC 25 |
| Peak memory | 154540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128165916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2128165916 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/10.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/11.prim_sync_alert.115703629 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 9067636 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:38 AM UTC 25 |
| Peak memory | 153212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115703629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1 1.prim_sync_alert.115703629 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/11.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/12.prim_sync_alert.3722912898 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9646921 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:38 AM UTC 25 |
| Peak memory | 153108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722912898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3722912898 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/12.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/13.prim_sync_alert.227102213 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9366906 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:38 AM UTC 25 |
| Peak memory | 154532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227102213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1 3.prim_sync_alert.227102213 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/13.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/14.prim_sync_alert.2860275207 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9570927 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:38 AM UTC 25 |
| Peak memory | 154536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860275207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2860275207 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/14.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/15.prim_sync_alert.1503358610 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10039462 ps |
| CPU time | 0.4 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:39 AM UTC 25 |
| Peak memory | 154540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503358610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1503358610 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/15.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/16.prim_sync_alert.166416548 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9263368 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:39 AM UTC 25 |
| Peak memory | 154532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166416548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1 6.prim_sync_alert.166416548 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/16.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/17.prim_sync_alert.3201316588 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 10170651 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:39 AM UTC 25 |
| Peak memory | 154540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201316588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3201316588 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/17.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/18.prim_sync_alert.2934710161 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9459096 ps |
| CPU time | 0.32 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:38 AM UTC 25 |
| Peak memory | 154540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934710161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2934710161 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/18.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/19.prim_sync_alert.2038449360 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9139430 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:39 AM UTC 25 |
| Peak memory | 154540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038449360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2038449360 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/19.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/2.prim_sync_alert.2851388987 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8450601 ps |
| CPU time | 0.35 seconds |
| Started | Feb 08 07:33:34 AM UTC 25 |
| Finished | Feb 08 07:33:36 AM UTC 25 |
| Peak memory | 154536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851388987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2851388987 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/2.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/3.prim_sync_alert.741443889 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8533220 ps |
| CPU time | 0.39 seconds |
| Started | Feb 08 07:33:35 AM UTC 25 |
| Finished | Feb 08 07:33:37 AM UTC 25 |
| Peak memory | 154536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741443889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3 .prim_sync_alert.741443889 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/3.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/4.prim_sync_alert.777784882 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9038210 ps |
| CPU time | 0.38 seconds |
| Started | Feb 08 07:33:35 AM UTC 25 |
| Finished | Feb 08 07:33:37 AM UTC 25 |
| Peak memory | 154536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777784882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4 .prim_sync_alert.777784882 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/4.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/5.prim_sync_alert.772549417 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10166628 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:35 AM UTC 25 |
| Finished | Feb 08 07:33:37 AM UTC 25 |
| Peak memory | 154536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772549417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5 .prim_sync_alert.772549417 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/5.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/6.prim_sync_alert.409119887 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10737906 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 07:33:35 AM UTC 25 |
| Finished | Feb 08 07:33:37 AM UTC 25 |
| Peak memory | 154536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409119887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6 .prim_sync_alert.409119887 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/6.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/7.prim_sync_alert.291915573 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9587561 ps |
| CPU time | 0.35 seconds |
| Started | Feb 08 07:33:35 AM UTC 25 |
| Finished | Feb 08 07:33:37 AM UTC 25 |
| Peak memory | 154536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291915573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7 .prim_sync_alert.291915573 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/7.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/8.prim_sync_alert.2383743525 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9536569 ps |
| CPU time | 0.32 seconds |
| Started | Feb 08 07:33:35 AM UTC 25 |
| Finished | Feb 08 07:33:37 AM UTC 25 |
| Peak memory | 154536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383743525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2383743525 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/8.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert/9.prim_sync_alert.1509890829 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9330723 ps |
| CPU time | 0.32 seconds |
| Started | Feb 08 07:33:35 AM UTC 25 |
| Finished | Feb 08 07:33:37 AM UTC 25 |
| Peak memory | 154532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509890829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1509890829 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/9.prim_sync_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.71298950 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 26507335 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:39 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71298950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.71298950 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.120672174 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 27535799 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:39 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120672174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nul l -cm_name 1.prim_sync_fatal_alert.120672174 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.957910660 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 29015104 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 07:33:38 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957910660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nul l -cm_name 10.prim_sync_fatal_alert.957910660 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/10.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.370309685 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27726478 ps |
| CPU time | 0.35 seconds |
| Started | Feb 08 07:33:38 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370309685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nul l -cm_name 11.prim_sync_fatal_alert.370309685 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/11.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.49389294 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27267672 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 07:33:38 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49389294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.49389294 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/12.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1210686005 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27850066 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 07:33:38 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210686005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 13.prim_sync_fatal_alert.1210686005 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/13.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1032297940 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27331795 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 07:33:38 AM UTC 25 |
| Finished | Feb 08 07:33:41 AM UTC 25 |
| Peak memory | 154176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032297940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 14.prim_sync_fatal_alert.1032297940 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/14.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.895867095 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27679953 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 07:33:38 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895867095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nul l -cm_name 15.prim_sync_fatal_alert.895867095 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/15.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.958827485 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 23968858 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 07:33:39 AM UTC 25 |
| Finished | Feb 08 07:33:41 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958827485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nul l -cm_name 16.prim_sync_fatal_alert.958827485 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/16.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1180392026 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 28917584 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 07:33:39 AM UTC 25 |
| Finished | Feb 08 07:33:41 AM UTC 25 |
| Peak memory | 154176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180392026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 17.prim_sync_fatal_alert.1180392026 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/17.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1062721093 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 27849197 ps |
| CPU time | 0.39 seconds |
| Started | Feb 08 07:33:39 AM UTC 25 |
| Finished | Feb 08 07:33:41 AM UTC 25 |
| Peak memory | 154176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062721093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 18.prim_sync_fatal_alert.1062721093 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2616526098 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 27146571 ps |
| CPU time | 0.39 seconds |
| Started | Feb 08 07:33:39 AM UTC 25 |
| Finished | Feb 08 07:33:41 AM UTC 25 |
| Peak memory | 154176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616526098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 19.prim_sync_fatal_alert.2616526098 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/19.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.796507734 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 29841035 ps |
| CPU time | 0.38 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:39 AM UTC 25 |
| Peak memory | 154244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796507734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nul l -cm_name 2.prim_sync_fatal_alert.796507734 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3380314183 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 29416460 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:36 AM UTC 25 |
| Finished | Feb 08 07:33:39 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380314183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 3.prim_sync_fatal_alert.3380314183 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1007949618 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28030299 ps |
| CPU time | 0.37 seconds |
| Started | Feb 08 07:33:37 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007949618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 4.prim_sync_fatal_alert.1007949618 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2178928773 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 26671785 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 07:33:37 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178928773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 5.prim_sync_fatal_alert.2178928773 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3377139994 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 28006641 ps |
| CPU time | 0.4 seconds |
| Started | Feb 08 07:33:37 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377139994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 6.prim_sync_fatal_alert.3377139994 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.686916592 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26611365 ps |
| CPU time | 0.35 seconds |
| Started | Feb 08 07:33:38 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686916592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nul l -cm_name 7.prim_sync_fatal_alert.686916592 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2557346184 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28235395 ps |
| CPU time | 0.38 seconds |
| Started | Feb 08 07:33:38 AM UTC 25 |
| Finished | Feb 08 07:33:40 AM UTC 25 |
| Peak memory | 154180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557346184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/nu ll -cm_name 9.prim_sync_fatal_alert.2557346184 |
| Directory | /workspaces/repo/scratch/os_regression/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest |
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