| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.70 | 86.70 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/16.prim_esc_test.1683063732 |
| 88.44 | 1.74 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/18.prim_esc_test.2664656508 |
| 89.58 | 1.14 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.2212593796 |
| 90.72 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1504456597 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/3.prim_esc_test.2125464825 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.4035654156 |
| /workspace/coverage/default/11.prim_esc_test.496360922 |
| /workspace/coverage/default/12.prim_esc_test.1663940527 |
| /workspace/coverage/default/13.prim_esc_test.2618958390 |
| /workspace/coverage/default/14.prim_esc_test.213534803 |
| /workspace/coverage/default/15.prim_esc_test.678724012 |
| /workspace/coverage/default/17.prim_esc_test.2357464223 |
| /workspace/coverage/default/19.prim_esc_test.1003384999 |
| /workspace/coverage/default/2.prim_esc_test.2341669390 |
| /workspace/coverage/default/4.prim_esc_test.868552261 |
| /workspace/coverage/default/5.prim_esc_test.369073129 |
| /workspace/coverage/default/6.prim_esc_test.3742381903 |
| /workspace/coverage/default/7.prim_esc_test.516798154 |
| /workspace/coverage/default/8.prim_esc_test.1545786882 |
| /workspace/coverage/default/9.prim_esc_test.2339390484 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_esc_test.1663940527 | May 26 01:11:20 AM PDT 23 | May 26 01:11:20 AM PDT 23 | 5512235 ps | ||
| T2 | /workspace/coverage/default/10.prim_esc_test.1504456597 | May 26 01:11:27 AM PDT 23 | May 26 01:11:28 AM PDT 23 | 5059576 ps | ||
| T3 | /workspace/coverage/default/8.prim_esc_test.1545786882 | May 26 01:11:20 AM PDT 23 | May 26 01:11:21 AM PDT 23 | 5084602 ps | ||
| T13 | /workspace/coverage/default/15.prim_esc_test.678724012 | May 26 01:11:35 AM PDT 23 | May 26 01:11:36 AM PDT 23 | 4679358 ps | ||
| T6 | /workspace/coverage/default/14.prim_esc_test.213534803 | May 26 01:11:19 AM PDT 23 | May 26 01:11:20 AM PDT 23 | 5080175 ps | ||
| T14 | /workspace/coverage/default/5.prim_esc_test.369073129 | May 26 01:11:19 AM PDT 23 | May 26 01:11:20 AM PDT 23 | 5339857 ps | ||
| T4 | /workspace/coverage/default/16.prim_esc_test.1683063732 | May 26 01:11:29 AM PDT 23 | May 26 01:11:30 AM PDT 23 | 4557841 ps | ||
| T7 | /workspace/coverage/default/9.prim_esc_test.2339390484 | May 26 01:11:27 AM PDT 23 | May 26 01:11:27 AM PDT 23 | 4486811 ps | ||
| T15 | /workspace/coverage/default/1.prim_esc_test.4035654156 | May 26 01:11:24 AM PDT 23 | May 26 01:11:25 AM PDT 23 | 5084337 ps | ||
| T5 | /workspace/coverage/default/17.prim_esc_test.2357464223 | May 26 01:11:32 AM PDT 23 | May 26 01:11:33 AM PDT 23 | 5107664 ps | ||
| T16 | /workspace/coverage/default/11.prim_esc_test.496360922 | May 26 01:11:24 AM PDT 23 | May 26 01:11:24 AM PDT 23 | 5477044 ps | ||
| T17 | /workspace/coverage/default/7.prim_esc_test.516798154 | May 26 01:11:24 AM PDT 23 | May 26 01:11:25 AM PDT 23 | 4058766 ps | ||
| T18 | /workspace/coverage/default/4.prim_esc_test.868552261 | May 26 01:11:32 AM PDT 23 | May 26 01:11:32 AM PDT 23 | 4778113 ps | ||
| T11 | /workspace/coverage/default/0.prim_esc_test.2212593796 | May 26 01:11:20 AM PDT 23 | May 26 01:11:21 AM PDT 23 | 5081883 ps | ||
| T19 | /workspace/coverage/default/6.prim_esc_test.3742381903 | May 26 01:11:24 AM PDT 23 | May 26 01:11:25 AM PDT 23 | 4798091 ps | ||
| T12 | /workspace/coverage/default/19.prim_esc_test.1003384999 | May 26 01:11:27 AM PDT 23 | May 26 01:11:28 AM PDT 23 | 4923197 ps | ||
| T8 | /workspace/coverage/default/18.prim_esc_test.2664656508 | May 26 01:11:27 AM PDT 23 | May 26 01:11:28 AM PDT 23 | 4336489 ps | ||
| T20 | /workspace/coverage/default/2.prim_esc_test.2341669390 | May 26 01:11:26 AM PDT 23 | May 26 01:11:27 AM PDT 23 | 4712621 ps | ||
| T9 | /workspace/coverage/default/13.prim_esc_test.2618958390 | May 26 01:11:35 AM PDT 23 | May 26 01:11:35 AM PDT 23 | 4596956 ps | ||
| T10 | /workspace/coverage/default/3.prim_esc_test.2125464825 | May 26 01:11:26 AM PDT 23 | May 26 01:11:27 AM PDT 23 | 4584316 ps |
| Test location | /workspace/coverage/default/16.prim_esc_test.1683063732 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4557841 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:11:29 AM PDT 23 |
| Finished | May 26 01:11:30 AM PDT 23 |
| Peak memory | 145792 kb |
| Host | smart-aabe2094-1c9e-4d4d-a6e5-465a22ba2315 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683063732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1683063732 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2664656508 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4336489 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:11:27 AM PDT 23 |
| Finished | May 26 01:11:28 AM PDT 23 |
| Peak memory | 145672 kb |
| Host | smart-00cae695-7766-4082-8f38-4244eb5072e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664656508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2664656508 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2212593796 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5081883 ps |
| CPU time | 0.39 seconds |
| Started | May 26 01:11:20 AM PDT 23 |
| Finished | May 26 01:11:21 AM PDT 23 |
| Peak memory | 145760 kb |
| Host | smart-5dbfefe5-fb30-4fc0-9351-5bd1d5f5814d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2212593796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2212593796 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1504456597 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5059576 ps |
| CPU time | 0.36 seconds |
| Started | May 26 01:11:27 AM PDT 23 |
| Finished | May 26 01:11:28 AM PDT 23 |
| Peak memory | 145792 kb |
| Host | smart-1845d90d-1537-4769-882a-9f38baf763d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1504456597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1504456597 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2125464825 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4584316 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:11:26 AM PDT 23 |
| Finished | May 26 01:11:27 AM PDT 23 |
| Peak memory | 145780 kb |
| Host | smart-138a52f8-d8ca-4b8e-a647-f1af7e55e350 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125464825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2125464825 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.4035654156 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5084337 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:11:24 AM PDT 23 |
| Finished | May 26 01:11:25 AM PDT 23 |
| Peak memory | 145760 kb |
| Host | smart-382bb47a-51e3-42b1-ac1b-3c24dcfd9770 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4035654156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4035654156 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.496360922 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5477044 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:11:24 AM PDT 23 |
| Finished | May 26 01:11:24 AM PDT 23 |
| Peak memory | 145760 kb |
| Host | smart-51447ee9-8c15-4289-91fa-0673f23df100 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496360922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.496360922 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1663940527 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5512235 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:11:20 AM PDT 23 |
| Finished | May 26 01:11:20 AM PDT 23 |
| Peak memory | 145792 kb |
| Host | smart-6de71935-3552-46a3-951e-3ce8bfb3076f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663940527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1663940527 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2618958390 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4596956 ps |
| CPU time | 0.36 seconds |
| Started | May 26 01:11:35 AM PDT 23 |
| Finished | May 26 01:11:35 AM PDT 23 |
| Peak memory | 145792 kb |
| Host | smart-292b969f-acd1-4388-a80a-83d5044daec3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618958390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2618958390 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.213534803 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5080175 ps |
| CPU time | 0.36 seconds |
| Started | May 26 01:11:19 AM PDT 23 |
| Finished | May 26 01:11:20 AM PDT 23 |
| Peak memory | 145760 kb |
| Host | smart-d395ed4c-3e53-446c-8ac5-f4c7c0ccb552 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=213534803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.213534803 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.678724012 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4679358 ps |
| CPU time | 0.36 seconds |
| Started | May 26 01:11:35 AM PDT 23 |
| Finished | May 26 01:11:36 AM PDT 23 |
| Peak memory | 145760 kb |
| Host | smart-a8cb7b02-f41e-4d97-b0bb-280fda6ff77a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=678724012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.678724012 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2357464223 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5107664 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:11:32 AM PDT 23 |
| Finished | May 26 01:11:33 AM PDT 23 |
| Peak memory | 145792 kb |
| Host | smart-5fa928e3-87d9-4ee4-9d5d-f8d6616630eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357464223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2357464223 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1003384999 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4923197 ps |
| CPU time | 0.42 seconds |
| Started | May 26 01:11:27 AM PDT 23 |
| Finished | May 26 01:11:28 AM PDT 23 |
| Peak memory | 145720 kb |
| Host | smart-15f4863e-f2e5-43fd-a2b6-f5b7c6d9ad1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003384999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1003384999 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2341669390 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4712621 ps |
| CPU time | 0.4 seconds |
| Started | May 26 01:11:26 AM PDT 23 |
| Finished | May 26 01:11:27 AM PDT 23 |
| Peak memory | 145780 kb |
| Host | smart-047fbc96-6f9b-426d-a763-b9fc23026c08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2341669390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2341669390 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.868552261 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4778113 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:11:32 AM PDT 23 |
| Finished | May 26 01:11:32 AM PDT 23 |
| Peak memory | 145760 kb |
| Host | smart-46616d6f-10cd-4fe1-b5c9-fda66fb3f6a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868552261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.868552261 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.369073129 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5339857 ps |
| CPU time | 0.37 seconds |
| Started | May 26 01:11:19 AM PDT 23 |
| Finished | May 26 01:11:20 AM PDT 23 |
| Peak memory | 145760 kb |
| Host | smart-a91f878d-417e-46fe-817e-8cb1e4859ab2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369073129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.369073129 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3742381903 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4798091 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:11:24 AM PDT 23 |
| Finished | May 26 01:11:25 AM PDT 23 |
| Peak memory | 145760 kb |
| Host | smart-82623a80-b60c-4dad-8105-b4ff742f8a89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3742381903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3742381903 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.516798154 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4058766 ps |
| CPU time | 0.38 seconds |
| Started | May 26 01:11:24 AM PDT 23 |
| Finished | May 26 01:11:25 AM PDT 23 |
| Peak memory | 145760 kb |
| Host | smart-1450a641-c12a-41e7-9651-05e187286bda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516798154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.516798154 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1545786882 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5084602 ps |
| CPU time | 0.41 seconds |
| Started | May 26 01:11:20 AM PDT 23 |
| Finished | May 26 01:11:21 AM PDT 23 |
| Peak memory | 145760 kb |
| Host | smart-535984bc-3248-440f-8f95-1acac9bca1f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545786882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1545786882 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2339390484 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4486811 ps |
| CPU time | 0.42 seconds |
| Started | May 26 01:11:27 AM PDT 23 |
| Finished | May 26 01:11:27 AM PDT 23 |
| Peak memory | 145780 kb |
| Host | smart-ff470ab2-adab-41c4-a6fa-c3c687f23116 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2339390484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2339390484 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |