Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.80 90.48 86.36 100.00 71.43 79.07 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
84.80 84.80 90.48 90.48 86.36 86.36 100.00 100.00 71.43 71.43 79.07 79.07 81.48 81.48 /workspace/coverage/default/0.prim_esc_test.57662743761270458788752445938769221980199574670196827890899638857245077315449

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.88274015264979191937647063014881700033968097888949087694855510308435356246192
/workspace/coverage/default/10.prim_esc_test.87481419347611102107984992580972583678625546800728086446004069429670375321811
/workspace/coverage/default/11.prim_esc_test.32018126556518557414734541439615750186404297215596119961160935641032086897283
/workspace/coverage/default/12.prim_esc_test.85994120320807733154941984024586167564995125620876383599162220759286593781581
/workspace/coverage/default/13.prim_esc_test.92768229101556278059300454786028348642389273938736204923692833097326977622956
/workspace/coverage/default/14.prim_esc_test.104070077826902435070527788321053148842326865444777171196946948721409261634082
/workspace/coverage/default/15.prim_esc_test.109083962580874091624555454221559641674898949918389811144410861965819222470887
/workspace/coverage/default/16.prim_esc_test.104630038974722326237777748597571640414384022030416933113824577924975843718095
/workspace/coverage/default/17.prim_esc_test.108732087382122813246171196450828491401756040269524642172979387629797659400129
/workspace/coverage/default/18.prim_esc_test.34066055516229913917766341204644387615741076758068109287083537137419025790633
/workspace/coverage/default/19.prim_esc_test.113245580524093327978569243605327747762195175348423947689084254373739210051837
/workspace/coverage/default/2.prim_esc_test.61659735837163208032281785208616179344881802809629994658311318062548713939919
/workspace/coverage/default/3.prim_esc_test.62391186608949063248433440754779542301174299606050418461177138485287945525164
/workspace/coverage/default/4.prim_esc_test.80119851519376336714985645735305983921137287143336533486952274478219835766796
/workspace/coverage/default/5.prim_esc_test.54495577575878063060152217279943093966148553908879607563636556403341083780603
/workspace/coverage/default/6.prim_esc_test.104494606205441959258227970946394615983401934549988346360490306255946026062774
/workspace/coverage/default/7.prim_esc_test.2566573335474430641058326711650772785582231232041243654762541245318931596547
/workspace/coverage/default/8.prim_esc_test.8734394455108164000662379493325796082161900235172075126558035180145106743535
/workspace/coverage/default/9.prim_esc_test.79436534676289328091522004075157718729812661445848086674894905418380829484199



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/13.prim_esc_test.92768229101556278059300454786028348642389273938736204923692833097326977622956 Nov 22 12:39:13 PM PST 23 Nov 22 12:39:16 PM PST 23 4799183 ps
T2 /workspace/coverage/default/12.prim_esc_test.85994120320807733154941984024586167564995125620876383599162220759286593781581 Nov 22 12:39:24 PM PST 23 Nov 22 12:39:26 PM PST 23 4799183 ps
T3 /workspace/coverage/default/14.prim_esc_test.104070077826902435070527788321053148842326865444777171196946948721409261634082 Nov 22 12:39:25 PM PST 23 Nov 22 12:39:28 PM PST 23 4799183 ps
T4 /workspace/coverage/default/10.prim_esc_test.87481419347611102107984992580972583678625546800728086446004069429670375321811 Nov 22 12:39:20 PM PST 23 Nov 22 12:39:23 PM PST 23 4799183 ps
T5 /workspace/coverage/default/0.prim_esc_test.57662743761270458788752445938769221980199574670196827890899638857245077315449 Nov 22 12:39:15 PM PST 23 Nov 22 12:39:19 PM PST 23 4799183 ps
T6 /workspace/coverage/default/5.prim_esc_test.54495577575878063060152217279943093966148553908879607563636556403341083780603 Nov 22 12:39:13 PM PST 23 Nov 22 12:39:14 PM PST 23 4799183 ps
T7 /workspace/coverage/default/17.prim_esc_test.108732087382122813246171196450828491401756040269524642172979387629797659400129 Nov 22 12:39:25 PM PST 23 Nov 22 12:39:28 PM PST 23 4799183 ps
T8 /workspace/coverage/default/9.prim_esc_test.79436534676289328091522004075157718729812661445848086674894905418380829484199 Nov 22 12:39:13 PM PST 23 Nov 22 12:39:15 PM PST 23 4799183 ps
T9 /workspace/coverage/default/1.prim_esc_test.88274015264979191937647063014881700033968097888949087694855510308435356246192 Nov 22 12:39:14 PM PST 23 Nov 22 12:39:17 PM PST 23 4799183 ps
T10 /workspace/coverage/default/4.prim_esc_test.80119851519376336714985645735305983921137287143336533486952274478219835766796 Nov 22 12:39:16 PM PST 23 Nov 22 12:39:19 PM PST 23 4799183 ps
T11 /workspace/coverage/default/18.prim_esc_test.34066055516229913917766341204644387615741076758068109287083537137419025790633 Nov 22 12:39:29 PM PST 23 Nov 22 12:39:33 PM PST 23 4799183 ps
T12 /workspace/coverage/default/2.prim_esc_test.61659735837163208032281785208616179344881802809629994658311318062548713939919 Nov 22 12:39:16 PM PST 23 Nov 22 12:39:19 PM PST 23 4799183 ps
T13 /workspace/coverage/default/7.prim_esc_test.2566573335474430641058326711650772785582231232041243654762541245318931596547 Nov 22 12:39:16 PM PST 23 Nov 22 12:39:20 PM PST 23 4799183 ps
T14 /workspace/coverage/default/15.prim_esc_test.109083962580874091624555454221559641674898949918389811144410861965819222470887 Nov 22 12:39:14 PM PST 23 Nov 22 12:39:16 PM PST 23 4799183 ps
T15 /workspace/coverage/default/3.prim_esc_test.62391186608949063248433440754779542301174299606050418461177138485287945525164 Nov 22 12:39:16 PM PST 23 Nov 22 12:39:19 PM PST 23 4799183 ps
T16 /workspace/coverage/default/6.prim_esc_test.104494606205441959258227970946394615983401934549988346360490306255946026062774 Nov 22 12:39:12 PM PST 23 Nov 22 12:39:14 PM PST 23 4799183 ps
T17 /workspace/coverage/default/19.prim_esc_test.113245580524093327978569243605327747762195175348423947689084254373739210051837 Nov 22 12:39:17 PM PST 23 Nov 22 12:39:21 PM PST 23 4799183 ps
T18 /workspace/coverage/default/16.prim_esc_test.104630038974722326237777748597571640414384022030416933113824577924975843718095 Nov 22 12:39:13 PM PST 23 Nov 22 12:39:16 PM PST 23 4799183 ps
T19 /workspace/coverage/default/11.prim_esc_test.32018126556518557414734541439615750186404297215596119961160935641032086897283 Nov 22 12:39:13 PM PST 23 Nov 22 12:39:16 PM PST 23 4799183 ps
T20 /workspace/coverage/default/8.prim_esc_test.8734394455108164000662379493325796082161900235172075126558035180145106743535 Nov 22 12:39:12 PM PST 23 Nov 22 12:39:14 PM PST 23 4799183 ps

Test location /workspace/coverage/default/0.prim_esc_test.57662743761270458788752445938769221980199574670196827890899638857245077315449
Short name T5
Test name
Test status
Simulation time 4799183 ps
CPU time 0.4 seconds
Started Nov 22 12:39:15 PM PST 23
Finished Nov 22 12:39:19 PM PST 23
Peak memory 145884 kb
Host smart-2686c4b5-e5d9-4119-ab71-d09bcb6c05dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57662743761270458788752445938769221980199574670196827890899638857245077315449 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.5766274376
1270458788752445938769221980199574670196827890899638857245077315449
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.88274015264979191937647063014881700033968097888949087694855510308435356246192
Short name T9
Test name
Test status
Simulation time 4799183 ps
CPU time 0.37 seconds
Started Nov 22 12:39:14 PM PST 23
Finished Nov 22 12:39:17 PM PST 23
Peak memory 145896 kb
Host smart-ade31898-8f23-421b-b274-bcf823c09da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88274015264979191937647063014881700033968097888949087694855510308435356246192 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.8827401526
4979191937647063014881700033968097888949087694855510308435356246192
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.87481419347611102107984992580972583678625546800728086446004069429670375321811
Short name T4
Test name
Test status
Simulation time 4799183 ps
CPU time 0.41 seconds
Started Nov 22 12:39:20 PM PST 23
Finished Nov 22 12:39:23 PM PST 23
Peak memory 145948 kb
Host smart-5c957f4d-e2b9-4696-8fa2-5e54ad234fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87481419347611102107984992580972583678625546800728086446004069429670375321811 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.874814193
47611102107984992580972583678625546800728086446004069429670375321811
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.32018126556518557414734541439615750186404297215596119961160935641032086897283
Short name T19
Test name
Test status
Simulation time 4799183 ps
CPU time 0.39 seconds
Started Nov 22 12:39:13 PM PST 23
Finished Nov 22 12:39:16 PM PST 23
Peak memory 145908 kb
Host smart-2c1b282d-0ed4-4ec4-9d33-93e13681b565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32018126556518557414734541439615750186404297215596119961160935641032086897283 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.320181265
56518557414734541439615750186404297215596119961160935641032086897283
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.85994120320807733154941984024586167564995125620876383599162220759286593781581
Short name T2
Test name
Test status
Simulation time 4799183 ps
CPU time 0.37 seconds
Started Nov 22 12:39:24 PM PST 23
Finished Nov 22 12:39:26 PM PST 23
Peak memory 145964 kb
Host smart-f13dbe99-26c7-4d6f-acbe-8220b75b28a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85994120320807733154941984024586167564995125620876383599162220759286593781581 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.859941203
20807733154941984024586167564995125620876383599162220759286593781581
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.92768229101556278059300454786028348642389273938736204923692833097326977622956
Short name T1
Test name
Test status
Simulation time 4799183 ps
CPU time 0.38 seconds
Started Nov 22 12:39:13 PM PST 23
Finished Nov 22 12:39:16 PM PST 23
Peak memory 145856 kb
Host smart-760228b2-41da-456b-8300-7899990854ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92768229101556278059300454786028348642389273938736204923692833097326977622956 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.927682291
01556278059300454786028348642389273938736204923692833097326977622956
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.104070077826902435070527788321053148842326865444777171196946948721409261634082
Short name T3
Test name
Test status
Simulation time 4799183 ps
CPU time 0.37 seconds
Started Nov 22 12:39:25 PM PST 23
Finished Nov 22 12:39:28 PM PST 23
Peak memory 145792 kb
Host smart-2b1b84e6-bcec-4f1e-89d4-0e079ab66681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104070077826902435070527788321053148842326865444777171196946948721409261634082 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.10407007
7826902435070527788321053148842326865444777171196946948721409261634082
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.109083962580874091624555454221559641674898949918389811144410861965819222470887
Short name T14
Test name
Test status
Simulation time 4799183 ps
CPU time 0.37 seconds
Started Nov 22 12:39:14 PM PST 23
Finished Nov 22 12:39:16 PM PST 23
Peak memory 145868 kb
Host smart-0fb72ba8-c49c-4643-b71c-9a4d40cf4750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109083962580874091624555454221559641674898949918389811144410861965819222470887 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.10908396
2580874091624555454221559641674898949918389811144410861965819222470887
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.104630038974722326237777748597571640414384022030416933113824577924975843718095
Short name T18
Test name
Test status
Simulation time 4799183 ps
CPU time 0.38 seconds
Started Nov 22 12:39:13 PM PST 23
Finished Nov 22 12:39:16 PM PST 23
Peak memory 145868 kb
Host smart-c3e62d94-87df-49ce-80f0-0dea6aee06a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104630038974722326237777748597571640414384022030416933113824577924975843718095 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.10463003
8974722326237777748597571640414384022030416933113824577924975843718095
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.108732087382122813246171196450828491401756040269524642172979387629797659400129
Short name T7
Test name
Test status
Simulation time 4799183 ps
CPU time 0.39 seconds
Started Nov 22 12:39:25 PM PST 23
Finished Nov 22 12:39:28 PM PST 23
Peak memory 145940 kb
Host smart-4a46e922-4128-41b9-b04e-031c985fcc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108732087382122813246171196450828491401756040269524642172979387629797659400129 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.10873208
7382122813246171196450828491401756040269524642172979387629797659400129
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.34066055516229913917766341204644387615741076758068109287083537137419025790633
Short name T11
Test name
Test status
Simulation time 4799183 ps
CPU time 0.38 seconds
Started Nov 22 12:39:29 PM PST 23
Finished Nov 22 12:39:33 PM PST 23
Peak memory 145892 kb
Host smart-f2e734b6-25eb-416c-bdb0-d1973a10f76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34066055516229913917766341204644387615741076758068109287083537137419025790633 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.340660555
16229913917766341204644387615741076758068109287083537137419025790633
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.113245580524093327978569243605327747762195175348423947689084254373739210051837
Short name T17
Test name
Test status
Simulation time 4799183 ps
CPU time 0.37 seconds
Started Nov 22 12:39:17 PM PST 23
Finished Nov 22 12:39:21 PM PST 23
Peak memory 145888 kb
Host smart-a9de4e55-00d1-46af-8da3-1bf76d4c454e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113245580524093327978569243605327747762195175348423947689084254373739210051837 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.11324558
0524093327978569243605327747762195175348423947689084254373739210051837
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.61659735837163208032281785208616179344881802809629994658311318062548713939919
Short name T12
Test name
Test status
Simulation time 4799183 ps
CPU time 0.39 seconds
Started Nov 22 12:39:16 PM PST 23
Finished Nov 22 12:39:19 PM PST 23
Peak memory 145856 kb
Host smart-c7fc9b3e-f8a2-46e9-9212-ea02a8a24872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61659735837163208032281785208616179344881802809629994658311318062548713939919 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.6165973583
7163208032281785208616179344881802809629994658311318062548713939919
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.62391186608949063248433440754779542301174299606050418461177138485287945525164
Short name T15
Test name
Test status
Simulation time 4799183 ps
CPU time 0.37 seconds
Started Nov 22 12:39:16 PM PST 23
Finished Nov 22 12:39:19 PM PST 23
Peak memory 145968 kb
Host smart-66604ab7-12d2-463b-9adc-7d669352a2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62391186608949063248433440754779542301174299606050418461177138485287945525164 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.6239118660
8949063248433440754779542301174299606050418461177138485287945525164
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.80119851519376336714985645735305983921137287143336533486952274478219835766796
Short name T10
Test name
Test status
Simulation time 4799183 ps
CPU time 0.37 seconds
Started Nov 22 12:39:16 PM PST 23
Finished Nov 22 12:39:19 PM PST 23
Peak memory 145896 kb
Host smart-61c8b1e4-e194-429c-b573-a52f3cc41070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80119851519376336714985645735305983921137287143336533486952274478219835766796 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.8011985151
9376336714985645735305983921137287143336533486952274478219835766796
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.54495577575878063060152217279943093966148553908879607563636556403341083780603
Short name T6
Test name
Test status
Simulation time 4799183 ps
CPU time 0.36 seconds
Started Nov 22 12:39:13 PM PST 23
Finished Nov 22 12:39:14 PM PST 23
Peak memory 145900 kb
Host smart-3c776244-1c84-4727-91b7-6077c1ffce85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54495577575878063060152217279943093966148553908879607563636556403341083780603 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.5449557757
5878063060152217279943093966148553908879607563636556403341083780603
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.104494606205441959258227970946394615983401934549988346360490306255946026062774
Short name T16
Test name
Test status
Simulation time 4799183 ps
CPU time 0.37 seconds
Started Nov 22 12:39:12 PM PST 23
Finished Nov 22 12:39:14 PM PST 23
Peak memory 145896 kb
Host smart-32964b0a-f260-4bc7-939c-64340c7e4752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104494606205441959258227970946394615983401934549988346360490306255946026062774 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.104494606
205441959258227970946394615983401934549988346360490306255946026062774
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.2566573335474430641058326711650772785582231232041243654762541245318931596547
Short name T13
Test name
Test status
Simulation time 4799183 ps
CPU time 0.37 seconds
Started Nov 22 12:39:16 PM PST 23
Finished Nov 22 12:39:20 PM PST 23
Peak memory 145896 kb
Host smart-8a4388e3-6f7b-4bf9-a4af-cbdfd90d3fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566573335474430641058326711650772785582231232041243654762541245318931596547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST
_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.25665733354
74430641058326711650772785582231232041243654762541245318931596547
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.8734394455108164000662379493325796082161900235172075126558035180145106743535
Short name T20
Test name
Test status
Simulation time 4799183 ps
CPU time 0.37 seconds
Started Nov 22 12:39:12 PM PST 23
Finished Nov 22 12:39:14 PM PST 23
Peak memory 145896 kb
Host smart-d801f8de-aefd-413a-a731-1ea77a10008b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8734394455108164000662379493325796082161900235172075126558035180145106743535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST
_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.87343944551
08164000662379493325796082161900235172075126558035180145106743535
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.79436534676289328091522004075157718729812661445848086674894905418380829484199
Short name T8
Test name
Test status
Simulation time 4799183 ps
CPU time 0.38 seconds
Started Nov 22 12:39:13 PM PST 23
Finished Nov 22 12:39:15 PM PST 23
Peak memory 145912 kb
Host smart-4530dada-c8f6-4823-82fa-7c0ba07e499a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79436534676289328091522004075157718729812661445848086674894905418380829484199 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.7943653467
6289328091522004075157718729812661445848086674894905418380829484199
Directory /workspace/9.prim_esc_test/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%