Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.35 85.35 92.38 92.38 81.82 81.82 100.00 100.00 75.00 75.00 81.40 81.40 81.48 81.48 /workspace/coverage/default/2.prim_esc_test.696903587
88.44 3.09 93.33 0.95 86.36 4.55 100.00 0.00 85.71 10.71 83.72 2.33 81.48 0.00 /workspace/coverage/default/8.prim_esc_test.178890346
89.58 1.14 94.29 0.95 86.36 0.00 100.00 0.00 89.29 3.57 86.05 2.33 81.48 0.00 /workspace/coverage/default/11.prim_esc_test.1570996211
90.72 1.14 95.24 0.95 86.36 0.00 100.00 0.00 92.86 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/15.prim_esc_test.3543626174
91.31 0.60 95.24 0.00 86.36 0.00 100.00 0.00 96.43 3.57 88.37 0.00 81.48 0.00 /workspace/coverage/default/12.prim_esc_test.3796968648

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.3383199113
/workspace/coverage/default/1.prim_esc_test.2350153738
/workspace/coverage/default/10.prim_esc_test.1104045612
/workspace/coverage/default/13.prim_esc_test.4055158533
/workspace/coverage/default/14.prim_esc_test.1430516574
/workspace/coverage/default/16.prim_esc_test.1525951352
/workspace/coverage/default/17.prim_esc_test.915045920
/workspace/coverage/default/18.prim_esc_test.3254603252
/workspace/coverage/default/19.prim_esc_test.2179928260
/workspace/coverage/default/3.prim_esc_test.3379327992
/workspace/coverage/default/4.prim_esc_test.693271274
/workspace/coverage/default/5.prim_esc_test.3060817081
/workspace/coverage/default/6.prim_esc_test.4067939488
/workspace/coverage/default/7.prim_esc_test.630167984
/workspace/coverage/default/9.prim_esc_test.2961406532



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/8.prim_esc_test.178890346 Dec 20 12:17:09 PM PST 23 Dec 20 12:17:19 PM PST 23 4525419 ps
T2 /workspace/coverage/default/4.prim_esc_test.693271274 Dec 20 12:17:10 PM PST 23 Dec 20 12:17:19 PM PST 23 4642831 ps
T3 /workspace/coverage/default/3.prim_esc_test.3379327992 Dec 20 12:17:05 PM PST 23 Dec 20 12:17:13 PM PST 23 4677997 ps
T7 /workspace/coverage/default/6.prim_esc_test.4067939488 Dec 20 12:17:04 PM PST 23 Dec 20 12:17:10 PM PST 23 4586650 ps
T11 /workspace/coverage/default/10.prim_esc_test.1104045612 Dec 20 12:17:09 PM PST 23 Dec 20 12:17:19 PM PST 23 4181829 ps
T8 /workspace/coverage/default/5.prim_esc_test.3060817081 Dec 20 12:16:50 PM PST 23 Dec 20 12:16:54 PM PST 23 5200571 ps
T4 /workspace/coverage/default/2.prim_esc_test.696903587 Dec 20 12:17:09 PM PST 23 Dec 20 12:17:19 PM PST 23 5149134 ps
T16 /workspace/coverage/default/0.prim_esc_test.3383199113 Dec 20 12:16:43 PM PST 23 Dec 20 12:16:47 PM PST 23 5900566 ps
T12 /workspace/coverage/default/9.prim_esc_test.2961406532 Dec 20 12:17:09 PM PST 23 Dec 20 12:17:19 PM PST 23 4702163 ps
T17 /workspace/coverage/default/14.prim_esc_test.1430516574 Dec 20 12:17:06 PM PST 23 Dec 20 12:17:16 PM PST 23 4257872 ps
T5 /workspace/coverage/default/12.prim_esc_test.3796968648 Dec 20 12:17:04 PM PST 23 Dec 20 12:17:09 PM PST 23 5008822 ps
T9 /workspace/coverage/default/15.prim_esc_test.3543626174 Dec 20 12:17:04 PM PST 23 Dec 20 12:17:09 PM PST 23 5128953 ps
T6 /workspace/coverage/default/18.prim_esc_test.3254603252 Dec 20 12:17:05 PM PST 23 Dec 20 12:17:10 PM PST 23 4961645 ps
T18 /workspace/coverage/default/19.prim_esc_test.2179928260 Dec 20 12:18:43 PM PST 23 Dec 20 12:18:48 PM PST 23 5121543 ps
T13 /workspace/coverage/default/7.prim_esc_test.630167984 Dec 20 12:17:04 PM PST 23 Dec 20 12:17:09 PM PST 23 5300893 ps
T14 /workspace/coverage/default/11.prim_esc_test.1570996211 Dec 20 12:17:05 PM PST 23 Dec 20 12:17:10 PM PST 23 4102053 ps
T19 /workspace/coverage/default/1.prim_esc_test.2350153738 Dec 20 12:17:10 PM PST 23 Dec 20 12:17:19 PM PST 23 4431341 ps
T15 /workspace/coverage/default/17.prim_esc_test.915045920 Dec 20 12:17:05 PM PST 23 Dec 20 12:17:14 PM PST 23 5539114 ps
T10 /workspace/coverage/default/16.prim_esc_test.1525951352 Dec 20 12:17:04 PM PST 23 Dec 20 12:17:10 PM PST 23 4561993 ps
T20 /workspace/coverage/default/13.prim_esc_test.4055158533 Dec 20 12:17:04 PM PST 23 Dec 20 12:17:09 PM PST 23 4553370 ps

Test location /workspace/coverage/default/2.prim_esc_test.696903587
Short name T4
Test name
Test status
Simulation time 5149134 ps
CPU time 0.38 seconds
Started Dec 20 12:17:09 PM PST 23
Finished Dec 20 12:17:19 PM PST 23
Peak memory 145972 kb
Host smart-27939b48-0bfa-4f49-bc02-bc19d49cde9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696903587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.696903587
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.178890346
Short name T1
Test name
Test status
Simulation time 4525419 ps
CPU time 0.39 seconds
Started Dec 20 12:17:09 PM PST 23
Finished Dec 20 12:17:19 PM PST 23
Peak memory 145996 kb
Host smart-1b2254d5-0223-4fed-b8b1-d43341a75533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178890346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.178890346
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1570996211
Short name T14
Test name
Test status
Simulation time 4102053 ps
CPU time 0.37 seconds
Started Dec 20 12:17:05 PM PST 23
Finished Dec 20 12:17:10 PM PST 23
Peak memory 145868 kb
Host smart-490a5761-d96e-4e3c-a9b2-4429286aaaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570996211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1570996211
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.3543626174
Short name T9
Test name
Test status
Simulation time 5128953 ps
CPU time 0.37 seconds
Started Dec 20 12:17:04 PM PST 23
Finished Dec 20 12:17:09 PM PST 23
Peak memory 145912 kb
Host smart-e1c83d40-dcea-40d5-88ef-67539915ce95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543626174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3543626174
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.3796968648
Short name T5
Test name
Test status
Simulation time 5008822 ps
CPU time 0.38 seconds
Started Dec 20 12:17:04 PM PST 23
Finished Dec 20 12:17:09 PM PST 23
Peak memory 145976 kb
Host smart-62c11f42-67ed-4a5e-b12b-7391e4cb512f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796968648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3796968648
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.3383199113
Short name T16
Test name
Test status
Simulation time 5900566 ps
CPU time 0.37 seconds
Started Dec 20 12:16:43 PM PST 23
Finished Dec 20 12:16:47 PM PST 23
Peak memory 145888 kb
Host smart-6fcd45f6-110b-4565-8234-cf369331db0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383199113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3383199113
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.2350153738
Short name T19
Test name
Test status
Simulation time 4431341 ps
CPU time 0.36 seconds
Started Dec 20 12:17:10 PM PST 23
Finished Dec 20 12:17:19 PM PST 23
Peak memory 145504 kb
Host smart-80a9061a-b92c-48c4-aaca-66078c286023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350153738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2350153738
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.1104045612
Short name T11
Test name
Test status
Simulation time 4181829 ps
CPU time 0.38 seconds
Started Dec 20 12:17:09 PM PST 23
Finished Dec 20 12:17:19 PM PST 23
Peak memory 145632 kb
Host smart-75ed0ea1-85b6-4fe0-ae11-2d90fd5ef4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104045612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1104045612
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.4055158533
Short name T20
Test name
Test status
Simulation time 4553370 ps
CPU time 0.37 seconds
Started Dec 20 12:17:04 PM PST 23
Finished Dec 20 12:17:09 PM PST 23
Peak memory 145884 kb
Host smart-201d9e4f-9b06-47f9-9344-4a59ee630f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055158533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4055158533
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.1430516574
Short name T17
Test name
Test status
Simulation time 4257872 ps
CPU time 0.37 seconds
Started Dec 20 12:17:06 PM PST 23
Finished Dec 20 12:17:16 PM PST 23
Peak memory 145948 kb
Host smart-cad07d8e-c26f-4916-846a-af892708e8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430516574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1430516574
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1525951352
Short name T10
Test name
Test status
Simulation time 4561993 ps
CPU time 0.37 seconds
Started Dec 20 12:17:04 PM PST 23
Finished Dec 20 12:17:10 PM PST 23
Peak memory 145908 kb
Host smart-0d0315cc-7669-4111-b1ed-c32ec53b34da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525951352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1525951352
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.915045920
Short name T15
Test name
Test status
Simulation time 5539114 ps
CPU time 0.38 seconds
Started Dec 20 12:17:05 PM PST 23
Finished Dec 20 12:17:14 PM PST 23
Peak memory 145944 kb
Host smart-cc5868e6-2e4b-4d73-ac64-da36ef8b8d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915045920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.915045920
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.3254603252
Short name T6
Test name
Test status
Simulation time 4961645 ps
CPU time 0.37 seconds
Started Dec 20 12:17:05 PM PST 23
Finished Dec 20 12:17:10 PM PST 23
Peak memory 145888 kb
Host smart-eba9e54d-3a07-4185-9100-48a1deb5d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254603252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3254603252
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2179928260
Short name T18
Test name
Test status
Simulation time 5121543 ps
CPU time 0.38 seconds
Started Dec 20 12:18:43 PM PST 23
Finished Dec 20 12:18:48 PM PST 23
Peak memory 145980 kb
Host smart-bfb66a46-32d1-4e2b-afe7-4a693e36b9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179928260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2179928260
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.3379327992
Short name T3
Test name
Test status
Simulation time 4677997 ps
CPU time 0.4 seconds
Started Dec 20 12:17:05 PM PST 23
Finished Dec 20 12:17:13 PM PST 23
Peak memory 145888 kb
Host smart-70ccf143-e143-40f0-9720-a491527f3ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379327992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3379327992
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.693271274
Short name T2
Test name
Test status
Simulation time 4642831 ps
CPU time 0.37 seconds
Started Dec 20 12:17:10 PM PST 23
Finished Dec 20 12:17:19 PM PST 23
Peak memory 145600 kb
Host smart-b23743b2-41ed-4185-be8c-6d0394c61151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693271274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.693271274
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.3060817081
Short name T8
Test name
Test status
Simulation time 5200571 ps
CPU time 0.37 seconds
Started Dec 20 12:16:50 PM PST 23
Finished Dec 20 12:16:54 PM PST 23
Peak memory 145968 kb
Host smart-4d4c2053-2392-44ce-99c2-bd2a0bbf8ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060817081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3060817081
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.4067939488
Short name T7
Test name
Test status
Simulation time 4586650 ps
CPU time 0.38 seconds
Started Dec 20 12:17:04 PM PST 23
Finished Dec 20 12:17:10 PM PST 23
Peak memory 145900 kb
Host smart-1e932fca-77e8-404c-a432-7ea01711d6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067939488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4067939488
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.630167984
Short name T13
Test name
Test status
Simulation time 5300893 ps
CPU time 0.37 seconds
Started Dec 20 12:17:04 PM PST 23
Finished Dec 20 12:17:09 PM PST 23
Peak memory 145980 kb
Host smart-40ab82c6-0bab-4424-9bd8-96c42f4c08fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630167984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.630167984
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.2961406532
Short name T12
Test name
Test status
Simulation time 4702163 ps
CPU time 0.38 seconds
Started Dec 20 12:17:09 PM PST 23
Finished Dec 20 12:17:19 PM PST 23
Peak memory 145476 kb
Host smart-d4a7a766-d34f-4011-b706-3da02e6dca3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961406532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2961406532
Directory /workspace/9.prim_esc_test/latest
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