| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.10 | 86.10 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/17.prim_esc_test.2756570727 |
| 87.84 | 1.74 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.2708882908 |
| 89.58 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/4.prim_esc_test.230032740 |
| 90.72 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.3886550484 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.2156365555 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.1158329638 |
| /workspace/coverage/default/11.prim_esc_test.2820651457 |
| /workspace/coverage/default/12.prim_esc_test.3550283682 |
| /workspace/coverage/default/13.prim_esc_test.1145777859 |
| /workspace/coverage/default/14.prim_esc_test.1598788776 |
| /workspace/coverage/default/16.prim_esc_test.3877569912 |
| /workspace/coverage/default/18.prim_esc_test.1808929303 |
| /workspace/coverage/default/19.prim_esc_test.708362057 |
| /workspace/coverage/default/2.prim_esc_test.118165375 |
| /workspace/coverage/default/3.prim_esc_test.3712933251 |
| /workspace/coverage/default/5.prim_esc_test.4094030840 |
| /workspace/coverage/default/6.prim_esc_test.540762705 |
| /workspace/coverage/default/7.prim_esc_test.3003470987 |
| /workspace/coverage/default/8.prim_esc_test.3700807283 |
| /workspace/coverage/default/9.prim_esc_test.3245674785 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_esc_test.4094030840 | Dec 24 12:18:59 PM PST 23 | Dec 24 12:19:01 PM PST 23 | 4923327 ps | ||
| T2 | /workspace/coverage/default/4.prim_esc_test.230032740 | Dec 24 12:19:46 PM PST 23 | Dec 24 12:19:49 PM PST 23 | 4893760 ps | ||
| T3 | /workspace/coverage/default/14.prim_esc_test.1598788776 | Dec 24 12:18:59 PM PST 23 | Dec 24 12:19:00 PM PST 23 | 4854706 ps | ||
| T6 | /workspace/coverage/default/11.prim_esc_test.2820651457 | Dec 24 12:18:59 PM PST 23 | Dec 24 12:19:01 PM PST 23 | 4838485 ps | ||
| T4 | /workspace/coverage/default/1.prim_esc_test.1158329638 | Dec 24 12:19:00 PM PST 23 | Dec 24 12:19:02 PM PST 23 | 4464372 ps | ||
| T5 | /workspace/coverage/default/2.prim_esc_test.118165375 | Dec 24 12:19:02 PM PST 23 | Dec 24 12:19:04 PM PST 23 | 4774789 ps | ||
| T9 | /workspace/coverage/default/10.prim_esc_test.2708882908 | Dec 24 12:18:53 PM PST 23 | Dec 24 12:18:55 PM PST 23 | 4372495 ps | ||
| T15 | /workspace/coverage/default/0.prim_esc_test.2156365555 | Dec 24 12:19:02 PM PST 23 | Dec 24 12:19:04 PM PST 23 | 5003996 ps | ||
| T7 | /workspace/coverage/default/17.prim_esc_test.2756570727 | Dec 24 12:19:46 PM PST 23 | Dec 24 12:19:49 PM PST 23 | 4797493 ps | ||
| T16 | /workspace/coverage/default/12.prim_esc_test.3550283682 | Dec 24 12:19:00 PM PST 23 | Dec 24 12:19:02 PM PST 23 | 4599772 ps | ||
| T17 | /workspace/coverage/default/6.prim_esc_test.540762705 | Dec 24 12:19:02 PM PST 23 | Dec 24 12:19:04 PM PST 23 | 4747141 ps | ||
| T11 | /workspace/coverage/default/8.prim_esc_test.3700807283 | Dec 24 12:19:00 PM PST 23 | Dec 24 12:19:02 PM PST 23 | 5290470 ps | ||
| T13 | /workspace/coverage/default/3.prim_esc_test.3712933251 | Dec 24 12:19:02 PM PST 23 | Dec 24 12:19:04 PM PST 23 | 4933251 ps | ||
| T10 | /workspace/coverage/default/7.prim_esc_test.3003470987 | Dec 24 12:19:00 PM PST 23 | Dec 24 12:19:02 PM PST 23 | 4631875 ps | ||
| T18 | /workspace/coverage/default/13.prim_esc_test.1145777859 | Dec 24 12:18:52 PM PST 23 | Dec 24 12:18:53 PM PST 23 | 5043021 ps | ||
| T12 | /workspace/coverage/default/16.prim_esc_test.3877569912 | Dec 24 12:19:00 PM PST 23 | Dec 24 12:19:01 PM PST 23 | 4950507 ps | ||
| T19 | /workspace/coverage/default/19.prim_esc_test.708362057 | Dec 24 12:19:02 PM PST 23 | Dec 24 12:19:04 PM PST 23 | 5287355 ps | ||
| T8 | /workspace/coverage/default/18.prim_esc_test.1808929303 | Dec 24 12:19:00 PM PST 23 | Dec 24 12:19:02 PM PST 23 | 4907812 ps | ||
| T20 | /workspace/coverage/default/9.prim_esc_test.3245674785 | Dec 24 12:19:02 PM PST 23 | Dec 24 12:19:04 PM PST 23 | 5590461 ps | ||
| T14 | /workspace/coverage/default/15.prim_esc_test.3886550484 | Dec 24 12:19:00 PM PST 23 | Dec 24 12:19:02 PM PST 23 | 5307114 ps |
| Test location | /workspace/coverage/default/17.prim_esc_test.2756570727 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4797493 ps |
| CPU time | 0.43 seconds |
| Started | Dec 24 12:19:46 PM PST 23 |
| Finished | Dec 24 12:19:49 PM PST 23 |
| Peak memory | 144384 kb |
| Host | smart-02a3fd03-ec05-4c89-90d8-94272f01faf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756570727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2756570727 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2708882908 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4372495 ps |
| CPU time | 0.43 seconds |
| Started | Dec 24 12:18:53 PM PST 23 |
| Finished | Dec 24 12:18:55 PM PST 23 |
| Peak memory | 145364 kb |
| Host | smart-4600a754-80c0-4ddb-a352-402fb6137961 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708882908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2708882908 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.230032740 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4893760 ps |
| CPU time | 0.42 seconds |
| Started | Dec 24 12:19:46 PM PST 23 |
| Finished | Dec 24 12:19:49 PM PST 23 |
| Peak memory | 144908 kb |
| Host | smart-45f79a0d-b9a6-4e10-a18a-bd986df1e673 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=230032740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.230032740 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3886550484 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5307114 ps |
| CPU time | 0.47 seconds |
| Started | Dec 24 12:19:00 PM PST 23 |
| Finished | Dec 24 12:19:02 PM PST 23 |
| Peak memory | 144008 kb |
| Host | smart-48a76e53-0e9d-4417-9036-59106648a8db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886550484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3886550484 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2156365555 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5003996 ps |
| CPU time | 0.55 seconds |
| Started | Dec 24 12:19:02 PM PST 23 |
| Finished | Dec 24 12:19:04 PM PST 23 |
| Peak memory | 143812 kb |
| Host | smart-81eebf0f-c29f-483d-a9ac-0cd482804694 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156365555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2156365555 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1158329638 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4464372 ps |
| CPU time | 0.4 seconds |
| Started | Dec 24 12:19:00 PM PST 23 |
| Finished | Dec 24 12:19:02 PM PST 23 |
| Peak memory | 145900 kb |
| Host | smart-83d78779-ac33-4d41-b9ec-17862ee82dee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1158329638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1158329638 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2820651457 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4838485 ps |
| CPU time | 0.39 seconds |
| Started | Dec 24 12:18:59 PM PST 23 |
| Finished | Dec 24 12:19:01 PM PST 23 |
| Peak memory | 145900 kb |
| Host | smart-e85ca5b1-4803-4fb3-89d3-9437854571e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820651457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2820651457 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3550283682 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4599772 ps |
| CPU time | 0.46 seconds |
| Started | Dec 24 12:19:00 PM PST 23 |
| Finished | Dec 24 12:19:02 PM PST 23 |
| Peak memory | 143828 kb |
| Host | smart-9c04bb30-06c3-4f83-b408-2b5077b1f0a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550283682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3550283682 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1145777859 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5043021 ps |
| CPU time | 0.39 seconds |
| Started | Dec 24 12:18:52 PM PST 23 |
| Finished | Dec 24 12:18:53 PM PST 23 |
| Peak memory | 145636 kb |
| Host | smart-99bde8ec-7955-4039-85f0-11b8feb8e589 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145777859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1145777859 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1598788776 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4854706 ps |
| CPU time | 0.39 seconds |
| Started | Dec 24 12:18:59 PM PST 23 |
| Finished | Dec 24 12:19:00 PM PST 23 |
| Peak memory | 145724 kb |
| Host | smart-93b4a6e1-e7cf-4a4e-8a81-a466fbdbe52d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598788776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1598788776 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3877569912 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4950507 ps |
| CPU time | 0.38 seconds |
| Started | Dec 24 12:19:00 PM PST 23 |
| Finished | Dec 24 12:19:01 PM PST 23 |
| Peak memory | 145904 kb |
| Host | smart-69deb496-7d41-42f1-bc30-b2ab65181c0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877569912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3877569912 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1808929303 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4907812 ps |
| CPU time | 0.45 seconds |
| Started | Dec 24 12:19:00 PM PST 23 |
| Finished | Dec 24 12:19:02 PM PST 23 |
| Peak memory | 143472 kb |
| Host | smart-b4017d54-612e-4872-adbc-7e56062e0e3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808929303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1808929303 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.708362057 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5287355 ps |
| CPU time | 0.5 seconds |
| Started | Dec 24 12:19:02 PM PST 23 |
| Finished | Dec 24 12:19:04 PM PST 23 |
| Peak memory | 142880 kb |
| Host | smart-32ae2537-aae6-4b18-b767-5270889c1e98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=708362057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.708362057 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.118165375 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4774789 ps |
| CPU time | 0.5 seconds |
| Started | Dec 24 12:19:02 PM PST 23 |
| Finished | Dec 24 12:19:04 PM PST 23 |
| Peak memory | 143152 kb |
| Host | smart-11d35568-6078-49c8-b3d4-f8816fcd85fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118165375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.118165375 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3712933251 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4933251 ps |
| CPU time | 0.5 seconds |
| Started | Dec 24 12:19:02 PM PST 23 |
| Finished | Dec 24 12:19:04 PM PST 23 |
| Peak memory | 142632 kb |
| Host | smart-da74b739-949f-4993-9c04-e7a758518901 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3712933251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3712933251 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.4094030840 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4923327 ps |
| CPU time | 0.38 seconds |
| Started | Dec 24 12:18:59 PM PST 23 |
| Finished | Dec 24 12:19:01 PM PST 23 |
| Peak memory | 145896 kb |
| Host | smart-c472c430-932d-4531-8dd5-49f3975a118f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094030840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.4094030840 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.540762705 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4747141 ps |
| CPU time | 0.54 seconds |
| Started | Dec 24 12:19:02 PM PST 23 |
| Finished | Dec 24 12:19:04 PM PST 23 |
| Peak memory | 143520 kb |
| Host | smart-7b88492a-7a46-4f61-b076-3b93491a85cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540762705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.540762705 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3003470987 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4631875 ps |
| CPU time | 0.44 seconds |
| Started | Dec 24 12:19:00 PM PST 23 |
| Finished | Dec 24 12:19:02 PM PST 23 |
| Peak memory | 143592 kb |
| Host | smart-567a7e68-d1b2-4a68-a2e9-a36febd54f13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003470987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3003470987 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3700807283 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5290470 ps |
| CPU time | 0.44 seconds |
| Started | Dec 24 12:19:00 PM PST 23 |
| Finished | Dec 24 12:19:02 PM PST 23 |
| Peak memory | 143436 kb |
| Host | smart-e62a516f-3d84-452c-99fb-288a71e320f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700807283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3700807283 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3245674785 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5590461 ps |
| CPU time | 0.52 seconds |
| Started | Dec 24 12:19:02 PM PST 23 |
| Finished | Dec 24 12:19:04 PM PST 23 |
| Peak memory | 142728 kb |
| Host | smart-4ffd5e82-7e59-4081-b6fd-3baed5083622 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3245674785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3245674785 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |