Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.32 86.32 92.38 92.38 84.09 84.09 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/3.prim_esc_test.1653386487
88.44 2.12 93.33 0.95 86.36 2.27 100.00 0.00 85.71 7.14 83.72 2.33 81.48 0.00 /workspace/coverage/default/12.prim_esc_test.2958045675
90.17 1.74 94.29 0.95 86.36 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/9.prim_esc_test.406077948
91.31 1.14 95.24 0.95 86.36 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/13.prim_esc_test.2461031162

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.2961673725
/workspace/coverage/default/1.prim_esc_test.3258653016
/workspace/coverage/default/10.prim_esc_test.3873820591
/workspace/coverage/default/11.prim_esc_test.1460121525
/workspace/coverage/default/14.prim_esc_test.103604299
/workspace/coverage/default/15.prim_esc_test.1756462859
/workspace/coverage/default/16.prim_esc_test.1808424234
/workspace/coverage/default/17.prim_esc_test.1675162161
/workspace/coverage/default/18.prim_esc_test.1900193046
/workspace/coverage/default/19.prim_esc_test.1923991306
/workspace/coverage/default/2.prim_esc_test.1572401519
/workspace/coverage/default/4.prim_esc_test.1698652767
/workspace/coverage/default/5.prim_esc_test.1044571771
/workspace/coverage/default/6.prim_esc_test.485420925
/workspace/coverage/default/7.prim_esc_test.3256075107
/workspace/coverage/default/8.prim_esc_test.392349526



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.prim_esc_test.1653386487 Dec 27 12:35:34 PM PST 23 Dec 27 12:35:47 PM PST 23 4859723 ps
T2 /workspace/coverage/default/1.prim_esc_test.3258653016 Dec 27 12:35:39 PM PST 23 Dec 27 12:35:54 PM PST 23 4938190 ps
T3 /workspace/coverage/default/8.prim_esc_test.392349526 Dec 27 12:35:42 PM PST 23 Dec 27 12:36:00 PM PST 23 4376550 ps
T4 /workspace/coverage/default/13.prim_esc_test.2461031162 Dec 27 12:36:07 PM PST 23 Dec 27 12:36:28 PM PST 23 5414696 ps
T13 /workspace/coverage/default/7.prim_esc_test.3256075107 Dec 27 12:35:43 PM PST 23 Dec 27 12:36:01 PM PST 23 5297917 ps
T14 /workspace/coverage/default/15.prim_esc_test.1756462859 Dec 27 12:35:37 PM PST 23 Dec 27 12:35:52 PM PST 23 4752607 ps
T5 /workspace/coverage/default/2.prim_esc_test.1572401519 Dec 27 12:36:02 PM PST 23 Dec 27 12:36:21 PM PST 23 4968699 ps
T15 /workspace/coverage/default/10.prim_esc_test.3873820591 Dec 27 12:35:49 PM PST 23 Dec 27 12:36:09 PM PST 23 4685139 ps
T6 /workspace/coverage/default/19.prim_esc_test.1923991306 Dec 27 12:35:29 PM PST 23 Dec 27 12:35:42 PM PST 23 4571408 ps
T16 /workspace/coverage/default/18.prim_esc_test.1900193046 Dec 27 12:35:51 PM PST 23 Dec 27 12:36:11 PM PST 23 4586770 ps
T8 /workspace/coverage/default/12.prim_esc_test.2958045675 Dec 27 12:35:37 PM PST 23 Dec 27 12:35:51 PM PST 23 5067038 ps
T11 /workspace/coverage/default/5.prim_esc_test.1044571771 Dec 27 12:36:19 PM PST 23 Dec 27 12:36:41 PM PST 23 4759684 ps
T9 /workspace/coverage/default/14.prim_esc_test.103604299 Dec 27 12:36:00 PM PST 23 Dec 27 12:36:18 PM PST 23 4601113 ps
T18 /workspace/coverage/default/16.prim_esc_test.1808424234 Dec 27 12:36:41 PM PST 23 Dec 27 12:37:10 PM PST 23 4325380 ps
T7 /workspace/coverage/default/9.prim_esc_test.406077948 Dec 27 12:35:37 PM PST 23 Dec 27 12:35:59 PM PST 23 4662754 ps
T10 /workspace/coverage/default/0.prim_esc_test.2961673725 Dec 27 12:35:40 PM PST 23 Dec 27 12:35:56 PM PST 23 4894142 ps
T19 /workspace/coverage/default/11.prim_esc_test.1460121525 Dec 27 12:35:42 PM PST 23 Dec 27 12:36:00 PM PST 23 4917723 ps
T12 /workspace/coverage/default/4.prim_esc_test.1698652767 Dec 27 12:35:57 PM PST 23 Dec 27 12:36:16 PM PST 23 5512304 ps
T17 /workspace/coverage/default/6.prim_esc_test.485420925 Dec 27 12:35:50 PM PST 23 Dec 27 12:36:10 PM PST 23 5072706 ps
T20 /workspace/coverage/default/17.prim_esc_test.1675162161 Dec 27 12:36:05 PM PST 23 Dec 27 12:36:23 PM PST 23 5175111 ps

Test location /workspace/coverage/default/3.prim_esc_test.1653386487
Short name T1
Test name
Test status
Simulation time 4859723 ps
CPU time 0.37 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:35:47 PM PST 23
Peak memory 145836 kb
Host smart-3e78785f-20f2-4855-a2a6-8c04e53a2a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653386487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1653386487
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.2958045675
Short name T8
Test name
Test status
Simulation time 5067038 ps
CPU time 0.37 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:51 PM PST 23
Peak memory 145888 kb
Host smart-cd3e0c1d-2664-4fbf-835a-1e7e2bd2d55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958045675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2958045675
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.406077948
Short name T7
Test name
Test status
Simulation time 4662754 ps
CPU time 0.37 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:59 PM PST 23
Peak memory 145832 kb
Host smart-fdbf5965-0ff3-4b41-b577-35070b8b790c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406077948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.406077948
Directory /workspace/9.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.2461031162
Short name T4
Test name
Test status
Simulation time 5414696 ps
CPU time 0.37 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:36:28 PM PST 23
Peak memory 145776 kb
Host smart-39e5f84a-ce82-4ebe-8e17-8afab2092586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461031162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2461031162
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.2961673725
Short name T10
Test name
Test status
Simulation time 4894142 ps
CPU time 0.38 seconds
Started Dec 27 12:35:40 PM PST 23
Finished Dec 27 12:35:56 PM PST 23
Peak memory 145800 kb
Host smart-51104ada-cbba-451b-a021-f951fd6ab6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961673725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2961673725
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.3258653016
Short name T2
Test name
Test status
Simulation time 4938190 ps
CPU time 0.38 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:35:54 PM PST 23
Peak memory 145884 kb
Host smart-c918a8bd-5a76-414a-8122-38f5ce293172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258653016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3258653016
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.3873820591
Short name T15
Test name
Test status
Simulation time 4685139 ps
CPU time 0.37 seconds
Started Dec 27 12:35:49 PM PST 23
Finished Dec 27 12:36:09 PM PST 23
Peak memory 145832 kb
Host smart-a66d6f0e-e361-4316-a995-a8381a087c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873820591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3873820591
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1460121525
Short name T19
Test name
Test status
Simulation time 4917723 ps
CPU time 0.38 seconds
Started Dec 27 12:35:42 PM PST 23
Finished Dec 27 12:36:00 PM PST 23
Peak memory 145768 kb
Host smart-3dcf3f44-43a2-42b1-8926-853b3b2fe640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460121525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1460121525
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.103604299
Short name T9
Test name
Test status
Simulation time 4601113 ps
CPU time 0.36 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:18 PM PST 23
Peak memory 145828 kb
Host smart-c93d8c4e-3dcb-42ca-960a-54b99c3a47bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103604299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.103604299
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.1756462859
Short name T14
Test name
Test status
Simulation time 4752607 ps
CPU time 0.36 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:52 PM PST 23
Peak memory 145792 kb
Host smart-971433b7-2f7f-4548-9680-69db092d1f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756462859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1756462859
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1808424234
Short name T18
Test name
Test status
Simulation time 4325380 ps
CPU time 0.37 seconds
Started Dec 27 12:36:41 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 145732 kb
Host smart-c7ecc337-024a-4f0d-b7d5-4d65153213cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808424234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1808424234
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1675162161
Short name T20
Test name
Test status
Simulation time 5175111 ps
CPU time 0.37 seconds
Started Dec 27 12:36:05 PM PST 23
Finished Dec 27 12:36:23 PM PST 23
Peak memory 145820 kb
Host smart-5ca04aa8-bd24-46f2-819c-76b01cbd03bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675162161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1675162161
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.1900193046
Short name T16
Test name
Test status
Simulation time 4586770 ps
CPU time 0.44 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:36:11 PM PST 23
Peak memory 145844 kb
Host smart-999c966f-739c-4513-ad9f-34a432296be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900193046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1900193046
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.1923991306
Short name T6
Test name
Test status
Simulation time 4571408 ps
CPU time 0.38 seconds
Started Dec 27 12:35:29 PM PST 23
Finished Dec 27 12:35:42 PM PST 23
Peak memory 145816 kb
Host smart-8ddb2b04-97ce-4457-a29f-d525ae3e9f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923991306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1923991306
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.1572401519
Short name T5
Test name
Test status
Simulation time 4968699 ps
CPU time 0.39 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 145768 kb
Host smart-69e4568a-d77e-4490-994c-36bb2daa3a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572401519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1572401519
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.1698652767
Short name T12
Test name
Test status
Simulation time 5512304 ps
CPU time 0.37 seconds
Started Dec 27 12:35:57 PM PST 23
Finished Dec 27 12:36:16 PM PST 23
Peak memory 145836 kb
Host smart-2714b3cc-04f5-4541-acf1-517120e1fad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698652767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1698652767
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.1044571771
Short name T11
Test name
Test status
Simulation time 4759684 ps
CPU time 0.39 seconds
Started Dec 27 12:36:19 PM PST 23
Finished Dec 27 12:36:41 PM PST 23
Peak memory 145816 kb
Host smart-24d8f43d-1434-45b9-8977-7c05bfeb88fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044571771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1044571771
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.485420925
Short name T17
Test name
Test status
Simulation time 5072706 ps
CPU time 0.37 seconds
Started Dec 27 12:35:50 PM PST 23
Finished Dec 27 12:36:10 PM PST 23
Peak memory 145868 kb
Host smart-341ac8fd-39ca-4731-a2fc-d8bc88dfd292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485420925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.485420925
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.3256075107
Short name T13
Test name
Test status
Simulation time 5297917 ps
CPU time 0.4 seconds
Started Dec 27 12:35:43 PM PST 23
Finished Dec 27 12:36:01 PM PST 23
Peak memory 145716 kb
Host smart-bfd50717-d0ff-42d3-b834-df900f3ba6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256075107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3256075107
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.392349526
Short name T3
Test name
Test status
Simulation time 4376550 ps
CPU time 0.37 seconds
Started Dec 27 12:35:42 PM PST 23
Finished Dec 27 12:36:00 PM PST 23
Peak memory 145832 kb
Host smart-639ec362-93a7-4d19-ae37-6c28648bcfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392349526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.392349526
Directory /workspace/8.prim_esc_test/latest
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