| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.72 | 85.72 | 92.38 | 92.38 | 84.09 | 84.09 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/15.prim_esc_test.3508735649 |
| 87.84 | 2.12 | 93.33 | 0.95 | 86.36 | 2.27 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.1442133595 |
| 89.58 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/18.prim_esc_test.747763254 |
| 90.72 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/3.prim_esc_test.1422231729 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.3978253165 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.3450228602 |
| /workspace/coverage/default/10.prim_esc_test.4175469570 |
| /workspace/coverage/default/11.prim_esc_test.773162711 |
| /workspace/coverage/default/13.prim_esc_test.1742458167 |
| /workspace/coverage/default/14.prim_esc_test.1131715522 |
| /workspace/coverage/default/16.prim_esc_test.998586290 |
| /workspace/coverage/default/17.prim_esc_test.2656024555 |
| /workspace/coverage/default/19.prim_esc_test.1038055246 |
| /workspace/coverage/default/2.prim_esc_test.534984357 |
| /workspace/coverage/default/4.prim_esc_test.1889693969 |
| /workspace/coverage/default/5.prim_esc_test.3653279570 |
| /workspace/coverage/default/6.prim_esc_test.2015899074 |
| /workspace/coverage/default/7.prim_esc_test.4284421029 |
| /workspace/coverage/default/8.prim_esc_test.3474712191 |
| /workspace/coverage/default/9.prim_esc_test.481167 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.prim_esc_test.2015899074 | Dec 31 12:17:19 PM PST 23 | Dec 31 12:17:21 PM PST 23 | 4552014 ps | ||
| T2 | /workspace/coverage/default/5.prim_esc_test.3653279570 | Dec 31 12:17:46 PM PST 23 | Dec 31 12:17:48 PM PST 23 | 4319707 ps | ||
| T3 | /workspace/coverage/default/10.prim_esc_test.4175469570 | Dec 31 12:17:13 PM PST 23 | Dec 31 12:17:15 PM PST 23 | 4182449 ps | ||
| T6 | /workspace/coverage/default/18.prim_esc_test.747763254 | Dec 31 12:17:11 PM PST 23 | Dec 31 12:17:12 PM PST 23 | 4415956 ps | ||
| T7 | /workspace/coverage/default/13.prim_esc_test.1742458167 | Dec 31 12:24:28 PM PST 23 | Dec 31 12:24:30 PM PST 23 | 4818689 ps | ||
| T11 | /workspace/coverage/default/12.prim_esc_test.3978253165 | Dec 31 12:17:11 PM PST 23 | Dec 31 12:17:12 PM PST 23 | 5164042 ps | ||
| T9 | /workspace/coverage/default/15.prim_esc_test.3508735649 | Dec 31 12:17:07 PM PST 23 | Dec 31 12:17:11 PM PST 23 | 4837342 ps | ||
| T4 | /workspace/coverage/default/19.prim_esc_test.1038055246 | Dec 31 12:17:19 PM PST 23 | Dec 31 12:17:21 PM PST 23 | 4680733 ps | ||
| T5 | /workspace/coverage/default/7.prim_esc_test.4284421029 | Dec 31 12:17:13 PM PST 23 | Dec 31 12:17:15 PM PST 23 | 4682053 ps | ||
| T12 | /workspace/coverage/default/11.prim_esc_test.773162711 | Dec 31 12:18:27 PM PST 23 | Dec 31 12:18:28 PM PST 23 | 4516159 ps | ||
| T13 | /workspace/coverage/default/3.prim_esc_test.1422231729 | Dec 31 12:17:19 PM PST 23 | Dec 31 12:17:21 PM PST 23 | 4595445 ps | ||
| T14 | /workspace/coverage/default/4.prim_esc_test.1889693969 | Dec 31 12:17:43 PM PST 23 | Dec 31 12:17:46 PM PST 23 | 4594798 ps | ||
| T8 | /workspace/coverage/default/2.prim_esc_test.534984357 | Dec 31 12:17:07 PM PST 23 | Dec 31 12:17:11 PM PST 23 | 4402065 ps | ||
| T15 | /workspace/coverage/default/17.prim_esc_test.2656024555 | Dec 31 12:17:07 PM PST 23 | Dec 31 12:17:11 PM PST 23 | 5039227 ps | ||
| T16 | /workspace/coverage/default/8.prim_esc_test.3474712191 | Dec 31 12:17:35 PM PST 23 | Dec 31 12:17:36 PM PST 23 | 5062034 ps | ||
| T17 | /workspace/coverage/default/16.prim_esc_test.998586290 | Dec 31 12:17:19 PM PST 23 | Dec 31 12:17:21 PM PST 23 | 4579350 ps | ||
| T18 | /workspace/coverage/default/0.prim_esc_test.1442133595 | Dec 31 12:17:11 PM PST 23 | Dec 31 12:17:12 PM PST 23 | 4885208 ps | ||
| T10 | /workspace/coverage/default/9.prim_esc_test.481167 | Dec 31 12:17:28 PM PST 23 | Dec 31 12:17:29 PM PST 23 | 4551058 ps | ||
| T19 | /workspace/coverage/default/1.prim_esc_test.3450228602 | Dec 31 12:17:07 PM PST 23 | Dec 31 12:17:11 PM PST 23 | 4927920 ps | ||
| T20 | /workspace/coverage/default/14.prim_esc_test.1131715522 | Dec 31 12:17:11 PM PST 23 | Dec 31 12:17:12 PM PST 23 | 5176156 ps |
| Test location | /workspace/coverage/default/15.prim_esc_test.3508735649 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4837342 ps |
| CPU time | 0.38 seconds |
| Started | Dec 31 12:17:07 PM PST 23 |
| Finished | Dec 31 12:17:11 PM PST 23 |
| Peak memory | 145380 kb |
| Host | smart-b58a2b1a-da63-4d0b-8b2a-ef8c1eac4171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508735649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3508735649 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1442133595 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4885208 ps |
| CPU time | 0.4 seconds |
| Started | Dec 31 12:17:11 PM PST 23 |
| Finished | Dec 31 12:17:12 PM PST 23 |
| Peak memory | 146044 kb |
| Host | smart-528af0af-2ed8-4cf1-b6b5-6867fb60b2a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442133595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1442133595 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.747763254 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4415956 ps |
| CPU time | 0.39 seconds |
| Started | Dec 31 12:17:11 PM PST 23 |
| Finished | Dec 31 12:17:12 PM PST 23 |
| Peak memory | 146052 kb |
| Host | smart-dd2bf5cd-8cf5-47b9-80de-a7488897b8aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=747763254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.747763254 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1422231729 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4595445 ps |
| CPU time | 0.43 seconds |
| Started | Dec 31 12:17:19 PM PST 23 |
| Finished | Dec 31 12:17:21 PM PST 23 |
| Peak memory | 143628 kb |
| Host | smart-840cd433-aac2-49f3-bbcb-f0a82f2c723d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422231729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1422231729 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3978253165 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5164042 ps |
| CPU time | 0.37 seconds |
| Started | Dec 31 12:17:11 PM PST 23 |
| Finished | Dec 31 12:17:12 PM PST 23 |
| Peak memory | 146044 kb |
| Host | smart-4f035a54-4de5-46ae-9778-12694dfe94fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978253165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3978253165 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3450228602 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4927920 ps |
| CPU time | 0.39 seconds |
| Started | Dec 31 12:17:07 PM PST 23 |
| Finished | Dec 31 12:17:11 PM PST 23 |
| Peak memory | 145488 kb |
| Host | smart-1c8ebb33-1e3b-42a8-9d1d-bfbdc7519d2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450228602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3450228602 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.4175469570 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4182449 ps |
| CPU time | 0.38 seconds |
| Started | Dec 31 12:17:13 PM PST 23 |
| Finished | Dec 31 12:17:15 PM PST 23 |
| Peak memory | 146052 kb |
| Host | smart-cf25d117-b3c6-41fc-ac68-b7c8b20890a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175469570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.4175469570 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.773162711 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4516159 ps |
| CPU time | 0.39 seconds |
| Started | Dec 31 12:18:27 PM PST 23 |
| Finished | Dec 31 12:18:28 PM PST 23 |
| Peak memory | 146052 kb |
| Host | smart-ca9c760c-8f44-490c-b075-f29f2792ef26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=773162711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.773162711 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1742458167 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4818689 ps |
| CPU time | 0.38 seconds |
| Started | Dec 31 12:24:28 PM PST 23 |
| Finished | Dec 31 12:24:30 PM PST 23 |
| Peak memory | 145732 kb |
| Host | smart-b0ef9792-7d71-4337-90b2-385812c742f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742458167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1742458167 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1131715522 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5176156 ps |
| CPU time | 0.38 seconds |
| Started | Dec 31 12:17:11 PM PST 23 |
| Finished | Dec 31 12:17:12 PM PST 23 |
| Peak memory | 146048 kb |
| Host | smart-b14a6e3b-3427-45ff-b85a-8550ce23e214 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131715522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1131715522 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.998586290 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4579350 ps |
| CPU time | 0.47 seconds |
| Started | Dec 31 12:17:19 PM PST 23 |
| Finished | Dec 31 12:17:21 PM PST 23 |
| Peak memory | 144192 kb |
| Host | smart-978b4acc-919e-48e1-b35e-5a380b265504 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998586290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.998586290 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2656024555 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5039227 ps |
| CPU time | 0.38 seconds |
| Started | Dec 31 12:17:07 PM PST 23 |
| Finished | Dec 31 12:17:11 PM PST 23 |
| Peak memory | 145828 kb |
| Host | smart-2c9646b7-7e6a-4621-a855-689d45b3af47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656024555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2656024555 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1038055246 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4680733 ps |
| CPU time | 0.45 seconds |
| Started | Dec 31 12:17:19 PM PST 23 |
| Finished | Dec 31 12:17:21 PM PST 23 |
| Peak memory | 143612 kb |
| Host | smart-7dc15448-f6c3-4817-af00-ead2638c9f4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1038055246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1038055246 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.534984357 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4402065 ps |
| CPU time | 0.39 seconds |
| Started | Dec 31 12:17:07 PM PST 23 |
| Finished | Dec 31 12:17:11 PM PST 23 |
| Peak memory | 145860 kb |
| Host | smart-dd93dbbe-f729-48a6-ba4a-4dde444c74ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534984357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.534984357 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1889693969 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4594798 ps |
| CPU time | 0.45 seconds |
| Started | Dec 31 12:17:43 PM PST 23 |
| Finished | Dec 31 12:17:46 PM PST 23 |
| Peak memory | 145244 kb |
| Host | smart-0be97736-7ab2-4bef-9146-b9938327573e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889693969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1889693969 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3653279570 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4319707 ps |
| CPU time | 0.51 seconds |
| Started | Dec 31 12:17:46 PM PST 23 |
| Finished | Dec 31 12:17:48 PM PST 23 |
| Peak memory | 144408 kb |
| Host | smart-dffb23d9-450f-40a5-8348-9648ee190653 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653279570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3653279570 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2015899074 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4552014 ps |
| CPU time | 0.47 seconds |
| Started | Dec 31 12:17:19 PM PST 23 |
| Finished | Dec 31 12:17:21 PM PST 23 |
| Peak memory | 144384 kb |
| Host | smart-8e6fe7a3-779d-4b3a-ba55-b2fc943a4f3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015899074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2015899074 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4284421029 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4682053 ps |
| CPU time | 0.38 seconds |
| Started | Dec 31 12:17:13 PM PST 23 |
| Finished | Dec 31 12:17:15 PM PST 23 |
| Peak memory | 146052 kb |
| Host | smart-a8b15e95-c19c-43ec-a6cc-98a9b26db4d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284421029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4284421029 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3474712191 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5062034 ps |
| CPU time | 0.38 seconds |
| Started | Dec 31 12:17:35 PM PST 23 |
| Finished | Dec 31 12:17:36 PM PST 23 |
| Peak memory | 146052 kb |
| Host | smart-f11b788f-069d-4112-97be-9e8e0124edc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474712191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3474712191 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.481167 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4551058 ps |
| CPU time | 0.39 seconds |
| Started | Dec 31 12:17:28 PM PST 23 |
| Finished | Dec 31 12:17:29 PM PST 23 |
| Peak memory | 146052 kb |
| Host | smart-44995fe4-994f-4aec-bf32-effe0e562385 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.481167 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |