| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 90.17 | 94.29 | 86.36 | 100.00 | 92.86 | 86.05 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.70 | 86.70 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/19.prim_esc_test.1560997810 |
| 88.44 | 1.74 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1216932426 |
| 90.17 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/4.prim_esc_test.541971376 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2789123021 |
| /workspace/coverage/default/1.prim_esc_test.3404090975 |
| /workspace/coverage/default/11.prim_esc_test.3273344999 |
| /workspace/coverage/default/12.prim_esc_test.4215885978 |
| /workspace/coverage/default/13.prim_esc_test.2373179657 |
| /workspace/coverage/default/14.prim_esc_test.215528411 |
| /workspace/coverage/default/15.prim_esc_test.3353470176 |
| /workspace/coverage/default/16.prim_esc_test.1534592914 |
| /workspace/coverage/default/17.prim_esc_test.2573926225 |
| /workspace/coverage/default/18.prim_esc_test.628744076 |
| /workspace/coverage/default/2.prim_esc_test.1066297783 |
| /workspace/coverage/default/3.prim_esc_test.384180700 |
| /workspace/coverage/default/5.prim_esc_test.1809016734 |
| /workspace/coverage/default/6.prim_esc_test.3484279932 |
| /workspace/coverage/default/7.prim_esc_test.3029006104 |
| /workspace/coverage/default/8.prim_esc_test.3550417357 |
| /workspace/coverage/default/9.prim_esc_test.3118183254 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_esc_test.4215885978 | Jan 03 12:41:32 PM PST 24 | Jan 03 12:42:59 PM PST 24 | 4798989 ps | ||
| T2 | /workspace/coverage/default/6.prim_esc_test.3484279932 | Jan 03 12:41:51 PM PST 24 | Jan 03 12:43:15 PM PST 24 | 4819826 ps | ||
| T3 | /workspace/coverage/default/10.prim_esc_test.1216932426 | Jan 03 12:41:54 PM PST 24 | Jan 03 12:43:18 PM PST 24 | 4928593 ps | ||
| T4 | /workspace/coverage/default/19.prim_esc_test.1560997810 | Jan 03 12:41:36 PM PST 24 | Jan 03 12:43:09 PM PST 24 | 4960796 ps | ||
| T5 | /workspace/coverage/default/0.prim_esc_test.2789123021 | Jan 03 12:41:39 PM PST 24 | Jan 03 12:43:05 PM PST 24 | 4819639 ps | ||
| T6 | /workspace/coverage/default/13.prim_esc_test.2373179657 | Jan 03 12:41:34 PM PST 24 | Jan 03 12:43:01 PM PST 24 | 5276460 ps | ||
| T7 | /workspace/coverage/default/5.prim_esc_test.1809016734 | Jan 03 12:41:47 PM PST 24 | Jan 03 12:43:12 PM PST 24 | 4574397 ps | ||
| T9 | /workspace/coverage/default/9.prim_esc_test.3118183254 | Jan 03 12:41:54 PM PST 24 | Jan 03 12:43:17 PM PST 24 | 4765792 ps | ||
| T13 | /workspace/coverage/default/17.prim_esc_test.2573926225 | Jan 03 12:41:30 PM PST 24 | Jan 03 12:43:00 PM PST 24 | 4456684 ps | ||
| T8 | /workspace/coverage/default/2.prim_esc_test.1066297783 | Jan 03 12:41:55 PM PST 24 | Jan 03 12:43:17 PM PST 24 | 4630856 ps | ||
| T14 | /workspace/coverage/default/11.prim_esc_test.3273344999 | Jan 03 12:41:29 PM PST 24 | Jan 03 12:42:56 PM PST 24 | 4915463 ps | ||
| T15 | /workspace/coverage/default/18.prim_esc_test.628744076 | Jan 03 12:41:27 PM PST 24 | Jan 03 12:42:55 PM PST 24 | 5247447 ps | ||
| T16 | /workspace/coverage/default/16.prim_esc_test.1534592914 | Jan 03 12:41:30 PM PST 24 | Jan 03 12:42:58 PM PST 24 | 4874139 ps | ||
| T17 | /workspace/coverage/default/15.prim_esc_test.3353470176 | Jan 03 12:41:28 PM PST 24 | Jan 03 12:42:56 PM PST 24 | 4949035 ps | ||
| T10 | /workspace/coverage/default/4.prim_esc_test.541971376 | Jan 03 12:41:44 PM PST 24 | Jan 03 12:43:09 PM PST 24 | 5433763 ps | ||
| T11 | /workspace/coverage/default/7.prim_esc_test.3029006104 | Jan 03 12:41:54 PM PST 24 | Jan 03 12:43:18 PM PST 24 | 5393621 ps | ||
| T12 | /workspace/coverage/default/14.prim_esc_test.215528411 | Jan 03 12:41:31 PM PST 24 | Jan 03 12:42:59 PM PST 24 | 4909318 ps | ||
| T18 | /workspace/coverage/default/1.prim_esc_test.3404090975 | Jan 03 12:41:38 PM PST 24 | Jan 03 12:43:04 PM PST 24 | 4251990 ps | ||
| T19 | /workspace/coverage/default/3.prim_esc_test.384180700 | Jan 03 12:42:04 PM PST 24 | Jan 03 12:43:28 PM PST 24 | 4647165 ps | ||
| T20 | /workspace/coverage/default/8.prim_esc_test.3550417357 | Jan 03 12:41:45 PM PST 24 | Jan 03 12:43:12 PM PST 24 | 5011012 ps |
| Test location | /workspace/coverage/default/19.prim_esc_test.1560997810 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4960796 ps |
| CPU time | 0.42 seconds |
| Started | Jan 03 12:41:36 PM PST 24 |
| Finished | Jan 03 12:43:09 PM PST 24 |
| Peak memory | 145912 kb |
| Host | smart-3c7fcdd3-e626-41e2-9dde-99f0cc291e6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560997810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1560997810 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1216932426 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4928593 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:41:54 PM PST 24 |
| Finished | Jan 03 12:43:18 PM PST 24 |
| Peak memory | 145828 kb |
| Host | smart-3ff0a099-d90f-4815-bbc5-5946fef30859 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216932426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1216932426 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.541971376 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5433763 ps |
| CPU time | 0.36 seconds |
| Started | Jan 03 12:41:44 PM PST 24 |
| Finished | Jan 03 12:43:09 PM PST 24 |
| Peak memory | 145800 kb |
| Host | smart-8af80491-190d-450f-a09f-679042684100 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541971376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.541971376 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2789123021 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4819639 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:39 PM PST 24 |
| Finished | Jan 03 12:43:05 PM PST 24 |
| Peak memory | 145908 kb |
| Host | smart-e2538377-b962-47f6-9db1-e7f8531d313f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789123021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2789123021 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3404090975 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4251990 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:38 PM PST 24 |
| Finished | Jan 03 12:43:04 PM PST 24 |
| Peak memory | 145764 kb |
| Host | smart-f8b0d9f3-87b8-4b2a-9ccf-0f68d0519f94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404090975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3404090975 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3273344999 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4915463 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:29 PM PST 24 |
| Finished | Jan 03 12:42:56 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-e61ab31b-90bb-429d-96b1-e9488f577575 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273344999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3273344999 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.4215885978 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4798989 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:32 PM PST 24 |
| Finished | Jan 03 12:42:59 PM PST 24 |
| Peak memory | 145844 kb |
| Host | smart-f7380eda-711c-4236-af82-4389aa26a250 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215885978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.4215885978 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2373179657 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5276460 ps |
| CPU time | 0.36 seconds |
| Started | Jan 03 12:41:34 PM PST 24 |
| Finished | Jan 03 12:43:01 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-e6c24d49-60ea-47ef-93c8-a157c6afbca3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373179657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2373179657 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.215528411 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4909318 ps |
| CPU time | 0.36 seconds |
| Started | Jan 03 12:41:31 PM PST 24 |
| Finished | Jan 03 12:42:59 PM PST 24 |
| Peak memory | 145776 kb |
| Host | smart-3dfeb159-643c-4fa8-a955-0b86ede15821 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215528411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.215528411 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3353470176 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4949035 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:28 PM PST 24 |
| Finished | Jan 03 12:42:56 PM PST 24 |
| Peak memory | 145820 kb |
| Host | smart-fc863fc4-0f09-4d42-ad6f-d17988cac290 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3353470176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3353470176 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1534592914 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4874139 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:30 PM PST 24 |
| Finished | Jan 03 12:42:58 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-596eb130-4a4f-4547-af66-f9d8cc41c5f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534592914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1534592914 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2573926225 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4456684 ps |
| CPU time | 0.36 seconds |
| Started | Jan 03 12:41:30 PM PST 24 |
| Finished | Jan 03 12:43:00 PM PST 24 |
| Peak memory | 145848 kb |
| Host | smart-fb4f17e6-ac77-4aaf-8237-0ff81503fa47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573926225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2573926225 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.628744076 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5247447 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:27 PM PST 24 |
| Finished | Jan 03 12:42:55 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-030d8880-4c08-4807-902b-27476ec875fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628744076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.628744076 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1066297783 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4630856 ps |
| CPU time | 0.36 seconds |
| Started | Jan 03 12:41:55 PM PST 24 |
| Finished | Jan 03 12:43:17 PM PST 24 |
| Peak memory | 145764 kb |
| Host | smart-99efb960-59ff-4028-a3a9-ceb59a19736c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066297783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1066297783 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.384180700 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4647165 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:42:04 PM PST 24 |
| Finished | Jan 03 12:43:28 PM PST 24 |
| Peak memory | 145828 kb |
| Host | smart-6500da8c-f3d1-422a-902c-cd76b8a8f0b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384180700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.384180700 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1809016734 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4574397 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:41:47 PM PST 24 |
| Finished | Jan 03 12:43:12 PM PST 24 |
| Peak memory | 145764 kb |
| Host | smart-e244c761-4aba-40de-8dab-4ae966f822ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809016734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1809016734 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3484279932 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4819826 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:51 PM PST 24 |
| Finished | Jan 03 12:43:15 PM PST 24 |
| Peak memory | 145844 kb |
| Host | smart-503c244c-f6af-4c4e-967a-36c916d0c934 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3484279932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3484279932 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3029006104 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5393621 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:54 PM PST 24 |
| Finished | Jan 03 12:43:18 PM PST 24 |
| Peak memory | 145900 kb |
| Host | smart-61b1d5e7-f5cf-4786-a283-ea92e948f402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3029006104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3029006104 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3550417357 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5011012 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:45 PM PST 24 |
| Finished | Jan 03 12:43:12 PM PST 24 |
| Peak memory | 145784 kb |
| Host | smart-7e4b38eb-9cee-45dc-ae76-31f2fd7e78f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550417357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3550417357 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3118183254 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4765792 ps |
| CPU time | 0.36 seconds |
| Started | Jan 03 12:41:54 PM PST 24 |
| Finished | Jan 03 12:43:17 PM PST 24 |
| Peak memory | 145892 kb |
| Host | smart-4faa015d-2d9a-4634-bd42-17a8749ed255 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3118183254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3118183254 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |