| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.40 | 85.40 | 90.48 | 90.48 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/16.prim_esc_test.956150436 |
| 88.44 | 3.04 | 93.33 | 2.86 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/9.prim_esc_test.4038537725 |
| 90.17 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/18.prim_esc_test.64816496 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.3631903392 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.340783216 |
| /workspace/coverage/default/10.prim_esc_test.680921014 |
| /workspace/coverage/default/12.prim_esc_test.2794264538 |
| /workspace/coverage/default/13.prim_esc_test.3497412300 |
| /workspace/coverage/default/14.prim_esc_test.1769792813 |
| /workspace/coverage/default/15.prim_esc_test.157575308 |
| /workspace/coverage/default/17.prim_esc_test.1151337230 |
| /workspace/coverage/default/19.prim_esc_test.897271909 |
| /workspace/coverage/default/2.prim_esc_test.3195272965 |
| /workspace/coverage/default/3.prim_esc_test.505337253 |
| /workspace/coverage/default/4.prim_esc_test.429870652 |
| /workspace/coverage/default/5.prim_esc_test.4291974716 |
| /workspace/coverage/default/6.prim_esc_test.364280491 |
| /workspace/coverage/default/7.prim_esc_test.3263025718 |
| /workspace/coverage/default/8.prim_esc_test.564236064 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_esc_test.64816496 | Jan 07 12:38:17 PM PST 24 | Jan 07 12:39:20 PM PST 24 | 4774593 ps | ||
| T2 | /workspace/coverage/default/8.prim_esc_test.564236064 | Jan 07 12:37:51 PM PST 24 | Jan 07 12:38:52 PM PST 24 | 4104562 ps | ||
| T3 | /workspace/coverage/default/9.prim_esc_test.4038537725 | Jan 07 12:38:00 PM PST 24 | Jan 07 12:39:04 PM PST 24 | 4898396 ps | ||
| T6 | /workspace/coverage/default/4.prim_esc_test.429870652 | Jan 07 12:37:50 PM PST 24 | Jan 07 12:39:01 PM PST 24 | 4539590 ps | ||
| T5 | /workspace/coverage/default/7.prim_esc_test.3263025718 | Jan 07 12:38:03 PM PST 24 | Jan 07 12:39:09 PM PST 24 | 4784817 ps | ||
| T15 | /workspace/coverage/default/14.prim_esc_test.1769792813 | Jan 07 12:37:46 PM PST 24 | Jan 07 12:39:07 PM PST 24 | 4517726 ps | ||
| T4 | /workspace/coverage/default/2.prim_esc_test.3195272965 | Jan 07 12:37:49 PM PST 24 | Jan 07 12:39:16 PM PST 24 | 4680061 ps | ||
| T13 | /workspace/coverage/default/5.prim_esc_test.4291974716 | Jan 07 12:38:26 PM PST 24 | Jan 07 12:39:37 PM PST 24 | 4485199 ps | ||
| T10 | /workspace/coverage/default/16.prim_esc_test.956150436 | Jan 07 12:38:31 PM PST 24 | Jan 07 12:39:53 PM PST 24 | 4723214 ps | ||
| T7 | /workspace/coverage/default/10.prim_esc_test.680921014 | Jan 07 12:38:34 PM PST 24 | Jan 07 12:40:23 PM PST 24 | 4719365 ps | ||
| T8 | /workspace/coverage/default/17.prim_esc_test.1151337230 | Jan 07 12:37:59 PM PST 24 | Jan 07 12:39:18 PM PST 24 | 4523822 ps | ||
| T16 | /workspace/coverage/default/12.prim_esc_test.2794264538 | Jan 07 12:37:52 PM PST 24 | Jan 07 12:38:54 PM PST 24 | 5109366 ps | ||
| T9 | /workspace/coverage/default/13.prim_esc_test.3497412300 | Jan 07 12:38:27 PM PST 24 | Jan 07 12:39:43 PM PST 24 | 4919398 ps | ||
| T11 | /workspace/coverage/default/19.prim_esc_test.897271909 | Jan 07 12:38:02 PM PST 24 | Jan 07 12:39:20 PM PST 24 | 4855268 ps | ||
| T12 | /workspace/coverage/default/15.prim_esc_test.157575308 | Jan 07 12:38:11 PM PST 24 | Jan 07 12:39:12 PM PST 24 | 4584010 ps | ||
| T14 | /workspace/coverage/default/11.prim_esc_test.3631903392 | Jan 07 12:38:35 PM PST 24 | Jan 07 12:39:37 PM PST 24 | 4811018 ps | ||
| T17 | /workspace/coverage/default/3.prim_esc_test.505337253 | Jan 07 12:37:54 PM PST 24 | Jan 07 12:39:10 PM PST 24 | 4733115 ps | ||
| T18 | /workspace/coverage/default/1.prim_esc_test.340783216 | Jan 07 12:38:32 PM PST 24 | Jan 07 12:39:32 PM PST 24 | 5172675 ps | ||
| T19 | /workspace/coverage/default/6.prim_esc_test.364280491 | Jan 07 12:37:51 PM PST 24 | Jan 07 12:39:10 PM PST 24 | 5036197 ps |
| Test location | /workspace/coverage/default/16.prim_esc_test.956150436 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4723214 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:38:31 PM PST 24 |
| Finished | Jan 07 12:39:53 PM PST 24 |
| Peak memory | 145808 kb |
| Host | smart-62fc572e-57e7-47f0-a22f-5fb53738b36e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956150436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.956150436 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.4038537725 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4898396 ps |
| CPU time | 0.36 seconds |
| Started | Jan 07 12:38:00 PM PST 24 |
| Finished | Jan 07 12:39:04 PM PST 24 |
| Peak memory | 145788 kb |
| Host | smart-643a94df-ae05-4552-8f45-4667aa391d37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038537725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.4038537725 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.64816496 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4774593 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:38:17 PM PST 24 |
| Finished | Jan 07 12:39:20 PM PST 24 |
| Peak memory | 145788 kb |
| Host | smart-0be185e1-51c9-4173-af6d-8c9d6f9b0156 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64816496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.64816496 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3631903392 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4811018 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:38:35 PM PST 24 |
| Finished | Jan 07 12:39:37 PM PST 24 |
| Peak memory | 145784 kb |
| Host | smart-b7995cab-14cd-4b49-9d18-b1c9d66cd96f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3631903392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3631903392 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.340783216 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5172675 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:38:32 PM PST 24 |
| Finished | Jan 07 12:39:32 PM PST 24 |
| Peak memory | 145864 kb |
| Host | smart-dab4eb70-2e36-4ba1-9606-48e7e8e91980 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340783216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.340783216 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.680921014 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4719365 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:38:34 PM PST 24 |
| Finished | Jan 07 12:40:23 PM PST 24 |
| Peak memory | 145752 kb |
| Host | smart-e1955f81-de9f-49ac-b3c2-2732674564b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680921014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.680921014 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2794264538 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5109366 ps |
| CPU time | 0.39 seconds |
| Started | Jan 07 12:37:52 PM PST 24 |
| Finished | Jan 07 12:38:54 PM PST 24 |
| Peak memory | 145792 kb |
| Host | smart-ce92ad90-91da-4dfa-9fb7-43e65ab48c0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794264538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2794264538 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3497412300 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4919398 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:38:27 PM PST 24 |
| Finished | Jan 07 12:39:43 PM PST 24 |
| Peak memory | 145796 kb |
| Host | smart-175c70e7-a86e-4543-8932-32b45d95d272 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497412300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3497412300 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1769792813 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4517726 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:37:46 PM PST 24 |
| Finished | Jan 07 12:39:07 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-c631d7aa-3641-469d-be87-5f551d724a02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769792813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1769792813 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.157575308 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4584010 ps |
| CPU time | 0.36 seconds |
| Started | Jan 07 12:38:11 PM PST 24 |
| Finished | Jan 07 12:39:12 PM PST 24 |
| Peak memory | 145808 kb |
| Host | smart-60d6a9b9-3431-4901-bf0e-c05b4fd788fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157575308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.157575308 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1151337230 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4523822 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:37:59 PM PST 24 |
| Finished | Jan 07 12:39:18 PM PST 24 |
| Peak memory | 145732 kb |
| Host | smart-fd69507c-06a5-4e80-8a1c-e6c9b729aff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151337230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1151337230 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.897271909 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4855268 ps |
| CPU time | 0.38 seconds |
| Started | Jan 07 12:38:02 PM PST 24 |
| Finished | Jan 07 12:39:20 PM PST 24 |
| Peak memory | 145824 kb |
| Host | smart-266527b0-9d23-49b4-91a7-32a5a6054f1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897271909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.897271909 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3195272965 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4680061 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:37:49 PM PST 24 |
| Finished | Jan 07 12:39:16 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-86ed9078-94bf-4a68-b156-6a4d670e7713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195272965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3195272965 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.505337253 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4733115 ps |
| CPU time | 0.36 seconds |
| Started | Jan 07 12:37:54 PM PST 24 |
| Finished | Jan 07 12:39:10 PM PST 24 |
| Peak memory | 145808 kb |
| Host | smart-8e7eb544-3018-4c1f-afb3-d055764626a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505337253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.505337253 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.429870652 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4539590 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:37:50 PM PST 24 |
| Finished | Jan 07 12:39:01 PM PST 24 |
| Peak memory | 145808 kb |
| Host | smart-792faa95-cb11-4c82-b2cf-b55531768d03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429870652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.429870652 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.4291974716 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4485199 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:38:26 PM PST 24 |
| Finished | Jan 07 12:39:37 PM PST 24 |
| Peak memory | 145800 kb |
| Host | smart-a3344260-124b-4dfe-a18f-74145ae2804d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291974716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.4291974716 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.364280491 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5036197 ps |
| CPU time | 0.36 seconds |
| Started | Jan 07 12:37:51 PM PST 24 |
| Finished | Jan 07 12:39:10 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-68d36fad-0f06-428b-bfc0-34a7b42f744f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=364280491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.364280491 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3263025718 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4784817 ps |
| CPU time | 0.37 seconds |
| Started | Jan 07 12:38:03 PM PST 24 |
| Finished | Jan 07 12:39:09 PM PST 24 |
| Peak memory | 145800 kb |
| Host | smart-6afcdfdc-a55f-4017-b259-6ada3dcf2a56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263025718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3263025718 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.564236064 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4104562 ps |
| CPU time | 0.36 seconds |
| Started | Jan 07 12:37:51 PM PST 24 |
| Finished | Jan 07 12:38:52 PM PST 24 |
| Peak memory | 145732 kb |
| Host | smart-d14527ec-a572-4384-a116-1d20e935b160 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=564236064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.564236064 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |