| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 90.17 | 94.29 | 86.36 | 100.00 | 92.86 | 86.05 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.56 | 85.56 | 92.38 | 92.38 | 79.55 | 79.55 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/10.prim_esc_test.4209108780 |
| 88.44 | 2.87 | 93.33 | 0.95 | 86.36 | 6.82 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.3496382964 |
| 89.58 | 1.14 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.321217924 |
| 90.17 | 0.60 | 94.29 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.05 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.4071545055 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.4121638802 |
| /workspace/coverage/default/11.prim_esc_test.683304531 |
| /workspace/coverage/default/12.prim_esc_test.660894506 |
| /workspace/coverage/default/13.prim_esc_test.2979646003 |
| /workspace/coverage/default/14.prim_esc_test.1238654623 |
| /workspace/coverage/default/15.prim_esc_test.3263730777 |
| /workspace/coverage/default/18.prim_esc_test.764899239 |
| /workspace/coverage/default/19.prim_esc_test.435387129 |
| /workspace/coverage/default/2.prim_esc_test.3181111057 |
| /workspace/coverage/default/3.prim_esc_test.2184581061 |
| /workspace/coverage/default/4.prim_esc_test.3732713343 |
| /workspace/coverage/default/5.prim_esc_test.3629063821 |
| /workspace/coverage/default/6.prim_esc_test.1192998076 |
| /workspace/coverage/default/7.prim_esc_test.1812497422 |
| /workspace/coverage/default/8.prim_esc_test.2853743858 |
| /workspace/coverage/default/9.prim_esc_test.3751227816 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/13.prim_esc_test.2979646003 | Jan 10 12:55:12 PM PST 24 | Jan 10 12:56:18 PM PST 24 | 4910688 ps | ||
| T2 | /workspace/coverage/default/16.prim_esc_test.4071545055 | Jan 10 12:55:07 PM PST 24 | Jan 10 12:56:12 PM PST 24 | 5118040 ps | ||
| T3 | /workspace/coverage/default/3.prim_esc_test.2184581061 | Jan 10 12:55:09 PM PST 24 | Jan 10 12:56:13 PM PST 24 | 4731224 ps | ||
| T4 | /workspace/coverage/default/18.prim_esc_test.764899239 | Jan 10 12:55:06 PM PST 24 | Jan 10 12:56:11 PM PST 24 | 4766847 ps | ||
| T8 | /workspace/coverage/default/1.prim_esc_test.321217924 | Jan 10 12:55:05 PM PST 24 | Jan 10 12:56:11 PM PST 24 | 4567511 ps | ||
| T9 | /workspace/coverage/default/10.prim_esc_test.4209108780 | Jan 10 12:55:12 PM PST 24 | Jan 10 12:56:17 PM PST 24 | 5168906 ps | ||
| T5 | /workspace/coverage/default/4.prim_esc_test.3732713343 | Jan 10 12:55:07 PM PST 24 | Jan 10 12:56:12 PM PST 24 | 4688429 ps | ||
| T11 | /workspace/coverage/default/14.prim_esc_test.1238654623 | Jan 10 12:55:11 PM PST 24 | Jan 10 12:56:15 PM PST 24 | 5344413 ps | ||
| T6 | /workspace/coverage/default/17.prim_esc_test.3496382964 | Jan 10 12:55:05 PM PST 24 | Jan 10 12:56:11 PM PST 24 | 5308744 ps | ||
| T7 | /workspace/coverage/default/9.prim_esc_test.3751227816 | Jan 10 12:55:07 PM PST 24 | Jan 10 12:56:13 PM PST 24 | 4882250 ps | ||
| T10 | /workspace/coverage/default/15.prim_esc_test.3263730777 | Jan 10 12:55:06 PM PST 24 | Jan 10 12:56:12 PM PST 24 | 4837909 ps | ||
| T13 | /workspace/coverage/default/5.prim_esc_test.3629063821 | Jan 10 12:55:08 PM PST 24 | Jan 10 12:56:13 PM PST 24 | 4716894 ps | ||
| T12 | /workspace/coverage/default/12.prim_esc_test.660894506 | Jan 10 12:55:06 PM PST 24 | Jan 10 12:56:12 PM PST 24 | 5207139 ps | ||
| T14 | /workspace/coverage/default/0.prim_esc_test.4121638802 | Jan 10 12:55:07 PM PST 24 | Jan 10 12:56:12 PM PST 24 | 4590714 ps | ||
| T15 | /workspace/coverage/default/11.prim_esc_test.683304531 | Jan 10 12:55:06 PM PST 24 | Jan 10 12:56:12 PM PST 24 | 5085198 ps | ||
| T16 | /workspace/coverage/default/7.prim_esc_test.1812497422 | Jan 10 12:55:08 PM PST 24 | Jan 10 12:56:13 PM PST 24 | 4391723 ps | ||
| T17 | /workspace/coverage/default/8.prim_esc_test.2853743858 | Jan 10 12:55:06 PM PST 24 | Jan 10 12:56:12 PM PST 24 | 4692464 ps | ||
| T18 | /workspace/coverage/default/2.prim_esc_test.3181111057 | Jan 10 12:55:09 PM PST 24 | Jan 10 12:56:14 PM PST 24 | 5016153 ps | ||
| T19 | /workspace/coverage/default/19.prim_esc_test.435387129 | Jan 10 12:55:07 PM PST 24 | Jan 10 12:56:13 PM PST 24 | 5378434 ps | ||
| T20 | /workspace/coverage/default/6.prim_esc_test.1192998076 | Jan 10 12:55:06 PM PST 24 | Jan 10 12:56:11 PM PST 24 | 4647117 ps |
| Test location | /workspace/coverage/default/10.prim_esc_test.4209108780 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5168906 ps |
| CPU time | 0.37 seconds |
| Started | Jan 10 12:55:12 PM PST 24 |
| Finished | Jan 10 12:56:17 PM PST 24 |
| Peak memory | 145892 kb |
| Host | smart-5d4a1f41-5bf6-4271-927a-fc1f2a304af3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209108780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.4209108780 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3496382964 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5308744 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:05 PM PST 24 |
| Finished | Jan 10 12:56:11 PM PST 24 |
| Peak memory | 145820 kb |
| Host | smart-76359d14-1ae2-40b9-b1ff-87a2e4bd7531 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3496382964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3496382964 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.321217924 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4567511 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:05 PM PST 24 |
| Finished | Jan 10 12:56:11 PM PST 24 |
| Peak memory | 145884 kb |
| Host | smart-e8bc8a2e-8849-4719-8884-6b50ac706084 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=321217924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.321217924 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.4071545055 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5118040 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:07 PM PST 24 |
| Finished | Jan 10 12:56:12 PM PST 24 |
| Peak memory | 145864 kb |
| Host | smart-b1a595a3-539e-4c5c-9719-aefb8bcb4e01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4071545055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.4071545055 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.4121638802 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4590714 ps |
| CPU time | 0.39 seconds |
| Started | Jan 10 12:55:07 PM PST 24 |
| Finished | Jan 10 12:56:12 PM PST 24 |
| Peak memory | 145900 kb |
| Host | smart-90a89b8c-fa48-4d91-b7fa-4247d3078f66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121638802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.4121638802 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.683304531 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5085198 ps |
| CPU time | 0.37 seconds |
| Started | Jan 10 12:55:06 PM PST 24 |
| Finished | Jan 10 12:56:12 PM PST 24 |
| Peak memory | 145876 kb |
| Host | smart-178ad55e-09c1-43d8-8706-8ba79dfd8402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683304531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.683304531 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.660894506 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5207139 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:06 PM PST 24 |
| Finished | Jan 10 12:56:12 PM PST 24 |
| Peak memory | 145804 kb |
| Host | smart-a935f212-7a38-4d56-9c44-262466b3e03f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660894506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.660894506 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2979646003 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4910688 ps |
| CPU time | 0.37 seconds |
| Started | Jan 10 12:55:12 PM PST 24 |
| Finished | Jan 10 12:56:18 PM PST 24 |
| Peak memory | 145800 kb |
| Host | smart-b3308d1f-0cfd-40bd-96f3-b90b1e2f4c67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979646003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2979646003 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1238654623 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5344413 ps |
| CPU time | 0.37 seconds |
| Started | Jan 10 12:55:11 PM PST 24 |
| Finished | Jan 10 12:56:15 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-d8767ab8-8f9e-42a7-aa0e-a243d5cef1b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1238654623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1238654623 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3263730777 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4837909 ps |
| CPU time | 0.37 seconds |
| Started | Jan 10 12:55:06 PM PST 24 |
| Finished | Jan 10 12:56:12 PM PST 24 |
| Peak memory | 145796 kb |
| Host | smart-4ad19d51-8c86-4302-afdf-82bc916b9d2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263730777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3263730777 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.764899239 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4766847 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:06 PM PST 24 |
| Finished | Jan 10 12:56:11 PM PST 24 |
| Peak memory | 145888 kb |
| Host | smart-634d5c45-e184-455f-b317-ed3789c53ffe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764899239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.764899239 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.435387129 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5378434 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:07 PM PST 24 |
| Finished | Jan 10 12:56:13 PM PST 24 |
| Peak memory | 145860 kb |
| Host | smart-b64813a2-c58c-478a-9c50-dbc859030a71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435387129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.435387129 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3181111057 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5016153 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:09 PM PST 24 |
| Finished | Jan 10 12:56:14 PM PST 24 |
| Peak memory | 145912 kb |
| Host | smart-2904e16c-8243-4969-8444-c1a25923e16e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3181111057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3181111057 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2184581061 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4731224 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:09 PM PST 24 |
| Finished | Jan 10 12:56:13 PM PST 24 |
| Peak memory | 145868 kb |
| Host | smart-e7e5f195-856e-4072-9a55-fdc7b2c9f285 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2184581061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2184581061 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3732713343 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4688429 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:07 PM PST 24 |
| Finished | Jan 10 12:56:12 PM PST 24 |
| Peak memory | 145832 kb |
| Host | smart-74bc2aaf-057b-476c-87f6-755eae91a43c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3732713343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3732713343 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3629063821 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4716894 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:08 PM PST 24 |
| Finished | Jan 10 12:56:13 PM PST 24 |
| Peak memory | 145892 kb |
| Host | smart-8cb2616d-0c25-48a3-a51f-ac40bac0b11f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629063821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3629063821 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1192998076 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4647117 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:06 PM PST 24 |
| Finished | Jan 10 12:56:11 PM PST 24 |
| Peak memory | 145852 kb |
| Host | smart-ee72ad0a-6e8c-40c2-95ef-04e817f872ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192998076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1192998076 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1812497422 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4391723 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:08 PM PST 24 |
| Finished | Jan 10 12:56:13 PM PST 24 |
| Peak memory | 145896 kb |
| Host | smart-02771daf-8051-49ec-896a-61981c6323a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812497422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1812497422 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2853743858 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4692464 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:06 PM PST 24 |
| Finished | Jan 10 12:56:12 PM PST 24 |
| Peak memory | 145888 kb |
| Host | smart-11b32918-4573-48cd-a7c5-8ca3aacd70f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2853743858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2853743858 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3751227816 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4882250 ps |
| CPU time | 0.38 seconds |
| Started | Jan 10 12:55:07 PM PST 24 |
| Finished | Jan 10 12:56:13 PM PST 24 |
| Peak memory | 145888 kb |
| Host | smart-4a8c2492-0d6e-4425-9633-fec89341c701 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751227816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3751227816 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |