| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.80 | 84.80 | 90.48 | 90.48 | 86.36 | 86.36 | 100.00 | 100.00 | 71.43 | 71.43 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/0.prim_esc_test.3789581648 |
| 87.25 | 2.44 | 93.33 | 2.86 | 86.36 | 0.00 | 100.00 | 0.00 | 78.57 | 7.14 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.594302585 |
| 88.98 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.3465698762 |
| 90.12 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/7.prim_esc_test.843127449 |
| 90.72 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.3031810800 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.2849270075 |
| Name |
|---|
| /workspace/coverage/default/10.prim_esc_test.2862788216 |
| /workspace/coverage/default/11.prim_esc_test.1734398017 |
| /workspace/coverage/default/12.prim_esc_test.3675052924 |
| /workspace/coverage/default/14.prim_esc_test.33863083 |
| /workspace/coverage/default/15.prim_esc_test.306801370 |
| /workspace/coverage/default/16.prim_esc_test.1980386776 |
| /workspace/coverage/default/18.prim_esc_test.330599226 |
| /workspace/coverage/default/2.prim_esc_test.814985008 |
| /workspace/coverage/default/3.prim_esc_test.4148200952 |
| /workspace/coverage/default/4.prim_esc_test.3456483431 |
| /workspace/coverage/default/5.prim_esc_test.2798851427 |
| /workspace/coverage/default/6.prim_esc_test.1753986481 |
| /workspace/coverage/default/8.prim_esc_test.2912401661 |
| /workspace/coverage/default/9.prim_esc_test.945510567 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.prim_esc_test.1753986481 | Jan 14 12:53:36 PM PST 24 | Jan 14 12:53:37 PM PST 24 | 4191040 ps | ||
| T2 | /workspace/coverage/default/1.prim_esc_test.3031810800 | Jan 14 12:53:20 PM PST 24 | Jan 14 12:53:22 PM PST 24 | 5225416 ps | ||
| T3 | /workspace/coverage/default/19.prim_esc_test.594302585 | Jan 14 12:53:38 PM PST 24 | Jan 14 12:53:39 PM PST 24 | 4669732 ps | ||
| T4 | /workspace/coverage/default/15.prim_esc_test.306801370 | Jan 14 12:53:36 PM PST 24 | Jan 14 12:53:37 PM PST 24 | 5183427 ps | ||
| T5 | /workspace/coverage/default/7.prim_esc_test.843127449 | Jan 14 12:53:39 PM PST 24 | Jan 14 12:53:40 PM PST 24 | 5100741 ps | ||
| T8 | /workspace/coverage/default/2.prim_esc_test.814985008 | Jan 14 12:53:20 PM PST 24 | Jan 14 12:53:21 PM PST 24 | 5222280 ps | ||
| T16 | /workspace/coverage/default/11.prim_esc_test.1734398017 | Jan 14 12:53:38 PM PST 24 | Jan 14 12:53:38 PM PST 24 | 4857169 ps | ||
| T6 | /workspace/coverage/default/16.prim_esc_test.1980386776 | Jan 14 12:53:37 PM PST 24 | Jan 14 12:53:38 PM PST 24 | 4969485 ps | ||
| T7 | /workspace/coverage/default/0.prim_esc_test.3789581648 | Jan 14 12:53:21 PM PST 24 | Jan 14 12:53:22 PM PST 24 | 4229465 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.2862788216 | Jan 14 12:53:31 PM PST 24 | Jan 14 12:53:32 PM PST 24 | 5167952 ps | ||
| T11 | /workspace/coverage/default/8.prim_esc_test.2912401661 | Jan 14 12:53:30 PM PST 24 | Jan 14 12:53:31 PM PST 24 | 4919488 ps | ||
| T17 | /workspace/coverage/default/12.prim_esc_test.3675052924 | Jan 14 12:53:36 PM PST 24 | Jan 14 12:53:37 PM PST 24 | 5053593 ps | ||
| T12 | /workspace/coverage/default/18.prim_esc_test.330599226 | Jan 14 12:53:39 PM PST 24 | Jan 14 12:53:40 PM PST 24 | 4533479 ps | ||
| T14 | /workspace/coverage/default/17.prim_esc_test.3465698762 | Jan 14 12:53:37 PM PST 24 | Jan 14 12:53:38 PM PST 24 | 4807016 ps | ||
| T18 | /workspace/coverage/default/9.prim_esc_test.945510567 | Jan 14 12:53:33 PM PST 24 | Jan 14 12:53:33 PM PST 24 | 4771015 ps | ||
| T13 | /workspace/coverage/default/14.prim_esc_test.33863083 | Jan 14 12:53:38 PM PST 24 | Jan 14 12:53:39 PM PST 24 | 5116027 ps | ||
| T19 | /workspace/coverage/default/13.prim_esc_test.2849270075 | Jan 14 12:53:39 PM PST 24 | Jan 14 12:53:40 PM PST 24 | 4967825 ps | ||
| T15 | /workspace/coverage/default/5.prim_esc_test.2798851427 | Jan 14 12:53:20 PM PST 24 | Jan 14 12:53:21 PM PST 24 | 5186451 ps | ||
| T9 | /workspace/coverage/default/3.prim_esc_test.4148200952 | Jan 14 12:53:21 PM PST 24 | Jan 14 12:53:22 PM PST 24 | 4278062 ps | ||
| T20 | /workspace/coverage/default/4.prim_esc_test.3456483431 | Jan 14 12:53:20 PM PST 24 | Jan 14 12:53:21 PM PST 24 | 4839068 ps |
| Test location | /workspace/coverage/default/0.prim_esc_test.3789581648 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4229465 ps |
| CPU time | 0.37 seconds |
| Started | Jan 14 12:53:21 PM PST 24 |
| Finished | Jan 14 12:53:22 PM PST 24 |
| Peak memory | 145884 kb |
| Host | smart-7cb77517-8f7f-4bcd-bba7-00abe9186d62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3789581648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3789581648 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.594302585 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4669732 ps |
| CPU time | 0.38 seconds |
| Started | Jan 14 12:53:38 PM PST 24 |
| Finished | Jan 14 12:53:39 PM PST 24 |
| Peak memory | 145864 kb |
| Host | smart-31e89e1b-5068-4896-99c8-db9a6f6ef89a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594302585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.594302585 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3465698762 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4807016 ps |
| CPU time | 0.43 seconds |
| Started | Jan 14 12:53:37 PM PST 24 |
| Finished | Jan 14 12:53:38 PM PST 24 |
| Peak memory | 145884 kb |
| Host | smart-15262430-a866-479f-8331-f12ff82e5ffd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465698762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3465698762 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.843127449 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5100741 ps |
| CPU time | 0.39 seconds |
| Started | Jan 14 12:53:39 PM PST 24 |
| Finished | Jan 14 12:53:40 PM PST 24 |
| Peak memory | 145884 kb |
| Host | smart-27fb2e07-3873-4c8e-9cc6-68e49e39c37c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843127449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.843127449 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3031810800 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5225416 ps |
| CPU time | 0.39 seconds |
| Started | Jan 14 12:53:20 PM PST 24 |
| Finished | Jan 14 12:53:22 PM PST 24 |
| Peak memory | 145844 kb |
| Host | smart-95222967-0df9-46ea-85bb-f544ed7095c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031810800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3031810800 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2849270075 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4967825 ps |
| CPU time | 0.36 seconds |
| Started | Jan 14 12:53:39 PM PST 24 |
| Finished | Jan 14 12:53:40 PM PST 24 |
| Peak memory | 145760 kb |
| Host | smart-10b38ece-2fce-4352-a412-f179af02fc84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2849270075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2849270075 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2862788216 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5167952 ps |
| CPU time | 0.38 seconds |
| Started | Jan 14 12:53:31 PM PST 24 |
| Finished | Jan 14 12:53:32 PM PST 24 |
| Peak memory | 145904 kb |
| Host | smart-1a3023d2-2985-4fba-89f0-53d3929fdf70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862788216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2862788216 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1734398017 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4857169 ps |
| CPU time | 0.37 seconds |
| Started | Jan 14 12:53:38 PM PST 24 |
| Finished | Jan 14 12:53:38 PM PST 24 |
| Peak memory | 145840 kb |
| Host | smart-9c5d8aeb-0d46-4c02-a667-3c9c3c322025 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734398017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1734398017 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3675052924 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5053593 ps |
| CPU time | 0.38 seconds |
| Started | Jan 14 12:53:36 PM PST 24 |
| Finished | Jan 14 12:53:37 PM PST 24 |
| Peak memory | 145868 kb |
| Host | smart-1ce5f999-90ad-42c8-984a-dea99cc0a23e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3675052924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3675052924 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.33863083 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5116027 ps |
| CPU time | 0.37 seconds |
| Started | Jan 14 12:53:38 PM PST 24 |
| Finished | Jan 14 12:53:39 PM PST 24 |
| Peak memory | 145816 kb |
| Host | smart-6a533dc7-fbcf-411b-a0d7-f8e86cb9ef30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33863083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.33863083 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.306801370 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5183427 ps |
| CPU time | 0.38 seconds |
| Started | Jan 14 12:53:36 PM PST 24 |
| Finished | Jan 14 12:53:37 PM PST 24 |
| Peak memory | 145840 kb |
| Host | smart-a10bc22e-38f5-46f7-b20b-4f82ae28e65d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=306801370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.306801370 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1980386776 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4969485 ps |
| CPU time | 0.38 seconds |
| Started | Jan 14 12:53:37 PM PST 24 |
| Finished | Jan 14 12:53:38 PM PST 24 |
| Peak memory | 145852 kb |
| Host | smart-abd27a12-c39f-4ab0-b8a7-c1ea3d4ab062 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1980386776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1980386776 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.330599226 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4533479 ps |
| CPU time | 0.38 seconds |
| Started | Jan 14 12:53:39 PM PST 24 |
| Finished | Jan 14 12:53:40 PM PST 24 |
| Peak memory | 145752 kb |
| Host | smart-5fc86684-8439-44da-a33c-936395abd366 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330599226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.330599226 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.814985008 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5222280 ps |
| CPU time | 0.38 seconds |
| Started | Jan 14 12:53:20 PM PST 24 |
| Finished | Jan 14 12:53:21 PM PST 24 |
| Peak memory | 145840 kb |
| Host | smart-8984504d-bde5-4163-8e10-b21aa915182c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=814985008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.814985008 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.4148200952 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4278062 ps |
| CPU time | 0.38 seconds |
| Started | Jan 14 12:53:21 PM PST 24 |
| Finished | Jan 14 12:53:22 PM PST 24 |
| Peak memory | 145780 kb |
| Host | smart-971c6d3e-78d7-4b2d-9a36-1b99cfa0c5ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4148200952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.4148200952 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3456483431 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4839068 ps |
| CPU time | 0.37 seconds |
| Started | Jan 14 12:53:20 PM PST 24 |
| Finished | Jan 14 12:53:21 PM PST 24 |
| Peak memory | 145796 kb |
| Host | smart-6492a0dd-9000-426b-8f30-3ed0a150e14f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456483431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3456483431 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2798851427 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5186451 ps |
| CPU time | 0.41 seconds |
| Started | Jan 14 12:53:20 PM PST 24 |
| Finished | Jan 14 12:53:21 PM PST 24 |
| Peak memory | 145824 kb |
| Host | smart-a81136e3-76a4-4608-b8a5-0c7d9c48ba4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798851427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2798851427 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1753986481 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4191040 ps |
| CPU time | 0.42 seconds |
| Started | Jan 14 12:53:36 PM PST 24 |
| Finished | Jan 14 12:53:37 PM PST 24 |
| Peak memory | 145904 kb |
| Host | smart-8df26231-73ac-456d-972b-bc3691411ce6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753986481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1753986481 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2912401661 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4919488 ps |
| CPU time | 0.37 seconds |
| Started | Jan 14 12:53:30 PM PST 24 |
| Finished | Jan 14 12:53:31 PM PST 24 |
| Peak memory | 145844 kb |
| Host | smart-19119cac-23e8-4d13-994a-15ab14fd0ed3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912401661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2912401661 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.945510567 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4771015 ps |
| CPU time | 0.38 seconds |
| Started | Jan 14 12:53:33 PM PST 24 |
| Finished | Jan 14 12:53:33 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-39a29b5a-d76d-4671-910d-06f12c0f2141 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945510567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.945510567 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |