| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.72 | 85.72 | 92.38 | 92.38 | 84.09 | 84.09 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/0.prim_esc_test.3837935975 |
| 87.84 | 2.12 | 93.33 | 0.95 | 86.36 | 2.27 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.3626580433 |
| 89.58 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/2.prim_esc_test.3645812958 |
| 90.72 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.3909733236 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/8.prim_esc_test.2183895441 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.2533413928 |
| /workspace/coverage/default/10.prim_esc_test.1503035583 |
| /workspace/coverage/default/11.prim_esc_test.1400731212 |
| /workspace/coverage/default/12.prim_esc_test.3738671567 |
| /workspace/coverage/default/13.prim_esc_test.2186824469 |
| /workspace/coverage/default/15.prim_esc_test.283329127 |
| /workspace/coverage/default/16.prim_esc_test.735367086 |
| /workspace/coverage/default/17.prim_esc_test.4191972255 |
| /workspace/coverage/default/18.prim_esc_test.1078793368 |
| /workspace/coverage/default/3.prim_esc_test.3087810218 |
| /workspace/coverage/default/4.prim_esc_test.2741361432 |
| /workspace/coverage/default/5.prim_esc_test.171995117 |
| /workspace/coverage/default/6.prim_esc_test.287141584 |
| /workspace/coverage/default/7.prim_esc_test.4030962069 |
| /workspace/coverage/default/9.prim_esc_test.3057445244 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_esc_test.171995117 | Jan 21 03:00:25 PM PST 24 | Jan 21 03:00:26 PM PST 24 | 5004660 ps | ||
| T2 | /workspace/coverage/default/1.prim_esc_test.2533413928 | Jan 21 03:00:29 PM PST 24 | Jan 21 03:00:30 PM PST 24 | 5036731 ps | ||
| T3 | /workspace/coverage/default/10.prim_esc_test.1503035583 | Jan 21 03:00:22 PM PST 24 | Jan 21 03:00:23 PM PST 24 | 5356464 ps | ||
| T4 | /workspace/coverage/default/19.prim_esc_test.3626580433 | Jan 21 03:00:40 PM PST 24 | Jan 21 03:00:41 PM PST 24 | 4955697 ps | ||
| T16 | /workspace/coverage/default/6.prim_esc_test.287141584 | Jan 21 03:00:24 PM PST 24 | Jan 21 03:00:25 PM PST 24 | 5064151 ps | ||
| T5 | /workspace/coverage/default/16.prim_esc_test.735367086 | Jan 21 03:00:40 PM PST 24 | Jan 21 03:00:41 PM PST 24 | 4835959 ps | ||
| T6 | /workspace/coverage/default/4.prim_esc_test.2741361432 | Jan 21 03:00:24 PM PST 24 | Jan 21 03:00:25 PM PST 24 | 4613998 ps | ||
| T7 | /workspace/coverage/default/7.prim_esc_test.4030962069 | Jan 21 03:00:24 PM PST 24 | Jan 21 03:00:25 PM PST 24 | 4760447 ps | ||
| T10 | /workspace/coverage/default/0.prim_esc_test.3837935975 | Jan 21 03:44:34 PM PST 24 | Jan 21 03:44:35 PM PST 24 | 4670738 ps | ||
| T13 | /workspace/coverage/default/8.prim_esc_test.2183895441 | Jan 21 03:00:29 PM PST 24 | Jan 21 03:00:30 PM PST 24 | 4683258 ps | ||
| T14 | /workspace/coverage/default/2.prim_esc_test.3645812958 | Jan 21 03:00:28 PM PST 24 | Jan 21 03:00:29 PM PST 24 | 4900665 ps | ||
| T8 | /workspace/coverage/default/14.prim_esc_test.3909733236 | Jan 21 03:00:45 PM PST 24 | Jan 21 03:00:46 PM PST 24 | 5301113 ps | ||
| T11 | /workspace/coverage/default/13.prim_esc_test.2186824469 | Jan 21 03:00:37 PM PST 24 | Jan 21 03:00:38 PM PST 24 | 4644061 ps | ||
| T12 | /workspace/coverage/default/11.prim_esc_test.1400731212 | Jan 21 03:00:25 PM PST 24 | Jan 21 03:00:26 PM PST 24 | 5145639 ps | ||
| T17 | /workspace/coverage/default/12.prim_esc_test.3738671567 | Jan 21 03:00:41 PM PST 24 | Jan 21 03:00:42 PM PST 24 | 5175932 ps | ||
| T18 | /workspace/coverage/default/18.prim_esc_test.1078793368 | Jan 21 03:00:37 PM PST 24 | Jan 21 03:00:38 PM PST 24 | 5092638 ps | ||
| T15 | /workspace/coverage/default/9.prim_esc_test.3057445244 | Jan 21 03:00:24 PM PST 24 | Jan 21 03:00:25 PM PST 24 | 5007124 ps | ||
| T9 | /workspace/coverage/default/3.prim_esc_test.3087810218 | Jan 21 03:00:22 PM PST 24 | Jan 21 03:00:23 PM PST 24 | 4363285 ps | ||
| T19 | /workspace/coverage/default/15.prim_esc_test.283329127 | Jan 21 03:00:34 PM PST 24 | Jan 21 03:00:35 PM PST 24 | 4938431 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.4191972255 | Jan 21 03:00:37 PM PST 24 | Jan 21 03:00:39 PM PST 24 | 4658865 ps |
| Test location | /workspace/coverage/default/0.prim_esc_test.3837935975 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4670738 ps |
| CPU time | 0.37 seconds |
| Started | Jan 21 03:44:34 PM PST 24 |
| Finished | Jan 21 03:44:35 PM PST 24 |
| Peak memory | 146300 kb |
| Host | smart-aaeebf03-ee26-4c86-ac6a-82d4a476ac12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837935975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3837935975 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3626580433 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4955697 ps |
| CPU time | 0.4 seconds |
| Started | Jan 21 03:00:40 PM PST 24 |
| Finished | Jan 21 03:00:41 PM PST 24 |
| Peak memory | 146312 kb |
| Host | smart-846d7e04-ffd3-48a3-aab1-bbb348102887 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626580433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3626580433 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3645812958 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4900665 ps |
| CPU time | 0.38 seconds |
| Started | Jan 21 03:00:28 PM PST 24 |
| Finished | Jan 21 03:00:29 PM PST 24 |
| Peak memory | 146280 kb |
| Host | smart-47e52996-d0f2-4522-8b3e-b16fec3965c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3645812958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3645812958 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3909733236 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5301113 ps |
| CPU time | 0.4 seconds |
| Started | Jan 21 03:00:45 PM PST 24 |
| Finished | Jan 21 03:00:46 PM PST 24 |
| Peak memory | 146312 kb |
| Host | smart-301245d6-d15d-4ade-afa4-900187c22044 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909733236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3909733236 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2183895441 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4683258 ps |
| CPU time | 0.39 seconds |
| Started | Jan 21 03:00:29 PM PST 24 |
| Finished | Jan 21 03:00:30 PM PST 24 |
| Peak memory | 146268 kb |
| Host | smart-79392024-8b26-4fa4-823e-48e09113c898 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183895441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2183895441 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2533413928 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5036731 ps |
| CPU time | 0.39 seconds |
| Started | Jan 21 03:00:29 PM PST 24 |
| Finished | Jan 21 03:00:30 PM PST 24 |
| Peak memory | 146280 kb |
| Host | smart-0f9fa643-730d-4b24-b041-3c1223b619db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533413928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2533413928 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1503035583 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5356464 ps |
| CPU time | 0.37 seconds |
| Started | Jan 21 03:00:22 PM PST 24 |
| Finished | Jan 21 03:00:23 PM PST 24 |
| Peak memory | 146268 kb |
| Host | smart-9f27cf25-0868-436d-8b7e-bb9c3152aa8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503035583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1503035583 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1400731212 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5145639 ps |
| CPU time | 0.38 seconds |
| Started | Jan 21 03:00:25 PM PST 24 |
| Finished | Jan 21 03:00:26 PM PST 24 |
| Peak memory | 146300 kb |
| Host | smart-5bbfedde-22e4-400f-8dd6-074541fd2aff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400731212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1400731212 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3738671567 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5175932 ps |
| CPU time | 0.37 seconds |
| Started | Jan 21 03:00:41 PM PST 24 |
| Finished | Jan 21 03:00:42 PM PST 24 |
| Peak memory | 146284 kb |
| Host | smart-86cf38c0-aeb4-4f25-adc9-5ea2593aee5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738671567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3738671567 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2186824469 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4644061 ps |
| CPU time | 0.39 seconds |
| Started | Jan 21 03:00:37 PM PST 24 |
| Finished | Jan 21 03:00:38 PM PST 24 |
| Peak memory | 146184 kb |
| Host | smart-f82c6a58-ec8f-4409-a570-5acb967dda67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186824469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2186824469 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.283329127 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4938431 ps |
| CPU time | 0.38 seconds |
| Started | Jan 21 03:00:34 PM PST 24 |
| Finished | Jan 21 03:00:35 PM PST 24 |
| Peak memory | 146292 kb |
| Host | smart-420328eb-2d29-4ed3-bb0b-5214fa55e358 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283329127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.283329127 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.735367086 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4835959 ps |
| CPU time | 0.37 seconds |
| Started | Jan 21 03:00:40 PM PST 24 |
| Finished | Jan 21 03:00:41 PM PST 24 |
| Peak memory | 146264 kb |
| Host | smart-605ad053-fab5-40ea-b7ec-54c697bab4c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=735367086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.735367086 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.4191972255 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4658865 ps |
| CPU time | 0.37 seconds |
| Started | Jan 21 03:00:37 PM PST 24 |
| Finished | Jan 21 03:00:39 PM PST 24 |
| Peak memory | 146304 kb |
| Host | smart-6764d98b-640e-4560-80a4-e2327485fa2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191972255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.4191972255 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1078793368 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5092638 ps |
| CPU time | 0.39 seconds |
| Started | Jan 21 03:00:37 PM PST 24 |
| Finished | Jan 21 03:00:38 PM PST 24 |
| Peak memory | 146240 kb |
| Host | smart-b5457150-f72e-48d2-bbff-3461452fef49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078793368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1078793368 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3087810218 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4363285 ps |
| CPU time | 0.39 seconds |
| Started | Jan 21 03:00:22 PM PST 24 |
| Finished | Jan 21 03:00:23 PM PST 24 |
| Peak memory | 146232 kb |
| Host | smart-cef71748-efb3-4fbe-911e-07ed7854f779 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3087810218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3087810218 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2741361432 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4613998 ps |
| CPU time | 0.39 seconds |
| Started | Jan 21 03:00:24 PM PST 24 |
| Finished | Jan 21 03:00:25 PM PST 24 |
| Peak memory | 146244 kb |
| Host | smart-27821aed-1438-4865-9396-fa4c258b824e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2741361432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2741361432 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.171995117 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5004660 ps |
| CPU time | 0.4 seconds |
| Started | Jan 21 03:00:25 PM PST 24 |
| Finished | Jan 21 03:00:26 PM PST 24 |
| Peak memory | 146300 kb |
| Host | smart-ca9b2d9d-f0c8-448a-a739-8a004ddaf636 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171995117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.171995117 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.287141584 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5064151 ps |
| CPU time | 0.41 seconds |
| Started | Jan 21 03:00:24 PM PST 24 |
| Finished | Jan 21 03:00:25 PM PST 24 |
| Peak memory | 146268 kb |
| Host | smart-60a52af7-db0c-4d31-95ea-95e084b680ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=287141584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.287141584 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4030962069 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4760447 ps |
| CPU time | 0.4 seconds |
| Started | Jan 21 03:00:24 PM PST 24 |
| Finished | Jan 21 03:00:25 PM PST 24 |
| Peak memory | 146244 kb |
| Host | smart-d3a7d159-1c8f-4ac2-93c9-a004543dec1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030962069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4030962069 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3057445244 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5007124 ps |
| CPU time | 0.37 seconds |
| Started | Jan 21 03:00:24 PM PST 24 |
| Finished | Jan 21 03:00:25 PM PST 24 |
| Peak memory | 146312 kb |
| Host | smart-ac7c6559-2cad-4ecd-9c11-4748e43fcedb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057445244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3057445244 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |