| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.02 | 85.02 | 90.48 | 90.48 | 84.09 | 84.09 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/3.prim_esc_test.669294875 |
| 87.46 | 2.44 | 93.33 | 2.86 | 84.09 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.684841068 |
| 89.58 | 2.12 | 94.29 | 0.95 | 86.36 | 2.27 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.851129794 |
| 90.72 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.555734786 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.993300312 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.138421125 |
| /workspace/coverage/default/1.prim_esc_test.3113192580 |
| /workspace/coverage/default/10.prim_esc_test.2167769670 |
| /workspace/coverage/default/11.prim_esc_test.625027575 |
| /workspace/coverage/default/12.prim_esc_test.2708443747 |
| /workspace/coverage/default/14.prim_esc_test.2014210600 |
| /workspace/coverage/default/15.prim_esc_test.1194690474 |
| /workspace/coverage/default/18.prim_esc_test.3592004824 |
| /workspace/coverage/default/2.prim_esc_test.3951426785 |
| /workspace/coverage/default/4.prim_esc_test.2409620742 |
| /workspace/coverage/default/5.prim_esc_test.1634357551 |
| /workspace/coverage/default/6.prim_esc_test.870581822 |
| /workspace/coverage/default/7.prim_esc_test.3670784052 |
| /workspace/coverage/default/8.prim_esc_test.609064973 |
| /workspace/coverage/default/9.prim_esc_test.34023604 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/19.prim_esc_test.555734786 | Jan 24 10:40:46 PM PST 24 | Jan 24 10:40:47 PM PST 24 | 5085495 ps | ||
| T2 | /workspace/coverage/default/14.prim_esc_test.2014210600 | Jan 24 10:40:32 PM PST 24 | Jan 24 10:40:33 PM PST 24 | 4811727 ps | ||
| T3 | /workspace/coverage/default/0.prim_esc_test.138421125 | Jan 24 10:40:05 PM PST 24 | Jan 24 10:40:06 PM PST 24 | 4744829 ps | ||
| T7 | /workspace/coverage/default/1.prim_esc_test.3113192580 | Jan 24 10:40:14 PM PST 24 | Jan 24 10:40:22 PM PST 24 | 4240095 ps | ||
| T8 | /workspace/coverage/default/12.prim_esc_test.2708443747 | Jan 24 10:40:30 PM PST 24 | Jan 24 10:40:31 PM PST 24 | 5213781 ps | ||
| T4 | /workspace/coverage/default/6.prim_esc_test.870581822 | Jan 24 10:40:13 PM PST 24 | Jan 24 10:40:17 PM PST 24 | 5103131 ps | ||
| T5 | /workspace/coverage/default/3.prim_esc_test.669294875 | Jan 24 10:40:28 PM PST 24 | Jan 24 10:40:30 PM PST 24 | 5285177 ps | ||
| T14 | /workspace/coverage/default/7.prim_esc_test.3670784052 | Jan 24 10:40:28 PM PST 24 | Jan 24 10:40:30 PM PST 24 | 5217096 ps | ||
| T6 | /workspace/coverage/default/9.prim_esc_test.34023604 | Jan 24 10:40:30 PM PST 24 | Jan 24 10:40:32 PM PST 24 | 4664275 ps | ||
| T16 | /workspace/coverage/default/10.prim_esc_test.2167769670 | Jan 24 10:40:30 PM PST 24 | Jan 24 10:40:32 PM PST 24 | 4737050 ps | ||
| T17 | /workspace/coverage/default/8.prim_esc_test.609064973 | Jan 24 10:40:14 PM PST 24 | Jan 24 10:40:22 PM PST 24 | 4569279 ps | ||
| T11 | /workspace/coverage/default/18.prim_esc_test.3592004824 | Jan 24 10:40:50 PM PST 24 | Jan 24 10:40:53 PM PST 24 | 5174223 ps | ||
| T12 | /workspace/coverage/default/2.prim_esc_test.3951426785 | Jan 24 10:40:28 PM PST 24 | Jan 24 10:40:29 PM PST 24 | 5052991 ps | ||
| T18 | /workspace/coverage/default/15.prim_esc_test.1194690474 | Jan 24 10:40:46 PM PST 24 | Jan 24 10:40:47 PM PST 24 | 5442336 ps | ||
| T19 | /workspace/coverage/default/13.prim_esc_test.851129794 | Jan 24 10:40:30 PM PST 24 | Jan 24 10:40:32 PM PST 24 | 4470294 ps | ||
| T13 | /workspace/coverage/default/16.prim_esc_test.993300312 | Jan 24 10:40:49 PM PST 24 | Jan 24 10:40:51 PM PST 24 | 5147868 ps | ||
| T20 | /workspace/coverage/default/11.prim_esc_test.625027575 | Jan 24 10:40:30 PM PST 24 | Jan 24 10:40:31 PM PST 24 | 5152468 ps | ||
| T9 | /workspace/coverage/default/5.prim_esc_test.1634357551 | Jan 24 10:40:28 PM PST 24 | Jan 24 10:40:29 PM PST 24 | 4909482 ps | ||
| T10 | /workspace/coverage/default/17.prim_esc_test.684841068 | Jan 24 10:40:53 PM PST 24 | Jan 24 10:41:00 PM PST 24 | 4630376 ps | ||
| T15 | /workspace/coverage/default/4.prim_esc_test.2409620742 | Jan 24 10:40:28 PM PST 24 | Jan 24 10:40:29 PM PST 24 | 4867255 ps |
| Test location | /workspace/coverage/default/3.prim_esc_test.669294875 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5285177 ps |
| CPU time | 0.38 seconds |
| Started | Jan 24 10:40:28 PM PST 24 |
| Finished | Jan 24 10:40:30 PM PST 24 |
| Peak memory | 146292 kb |
| Host | smart-835e11f3-b4e1-4061-bc1b-f2e1e71b8269 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669294875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.669294875 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.684841068 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4630376 ps |
| CPU time | 0.38 seconds |
| Started | Jan 24 10:40:53 PM PST 24 |
| Finished | Jan 24 10:41:00 PM PST 24 |
| Peak memory | 146392 kb |
| Host | smart-75b037b5-6b79-4906-b89b-a96da8dd5cac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=684841068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.684841068 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.851129794 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4470294 ps |
| CPU time | 0.37 seconds |
| Started | Jan 24 10:40:30 PM PST 24 |
| Finished | Jan 24 10:40:32 PM PST 24 |
| Peak memory | 146328 kb |
| Host | smart-10b1f9c0-7285-4ec7-8620-7d386a76d66f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851129794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.851129794 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.555734786 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5085495 ps |
| CPU time | 0.38 seconds |
| Started | Jan 24 10:40:46 PM PST 24 |
| Finished | Jan 24 10:40:47 PM PST 24 |
| Peak memory | 146320 kb |
| Host | smart-a0aa26a7-aa0d-47fd-b567-c3e9fdd340bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555734786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.555734786 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.993300312 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5147868 ps |
| CPU time | 0.43 seconds |
| Started | Jan 24 10:40:49 PM PST 24 |
| Finished | Jan 24 10:40:51 PM PST 24 |
| Peak memory | 146384 kb |
| Host | smart-c2ac3f6b-27cb-4927-ae26-7b2fd31f518b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993300312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.993300312 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.138421125 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4744829 ps |
| CPU time | 0.4 seconds |
| Started | Jan 24 10:40:05 PM PST 24 |
| Finished | Jan 24 10:40:06 PM PST 24 |
| Peak memory | 146384 kb |
| Host | smart-b43105fa-b080-411e-927b-2806219b35b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138421125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.138421125 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3113192580 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4240095 ps |
| CPU time | 0.39 seconds |
| Started | Jan 24 10:40:14 PM PST 24 |
| Finished | Jan 24 10:40:22 PM PST 24 |
| Peak memory | 146336 kb |
| Host | smart-d81b7ccf-dcc1-4610-8597-dbbd2139238a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113192580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3113192580 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2167769670 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4737050 ps |
| CPU time | 0.38 seconds |
| Started | Jan 24 10:40:30 PM PST 24 |
| Finished | Jan 24 10:40:32 PM PST 24 |
| Peak memory | 146328 kb |
| Host | smart-89e34cf5-d7ee-4e0e-83e8-486c77f1bea0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167769670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2167769670 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.625027575 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5152468 ps |
| CPU time | 0.39 seconds |
| Started | Jan 24 10:40:30 PM PST 24 |
| Finished | Jan 24 10:40:31 PM PST 24 |
| Peak memory | 146304 kb |
| Host | smart-a80dd0d4-f7ea-4c30-8fdd-afbbc84e0547 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625027575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.625027575 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2708443747 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5213781 ps |
| CPU time | 0.38 seconds |
| Started | Jan 24 10:40:30 PM PST 24 |
| Finished | Jan 24 10:40:31 PM PST 24 |
| Peak memory | 146336 kb |
| Host | smart-902e7416-3c3d-4396-89bc-c9963ca4fdb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708443747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2708443747 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2014210600 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4811727 ps |
| CPU time | 0.41 seconds |
| Started | Jan 24 10:40:32 PM PST 24 |
| Finished | Jan 24 10:40:33 PM PST 24 |
| Peak memory | 146320 kb |
| Host | smart-1b06e95c-c800-4ecb-9c75-bf77431cbbaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014210600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2014210600 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1194690474 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5442336 ps |
| CPU time | 0.42 seconds |
| Started | Jan 24 10:40:46 PM PST 24 |
| Finished | Jan 24 10:40:47 PM PST 24 |
| Peak memory | 146292 kb |
| Host | smart-fe83fb88-5b68-4e21-bf68-69de444c7ee7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194690474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1194690474 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3592004824 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5174223 ps |
| CPU time | 0.43 seconds |
| Started | Jan 24 10:40:50 PM PST 24 |
| Finished | Jan 24 10:40:53 PM PST 24 |
| Peak memory | 146316 kb |
| Host | smart-01165ed3-656a-4138-b079-8550489af1b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592004824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3592004824 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3951426785 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5052991 ps |
| CPU time | 0.39 seconds |
| Started | Jan 24 10:40:28 PM PST 24 |
| Finished | Jan 24 10:40:29 PM PST 24 |
| Peak memory | 146136 kb |
| Host | smart-64d27555-2207-413f-aaf1-8e608aad3426 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951426785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3951426785 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2409620742 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4867255 ps |
| CPU time | 0.38 seconds |
| Started | Jan 24 10:40:28 PM PST 24 |
| Finished | Jan 24 10:40:29 PM PST 24 |
| Peak memory | 146140 kb |
| Host | smart-71e05028-894d-4936-827a-30fb9424c53c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2409620742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2409620742 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1634357551 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4909482 ps |
| CPU time | 0.38 seconds |
| Started | Jan 24 10:40:28 PM PST 24 |
| Finished | Jan 24 10:40:29 PM PST 24 |
| Peak memory | 146316 kb |
| Host | smart-02e2e050-a83e-4516-be27-67e13839277f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1634357551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1634357551 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.870581822 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5103131 ps |
| CPU time | 0.38 seconds |
| Started | Jan 24 10:40:13 PM PST 24 |
| Finished | Jan 24 10:40:17 PM PST 24 |
| Peak memory | 146288 kb |
| Host | smart-03ab4139-2213-427c-b9c8-22503410aee4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870581822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.870581822 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3670784052 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5217096 ps |
| CPU time | 0.38 seconds |
| Started | Jan 24 10:40:28 PM PST 24 |
| Finished | Jan 24 10:40:30 PM PST 24 |
| Peak memory | 146316 kb |
| Host | smart-452e9299-b9b1-4220-aedf-33afef0886d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670784052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3670784052 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.609064973 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4569279 ps |
| CPU time | 0.39 seconds |
| Started | Jan 24 10:40:14 PM PST 24 |
| Finished | Jan 24 10:40:22 PM PST 24 |
| Peak memory | 146328 kb |
| Host | smart-89ed07d8-fd72-44a4-a252-a4fd641b86ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=609064973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.609064973 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.34023604 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4664275 ps |
| CPU time | 0.39 seconds |
| Started | Jan 24 10:40:30 PM PST 24 |
| Finished | Jan 24 10:40:32 PM PST 24 |
| Peak memory | 146332 kb |
| Host | smart-4e0c3851-14cd-4a8c-889a-b920ebe3dd2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34023604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.34023604 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |