Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.40 85.40 90.48 90.48 86.36 86.36 100.00 100.00 75.00 75.00 79.07 79.07 81.48 81.48 /workspace/coverage/default/9.prim_esc_test.299691501
87.84 2.44 93.33 2.86 86.36 0.00 100.00 0.00 82.14 7.14 83.72 4.65 81.48 0.00 /workspace/coverage/default/10.prim_esc_test.1866442507
90.17 2.33 94.29 0.95 86.36 0.00 100.00 0.00 92.86 10.71 86.05 2.33 81.48 0.00 /workspace/coverage/default/18.prim_esc_test.3763041567
91.31 1.14 95.24 0.95 86.36 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/19.prim_esc_test.2196428564

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.4216088938
/workspace/coverage/default/1.prim_esc_test.1242647538
/workspace/coverage/default/11.prim_esc_test.4193013764
/workspace/coverage/default/12.prim_esc_test.2712963504
/workspace/coverage/default/13.prim_esc_test.1634427624
/workspace/coverage/default/14.prim_esc_test.70720372
/workspace/coverage/default/15.prim_esc_test.424245135
/workspace/coverage/default/16.prim_esc_test.3375082001
/workspace/coverage/default/17.prim_esc_test.3724056472
/workspace/coverage/default/2.prim_esc_test.1687545151
/workspace/coverage/default/3.prim_esc_test.2217234319
/workspace/coverage/default/4.prim_esc_test.3974626752
/workspace/coverage/default/5.prim_esc_test.882744983
/workspace/coverage/default/6.prim_esc_test.4035830219
/workspace/coverage/default/7.prim_esc_test.3835739297
/workspace/coverage/default/8.prim_esc_test.960311639



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.prim_esc_test.2712963504 Feb 04 12:33:24 PM PST 24 Feb 04 12:33:35 PM PST 24 5461727 ps
T2 /workspace/coverage/default/14.prim_esc_test.70720372 Feb 04 12:33:23 PM PST 24 Feb 04 12:33:32 PM PST 24 4703681 ps
T3 /workspace/coverage/default/8.prim_esc_test.960311639 Feb 04 12:33:26 PM PST 24 Feb 04 12:33:39 PM PST 24 4690670 ps
T8 /workspace/coverage/default/16.prim_esc_test.3375082001 Feb 04 12:33:20 PM PST 24 Feb 04 12:33:26 PM PST 24 4693678 ps
T4 /workspace/coverage/default/15.prim_esc_test.424245135 Feb 04 12:33:20 PM PST 24 Feb 04 12:33:26 PM PST 24 4894040 ps
T5 /workspace/coverage/default/1.prim_esc_test.1242647538 Feb 04 12:33:34 PM PST 24 Feb 04 12:33:43 PM PST 24 4831711 ps
T6 /workspace/coverage/default/17.prim_esc_test.3724056472 Feb 04 12:33:27 PM PST 24 Feb 04 12:33:41 PM PST 24 5170350 ps
T14 /workspace/coverage/default/6.prim_esc_test.4035830219 Feb 04 12:33:34 PM PST 24 Feb 04 12:33:43 PM PST 24 4736452 ps
T12 /workspace/coverage/default/5.prim_esc_test.882744983 Feb 04 12:33:38 PM PST 24 Feb 04 12:33:46 PM PST 24 4900661 ps
T11 /workspace/coverage/default/9.prim_esc_test.299691501 Feb 04 12:33:30 PM PST 24 Feb 04 12:33:41 PM PST 24 5061045 ps
T9 /workspace/coverage/default/7.prim_esc_test.3835739297 Feb 04 12:33:20 PM PST 24 Feb 04 12:33:26 PM PST 24 4723473 ps
T13 /workspace/coverage/default/19.prim_esc_test.2196428564 Feb 04 12:33:27 PM PST 24 Feb 04 12:33:41 PM PST 24 4575485 ps
T15 /workspace/coverage/default/0.prim_esc_test.4216088938 Feb 04 12:33:26 PM PST 24 Feb 04 12:33:40 PM PST 24 4582769 ps
T16 /workspace/coverage/default/13.prim_esc_test.1634427624 Feb 04 12:33:24 PM PST 24 Feb 04 12:33:33 PM PST 24 4545374 ps
T17 /workspace/coverage/default/2.prim_esc_test.1687545151 Feb 04 12:33:33 PM PST 24 Feb 04 12:33:42 PM PST 24 4827510 ps
T10 /workspace/coverage/default/3.prim_esc_test.2217234319 Feb 04 12:33:34 PM PST 24 Feb 04 12:33:43 PM PST 24 4157227 ps
T18 /workspace/coverage/default/11.prim_esc_test.4193013764 Feb 04 12:33:24 PM PST 24 Feb 04 12:33:36 PM PST 24 4368954 ps
T19 /workspace/coverage/default/4.prim_esc_test.3974626752 Feb 04 12:33:34 PM PST 24 Feb 04 12:33:43 PM PST 24 5243441 ps
T20 /workspace/coverage/default/10.prim_esc_test.1866442507 Feb 04 12:33:28 PM PST 24 Feb 04 12:33:41 PM PST 24 4256795 ps
T7 /workspace/coverage/default/18.prim_esc_test.3763041567 Feb 04 12:33:24 PM PST 24 Feb 04 12:33:36 PM PST 24 4689292 ps

Test location /workspace/coverage/default/9.prim_esc_test.299691501
Short name T11
Test name
Test status
Simulation time 5061045 ps
CPU time 0.37 seconds
Started Feb 04 12:33:30 PM PST 24
Finished Feb 04 12:33:41 PM PST 24
Peak memory 146164 kb
Host smart-a8b04f12-2780-4dc0-be04-c7074908ee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299691501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.299691501
Directory /workspace/9.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.1866442507
Short name T20
Test name
Test status
Simulation time 4256795 ps
CPU time 0.37 seconds
Started Feb 04 12:33:28 PM PST 24
Finished Feb 04 12:33:41 PM PST 24
Peak memory 146164 kb
Host smart-1b8a3ad4-372e-417c-bdf3-cb07b971bd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866442507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1866442507
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.3763041567
Short name T7
Test name
Test status
Simulation time 4689292 ps
CPU time 0.42 seconds
Started Feb 04 12:33:24 PM PST 24
Finished Feb 04 12:33:36 PM PST 24
Peak memory 146188 kb
Host smart-bd948132-64b8-437b-bd5c-f6cdafd52937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763041567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3763041567
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2196428564
Short name T13
Test name
Test status
Simulation time 4575485 ps
CPU time 0.37 seconds
Started Feb 04 12:33:27 PM PST 24
Finished Feb 04 12:33:41 PM PST 24
Peak memory 146164 kb
Host smart-8e515f46-9244-4fc7-a817-40e853e6aeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196428564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2196428564
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.4216088938
Short name T15
Test name
Test status
Simulation time 4582769 ps
CPU time 0.36 seconds
Started Feb 04 12:33:26 PM PST 24
Finished Feb 04 12:33:40 PM PST 24
Peak memory 146180 kb
Host smart-48c915c2-0a5a-455c-b617-89549981f3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216088938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.4216088938
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.1242647538
Short name T5
Test name
Test status
Simulation time 4831711 ps
CPU time 0.36 seconds
Started Feb 04 12:33:34 PM PST 24
Finished Feb 04 12:33:43 PM PST 24
Peak memory 146156 kb
Host smart-c04a9cbd-9ff3-465e-9085-409246fbe75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242647538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1242647538
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.4193013764
Short name T18
Test name
Test status
Simulation time 4368954 ps
CPU time 0.37 seconds
Started Feb 04 12:33:24 PM PST 24
Finished Feb 04 12:33:36 PM PST 24
Peak memory 146196 kb
Host smart-894c4097-2239-4ff6-9f9d-10ef82540326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193013764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.4193013764
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.2712963504
Short name T1
Test name
Test status
Simulation time 5461727 ps
CPU time 0.38 seconds
Started Feb 04 12:33:24 PM PST 24
Finished Feb 04 12:33:35 PM PST 24
Peak memory 146188 kb
Host smart-b565d499-c83e-45ca-99e1-2871ab137d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712963504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2712963504
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.1634427624
Short name T16
Test name
Test status
Simulation time 4545374 ps
CPU time 0.37 seconds
Started Feb 04 12:33:24 PM PST 24
Finished Feb 04 12:33:33 PM PST 24
Peak memory 146164 kb
Host smart-b3de91bc-69ef-4fcd-9004-5c28005ac660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634427624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1634427624
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.70720372
Short name T2
Test name
Test status
Simulation time 4703681 ps
CPU time 0.37 seconds
Started Feb 04 12:33:23 PM PST 24
Finished Feb 04 12:33:32 PM PST 24
Peak memory 146252 kb
Host smart-07f3bec7-26e3-4a51-82a3-c75f0cf5aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70720372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.70720372
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.424245135
Short name T4
Test name
Test status
Simulation time 4894040 ps
CPU time 0.37 seconds
Started Feb 04 12:33:20 PM PST 24
Finished Feb 04 12:33:26 PM PST 24
Peak memory 146332 kb
Host smart-cee6b122-1fe5-4791-afab-5051e895c362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424245135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.424245135
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.3375082001
Short name T8
Test name
Test status
Simulation time 4693678 ps
CPU time 0.36 seconds
Started Feb 04 12:33:20 PM PST 24
Finished Feb 04 12:33:26 PM PST 24
Peak memory 146140 kb
Host smart-25f0824d-149e-4a68-97ff-245127809b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375082001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3375082001
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.3724056472
Short name T6
Test name
Test status
Simulation time 5170350 ps
CPU time 0.37 seconds
Started Feb 04 12:33:27 PM PST 24
Finished Feb 04 12:33:41 PM PST 24
Peak memory 146236 kb
Host smart-c90deff4-f020-469e-b3eb-484ba14e57e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724056472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3724056472
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.1687545151
Short name T17
Test name
Test status
Simulation time 4827510 ps
CPU time 0.36 seconds
Started Feb 04 12:33:33 PM PST 24
Finished Feb 04 12:33:42 PM PST 24
Peak memory 146156 kb
Host smart-3f26c12d-42b6-4a73-8306-4701945653b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687545151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1687545151
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.2217234319
Short name T10
Test name
Test status
Simulation time 4157227 ps
CPU time 0.37 seconds
Started Feb 04 12:33:34 PM PST 24
Finished Feb 04 12:33:43 PM PST 24
Peak memory 146100 kb
Host smart-fd72ca09-239f-41dc-a2cb-cc20dcc77f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217234319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2217234319
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.3974626752
Short name T19
Test name
Test status
Simulation time 5243441 ps
CPU time 0.37 seconds
Started Feb 04 12:33:34 PM PST 24
Finished Feb 04 12:33:43 PM PST 24
Peak memory 146116 kb
Host smart-b9fa375b-56f6-4096-b3b6-fa8538909af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974626752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3974626752
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.882744983
Short name T12
Test name
Test status
Simulation time 4900661 ps
CPU time 0.39 seconds
Started Feb 04 12:33:38 PM PST 24
Finished Feb 04 12:33:46 PM PST 24
Peak memory 146172 kb
Host smart-fc0a0836-e12f-4d9a-96fc-9ee4d38e4fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882744983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.882744983
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.4035830219
Short name T14
Test name
Test status
Simulation time 4736452 ps
CPU time 0.41 seconds
Started Feb 04 12:33:34 PM PST 24
Finished Feb 04 12:33:43 PM PST 24
Peak memory 146208 kb
Host smart-ad6eb635-3bdc-4b18-888e-0f298a3c6b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035830219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4035830219
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.3835739297
Short name T9
Test name
Test status
Simulation time 4723473 ps
CPU time 0.37 seconds
Started Feb 04 12:33:20 PM PST 24
Finished Feb 04 12:33:26 PM PST 24
Peak memory 146148 kb
Host smart-2b85d989-193b-4108-9181-d7cbecf82f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835739297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3835739297
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.960311639
Short name T3
Test name
Test status
Simulation time 4690670 ps
CPU time 0.37 seconds
Started Feb 04 12:33:26 PM PST 24
Finished Feb 04 12:33:39 PM PST 24
Peak memory 146200 kb
Host smart-eb1015ea-1210-43e2-aaf4-41d283521695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960311639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.960311639
Directory /workspace/8.prim_esc_test/latest
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