| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.10 | 86.10 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/18.prim_esc_test.618318821 |
| 88.44 | 2.33 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.1726188673 |
| 90.17 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.1938550552 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.3771782405 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.1033590046 |
| /workspace/coverage/default/10.prim_esc_test.4246990674 |
| /workspace/coverage/default/12.prim_esc_test.1971385011 |
| /workspace/coverage/default/13.prim_esc_test.3937728496 |
| /workspace/coverage/default/14.prim_esc_test.3621193546 |
| /workspace/coverage/default/15.prim_esc_test.2142291227 |
| /workspace/coverage/default/17.prim_esc_test.2458112257 |
| /workspace/coverage/default/19.prim_esc_test.2376229426 |
| /workspace/coverage/default/2.prim_esc_test.833934546 |
| /workspace/coverage/default/3.prim_esc_test.3942468362 |
| /workspace/coverage/default/4.prim_esc_test.3556181918 |
| /workspace/coverage/default/5.prim_esc_test.2442177120 |
| /workspace/coverage/default/6.prim_esc_test.5679446 |
| /workspace/coverage/default/7.prim_esc_test.1619013173 |
| /workspace/coverage/default/8.prim_esc_test.663892795 |
| /workspace/coverage/default/9.prim_esc_test.2325776912 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/13.prim_esc_test.3937728496 | Feb 18 12:37:23 PM PST 24 | Feb 18 12:37:24 PM PST 24 | 4681693 ps | ||
| T2 | /workspace/coverage/default/0.prim_esc_test.1726188673 | Feb 18 12:37:15 PM PST 24 | Feb 18 12:37:17 PM PST 24 | 5285891 ps | ||
| T3 | /workspace/coverage/default/2.prim_esc_test.833934546 | Feb 18 12:37:20 PM PST 24 | Feb 18 12:37:22 PM PST 24 | 4903488 ps | ||
| T4 | /workspace/coverage/default/12.prim_esc_test.1971385011 | Feb 18 12:37:24 PM PST 24 | Feb 18 12:37:25 PM PST 24 | 4923503 ps | ||
| T12 | /workspace/coverage/default/17.prim_esc_test.2458112257 | Feb 18 12:37:25 PM PST 24 | Feb 18 12:37:26 PM PST 24 | 4668142 ps | ||
| T5 | /workspace/coverage/default/18.prim_esc_test.618318821 | Feb 18 12:37:20 PM PST 24 | Feb 18 12:37:22 PM PST 24 | 4781066 ps | ||
| T13 | /workspace/coverage/default/14.prim_esc_test.3621193546 | Feb 18 12:37:19 PM PST 24 | Feb 18 12:37:20 PM PST 24 | 4903985 ps | ||
| T14 | /workspace/coverage/default/9.prim_esc_test.2325776912 | Feb 18 12:37:25 PM PST 24 | Feb 18 12:37:27 PM PST 24 | 4545222 ps | ||
| T7 | /workspace/coverage/default/7.prim_esc_test.1619013173 | Feb 18 12:37:20 PM PST 24 | Feb 18 12:37:22 PM PST 24 | 4647083 ps | ||
| T8 | /workspace/coverage/default/10.prim_esc_test.4246990674 | Feb 18 12:37:20 PM PST 24 | Feb 18 12:37:21 PM PST 24 | 4545848 ps | ||
| T16 | /workspace/coverage/default/8.prim_esc_test.663892795 | Feb 18 12:37:20 PM PST 24 | Feb 18 12:37:21 PM PST 24 | 4953749 ps | ||
| T6 | /workspace/coverage/default/11.prim_esc_test.3771782405 | Feb 18 12:37:23 PM PST 24 | Feb 18 12:37:24 PM PST 24 | 5362640 ps | ||
| T17 | /workspace/coverage/default/3.prim_esc_test.3942468362 | Feb 18 12:37:17 PM PST 24 | Feb 18 12:37:18 PM PST 24 | 5615602 ps | ||
| T9 | /workspace/coverage/default/5.prim_esc_test.2442177120 | Feb 18 12:37:16 PM PST 24 | Feb 18 12:37:17 PM PST 24 | 4518576 ps | ||
| T18 | /workspace/coverage/default/15.prim_esc_test.2142291227 | Feb 18 12:37:21 PM PST 24 | Feb 18 12:37:23 PM PST 24 | 4979944 ps | ||
| T11 | /workspace/coverage/default/1.prim_esc_test.1033590046 | Feb 18 12:37:16 PM PST 24 | Feb 18 12:37:17 PM PST 24 | 4370988 ps | ||
| T10 | /workspace/coverage/default/16.prim_esc_test.1938550552 | Feb 18 12:37:19 PM PST 24 | Feb 18 12:37:20 PM PST 24 | 4561318 ps | ||
| T19 | /workspace/coverage/default/4.prim_esc_test.3556181918 | Feb 18 12:37:19 PM PST 24 | Feb 18 12:37:20 PM PST 24 | 4748059 ps | ||
| T15 | /workspace/coverage/default/6.prim_esc_test.5679446 | Feb 18 12:37:19 PM PST 24 | Feb 18 12:37:20 PM PST 24 | 4736740 ps | ||
| T20 | /workspace/coverage/default/19.prim_esc_test.2376229426 | Feb 18 12:37:21 PM PST 24 | Feb 18 12:37:23 PM PST 24 | 5113720 ps |
| Test location | /workspace/coverage/default/18.prim_esc_test.618318821 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4781066 ps |
| CPU time | 0.38 seconds |
| Started | Feb 18 12:37:20 PM PST 24 |
| Finished | Feb 18 12:37:22 PM PST 24 |
| Peak memory | 146184 kb |
| Host | smart-8d46e5dd-3e3e-4540-8a7b-09011ee08568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618318821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.618318821 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1726188673 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5285891 ps |
| CPU time | 0.37 seconds |
| Started | Feb 18 12:37:15 PM PST 24 |
| Finished | Feb 18 12:37:17 PM PST 24 |
| Peak memory | 146132 kb |
| Host | smart-e24ce113-210e-45b3-ad19-6a402e91a568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726188673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1726188673 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1938550552 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4561318 ps |
| CPU time | 0.38 seconds |
| Started | Feb 18 12:37:19 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146252 kb |
| Host | smart-67f70b5e-894e-4183-9eed-46bc309047a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938550552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1938550552 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3771782405 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5362640 ps |
| CPU time | 0.4 seconds |
| Started | Feb 18 12:37:23 PM PST 24 |
| Finished | Feb 18 12:37:24 PM PST 24 |
| Peak memory | 146224 kb |
| Host | smart-2c9ef808-47f0-494e-98b5-776218714473 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771782405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3771782405 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1033590046 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4370988 ps |
| CPU time | 0.37 seconds |
| Started | Feb 18 12:37:16 PM PST 24 |
| Finished | Feb 18 12:37:17 PM PST 24 |
| Peak memory | 146132 kb |
| Host | smart-36eff52c-6a59-44c8-a7ee-74af6b145422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1033590046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1033590046 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.4246990674 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4545848 ps |
| CPU time | 0.41 seconds |
| Started | Feb 18 12:37:20 PM PST 24 |
| Finished | Feb 18 12:37:21 PM PST 24 |
| Peak memory | 146304 kb |
| Host | smart-fbec9624-419b-4f00-a04e-c55ed467a9e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246990674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.4246990674 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1971385011 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4923503 ps |
| CPU time | 0.38 seconds |
| Started | Feb 18 12:37:24 PM PST 24 |
| Finished | Feb 18 12:37:25 PM PST 24 |
| Peak memory | 146224 kb |
| Host | smart-b8e387ec-5c81-4834-86ae-06207d6df743 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1971385011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1971385011 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3937728496 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4681693 ps |
| CPU time | 0.37 seconds |
| Started | Feb 18 12:37:23 PM PST 24 |
| Finished | Feb 18 12:37:24 PM PST 24 |
| Peak memory | 146228 kb |
| Host | smart-9986a383-2aa2-49a1-b1db-a6b64144335a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3937728496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3937728496 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3621193546 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4903985 ps |
| CPU time | 0.37 seconds |
| Started | Feb 18 12:37:19 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146216 kb |
| Host | smart-eb8f2b7c-430c-4867-be46-588cfe530b80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621193546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3621193546 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2142291227 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4979944 ps |
| CPU time | 0.39 seconds |
| Started | Feb 18 12:37:21 PM PST 24 |
| Finished | Feb 18 12:37:23 PM PST 24 |
| Peak memory | 146216 kb |
| Host | smart-1b2cabf0-67b5-4603-aef6-c65f4cdce347 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2142291227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2142291227 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2458112257 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4668142 ps |
| CPU time | 0.42 seconds |
| Started | Feb 18 12:37:25 PM PST 24 |
| Finished | Feb 18 12:37:26 PM PST 24 |
| Peak memory | 146192 kb |
| Host | smart-e50d4356-27b3-45a4-a75f-a13f2902d140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2458112257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2458112257 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2376229426 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5113720 ps |
| CPU time | 0.38 seconds |
| Started | Feb 18 12:37:21 PM PST 24 |
| Finished | Feb 18 12:37:23 PM PST 24 |
| Peak memory | 146204 kb |
| Host | smart-6216e68e-e06b-449b-8b17-8c4317ffe5a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376229426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2376229426 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.833934546 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4903488 ps |
| CPU time | 0.41 seconds |
| Started | Feb 18 12:37:20 PM PST 24 |
| Finished | Feb 18 12:37:22 PM PST 24 |
| Peak memory | 146164 kb |
| Host | smart-17c83f0d-b15c-4426-a7cb-efb36dd7fed9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833934546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.833934546 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3942468362 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5615602 ps |
| CPU time | 0.38 seconds |
| Started | Feb 18 12:37:17 PM PST 24 |
| Finished | Feb 18 12:37:18 PM PST 24 |
| Peak memory | 146196 kb |
| Host | smart-4ba0b352-f3ac-4373-bb1d-cfe38ec0eff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3942468362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3942468362 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3556181918 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4748059 ps |
| CPU time | 0.37 seconds |
| Started | Feb 18 12:37:19 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146148 kb |
| Host | smart-859add96-2c75-478d-b93f-20811d2a01c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3556181918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3556181918 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2442177120 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4518576 ps |
| CPU time | 0.38 seconds |
| Started | Feb 18 12:37:16 PM PST 24 |
| Finished | Feb 18 12:37:17 PM PST 24 |
| Peak memory | 146216 kb |
| Host | smart-5874b995-325b-4fd2-8b88-eb2d7db8ae4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442177120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2442177120 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.5679446 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4736740 ps |
| CPU time | 0.37 seconds |
| Started | Feb 18 12:37:19 PM PST 24 |
| Finished | Feb 18 12:37:20 PM PST 24 |
| Peak memory | 146160 kb |
| Host | smart-c0379232-687d-4c59-a19c-f2f5258752eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5679446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.5679446 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1619013173 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4647083 ps |
| CPU time | 0.37 seconds |
| Started | Feb 18 12:37:20 PM PST 24 |
| Finished | Feb 18 12:37:22 PM PST 24 |
| Peak memory | 146260 kb |
| Host | smart-0eac6fc8-6186-432c-aa3a-6277ca6b126e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619013173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1619013173 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.663892795 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4953749 ps |
| CPU time | 0.4 seconds |
| Started | Feb 18 12:37:20 PM PST 24 |
| Finished | Feb 18 12:37:21 PM PST 24 |
| Peak memory | 146128 kb |
| Host | smart-d009fd93-627b-4648-aa12-4a0a89580c08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663892795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.663892795 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2325776912 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4545222 ps |
| CPU time | 0.38 seconds |
| Started | Feb 18 12:37:25 PM PST 24 |
| Finished | Feb 18 12:37:27 PM PST 24 |
| Peak memory | 146200 kb |
| Host | smart-c00bbed7-f4a9-4ee0-b565-46aa69760e0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2325776912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2325776912 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |