| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.10 | 86.10 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/10.prim_esc_test.3722574424 |
| 87.84 | 1.74 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.2299412582 |
| 89.58 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/9.prim_esc_test.365673146 |
| 90.72 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.2228107699 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.4276829081 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3373465316 |
| /workspace/coverage/default/1.prim_esc_test.202092527 |
| /workspace/coverage/default/12.prim_esc_test.2118718396 |
| /workspace/coverage/default/14.prim_esc_test.3919301111 |
| /workspace/coverage/default/15.prim_esc_test.3764747634 |
| /workspace/coverage/default/17.prim_esc_test.1299786781 |
| /workspace/coverage/default/18.prim_esc_test.904751336 |
| /workspace/coverage/default/19.prim_esc_test.3819482164 |
| /workspace/coverage/default/2.prim_esc_test.1715029347 |
| /workspace/coverage/default/3.prim_esc_test.775006806 |
| /workspace/coverage/default/4.prim_esc_test.3841920960 |
| /workspace/coverage/default/5.prim_esc_test.2829373338 |
| /workspace/coverage/default/6.prim_esc_test.2498366842 |
| /workspace/coverage/default/7.prim_esc_test.3883900823 |
| /workspace/coverage/default/8.prim_esc_test.1365551217 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_esc_test.1299786781 | Feb 21 12:32:32 PM PST 24 | Feb 21 12:32:33 PM PST 24 | 4787185 ps | ||
| T2 | /workspace/coverage/default/9.prim_esc_test.365673146 | Feb 21 12:32:30 PM PST 24 | Feb 21 12:32:31 PM PST 24 | 4896699 ps | ||
| T3 | /workspace/coverage/default/7.prim_esc_test.3883900823 | Feb 21 12:32:33 PM PST 24 | Feb 21 12:32:36 PM PST 24 | 5182249 ps | ||
| T6 | /workspace/coverage/default/6.prim_esc_test.2498366842 | Feb 21 12:32:50 PM PST 24 | Feb 21 12:32:52 PM PST 24 | 5185951 ps | ||
| T17 | /workspace/coverage/default/0.prim_esc_test.3373465316 | Feb 21 12:32:35 PM PST 24 | Feb 21 12:32:37 PM PST 24 | 4733380 ps | ||
| T4 | /workspace/coverage/default/16.prim_esc_test.2299412582 | Feb 21 12:32:31 PM PST 24 | Feb 21 12:32:32 PM PST 24 | 5088735 ps | ||
| T5 | /workspace/coverage/default/3.prim_esc_test.775006806 | Feb 21 12:32:34 PM PST 24 | Feb 21 12:32:37 PM PST 24 | 4750295 ps | ||
| T15 | /workspace/coverage/default/5.prim_esc_test.2829373338 | Feb 21 12:32:21 PM PST 24 | Feb 21 12:32:22 PM PST 24 | 4888515 ps | ||
| T8 | /workspace/coverage/default/10.prim_esc_test.3722574424 | Feb 21 12:32:31 PM PST 24 | Feb 21 12:32:32 PM PST 24 | 4991812 ps | ||
| T16 | /workspace/coverage/default/19.prim_esc_test.3819482164 | Feb 21 12:32:26 PM PST 24 | Feb 21 12:32:27 PM PST 24 | 4975093 ps | ||
| T7 | /workspace/coverage/default/4.prim_esc_test.3841920960 | Feb 21 12:32:43 PM PST 24 | Feb 21 12:32:43 PM PST 24 | 5008281 ps | ||
| T13 | /workspace/coverage/default/18.prim_esc_test.904751336 | Feb 21 12:32:38 PM PST 24 | Feb 21 12:32:39 PM PST 24 | 4367031 ps | ||
| T9 | /workspace/coverage/default/12.prim_esc_test.2118718396 | Feb 21 12:32:17 PM PST 24 | Feb 21 12:32:20 PM PST 24 | 4938915 ps | ||
| T10 | /workspace/coverage/default/2.prim_esc_test.1715029347 | Feb 21 12:32:34 PM PST 24 | Feb 21 12:32:37 PM PST 24 | 5471835 ps | ||
| T18 | /workspace/coverage/default/1.prim_esc_test.202092527 | Feb 21 12:32:19 PM PST 24 | Feb 21 12:32:21 PM PST 24 | 5219890 ps | ||
| T11 | /workspace/coverage/default/13.prim_esc_test.2228107699 | Feb 21 12:32:28 PM PST 24 | Feb 21 12:32:29 PM PST 24 | 5101942 ps | ||
| T12 | /workspace/coverage/default/8.prim_esc_test.1365551217 | Feb 21 12:32:43 PM PST 24 | Feb 21 12:32:44 PM PST 24 | 4822841 ps | ||
| T19 | /workspace/coverage/default/15.prim_esc_test.3764747634 | Feb 21 12:32:52 PM PST 24 | Feb 21 12:32:58 PM PST 24 | 5038736 ps | ||
| T14 | /workspace/coverage/default/11.prim_esc_test.4276829081 | Feb 21 12:32:29 PM PST 24 | Feb 21 12:32:30 PM PST 24 | 4429366 ps | ||
| T20 | /workspace/coverage/default/14.prim_esc_test.3919301111 | Feb 21 12:32:46 PM PST 24 | Feb 21 12:32:49 PM PST 24 | 5689443 ps |
| Test location | /workspace/coverage/default/10.prim_esc_test.3722574424 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4991812 ps |
| CPU time | 0.36 seconds |
| Started | Feb 21 12:32:31 PM PST 24 |
| Finished | Feb 21 12:32:32 PM PST 24 |
| Peak memory | 146220 kb |
| Host | smart-d36694db-c0db-4efb-8cfd-4ae11cd04b22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722574424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3722574424 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2299412582 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5088735 ps |
| CPU time | 0.36 seconds |
| Started | Feb 21 12:32:31 PM PST 24 |
| Finished | Feb 21 12:32:32 PM PST 24 |
| Peak memory | 146220 kb |
| Host | smart-0f56a504-4176-4f30-82d5-ecfbc9f83171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299412582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2299412582 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.365673146 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4896699 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 12:32:30 PM PST 24 |
| Finished | Feb 21 12:32:31 PM PST 24 |
| Peak memory | 146192 kb |
| Host | smart-ff1a6c02-f970-4ecc-95c1-bec8d1d3c8d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365673146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.365673146 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2228107699 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5101942 ps |
| CPU time | 0.42 seconds |
| Started | Feb 21 12:32:28 PM PST 24 |
| Finished | Feb 21 12:32:29 PM PST 24 |
| Peak memory | 144864 kb |
| Host | smart-67b7b297-b91b-4b26-95e6-aeea7bc601a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228107699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2228107699 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.4276829081 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4429366 ps |
| CPU time | 0.36 seconds |
| Started | Feb 21 12:32:29 PM PST 24 |
| Finished | Feb 21 12:32:30 PM PST 24 |
| Peak memory | 146172 kb |
| Host | smart-5f8962a7-6891-4050-a7c8-792fb39dd608 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276829081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.4276829081 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3373465316 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4733380 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 12:32:35 PM PST 24 |
| Finished | Feb 21 12:32:37 PM PST 24 |
| Peak memory | 146276 kb |
| Host | smart-b7f2e6ca-6b4d-45e6-8200-25ffdfe94a69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373465316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3373465316 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.202092527 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5219890 ps |
| CPU time | 0.36 seconds |
| Started | Feb 21 12:32:19 PM PST 24 |
| Finished | Feb 21 12:32:21 PM PST 24 |
| Peak memory | 146264 kb |
| Host | smart-5e809bc1-a0fe-4db8-8d46-314f8d97c462 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202092527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.202092527 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2118718396 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4938915 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:32:17 PM PST 24 |
| Finished | Feb 21 12:32:20 PM PST 24 |
| Peak memory | 146296 kb |
| Host | smart-da65fcdb-58e3-46c6-a60d-84b6ce1ce137 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2118718396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2118718396 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3919301111 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5689443 ps |
| CPU time | 0.39 seconds |
| Started | Feb 21 12:32:46 PM PST 24 |
| Finished | Feb 21 12:32:49 PM PST 24 |
| Peak memory | 146204 kb |
| Host | smart-d93b0164-31bf-463f-9fc9-8ab36513da2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3919301111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3919301111 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3764747634 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5038736 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:32:52 PM PST 24 |
| Finished | Feb 21 12:32:58 PM PST 24 |
| Peak memory | 146276 kb |
| Host | smart-39c0a2f4-122f-428a-8549-52b9ba942a0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764747634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3764747634 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1299786781 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4787185 ps |
| CPU time | 0.41 seconds |
| Started | Feb 21 12:32:32 PM PST 24 |
| Finished | Feb 21 12:32:33 PM PST 24 |
| Peak memory | 146148 kb |
| Host | smart-ffd99d2f-731b-49ec-888e-af93e31acdf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1299786781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1299786781 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.904751336 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4367031 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 12:32:38 PM PST 24 |
| Finished | Feb 21 12:32:39 PM PST 24 |
| Peak memory | 146268 kb |
| Host | smart-6ca2f6b1-22c7-4b2c-a217-8076cbcc13a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=904751336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.904751336 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3819482164 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4975093 ps |
| CPU time | 0.36 seconds |
| Started | Feb 21 12:32:26 PM PST 24 |
| Finished | Feb 21 12:32:27 PM PST 24 |
| Peak memory | 146244 kb |
| Host | smart-a66ea3c5-9019-4d2f-b1c6-438f002b3f56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819482164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3819482164 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1715029347 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5471835 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 12:32:34 PM PST 24 |
| Finished | Feb 21 12:32:37 PM PST 24 |
| Peak memory | 146276 kb |
| Host | smart-4be7f99f-bf9f-48f6-bf00-89c0d9dedf4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1715029347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1715029347 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.775006806 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4750295 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 12:32:34 PM PST 24 |
| Finished | Feb 21 12:32:37 PM PST 24 |
| Peak memory | 146280 kb |
| Host | smart-e394aed3-0360-4846-9496-d9626eeeb542 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775006806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.775006806 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3841920960 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5008281 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:32:43 PM PST 24 |
| Finished | Feb 21 12:32:43 PM PST 24 |
| Peak memory | 146276 kb |
| Host | smart-cadb28c0-81f8-4a22-8e94-24d1f15729cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841920960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3841920960 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2829373338 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4888515 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 12:32:21 PM PST 24 |
| Finished | Feb 21 12:32:22 PM PST 24 |
| Peak memory | 146120 kb |
| Host | smart-c721954f-705d-45fd-b7f6-fc2777d15057 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2829373338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2829373338 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2498366842 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5185951 ps |
| CPU time | 0.37 seconds |
| Started | Feb 21 12:32:50 PM PST 24 |
| Finished | Feb 21 12:32:52 PM PST 24 |
| Peak memory | 146188 kb |
| Host | smart-d93da30d-7e63-4006-9c45-6f67fde20e68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498366842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2498366842 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3883900823 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5182249 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:32:33 PM PST 24 |
| Finished | Feb 21 12:32:36 PM PST 24 |
| Peak memory | 146188 kb |
| Host | smart-bccfb48c-347f-417c-a4f5-7914a9181c49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883900823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3883900823 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1365551217 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4822841 ps |
| CPU time | 0.38 seconds |
| Started | Feb 21 12:32:43 PM PST 24 |
| Finished | Feb 21 12:32:44 PM PST 24 |
| Peak memory | 146276 kb |
| Host | smart-1d851df5-26bf-4317-b235-a2e8b775b54b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365551217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1365551217 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |