| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.02 | 85.02 | 90.48 | 90.48 | 84.09 | 84.09 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/3.prim_esc_test.1799006736 |
| 87.84 | 2.82 | 93.33 | 2.86 | 86.36 | 2.27 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.383795341 |
| 90.17 | 2.33 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 10.71 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/9.prim_esc_test.1131224639 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.3834154734 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.2132236722 |
| /workspace/coverage/default/10.prim_esc_test.988060767 |
| /workspace/coverage/default/11.prim_esc_test.1588133795 |
| /workspace/coverage/default/12.prim_esc_test.3652674896 |
| /workspace/coverage/default/13.prim_esc_test.469536554 |
| /workspace/coverage/default/15.prim_esc_test.4288065011 |
| /workspace/coverage/default/16.prim_esc_test.2794067871 |
| /workspace/coverage/default/17.prim_esc_test.1740362300 |
| /workspace/coverage/default/18.prim_esc_test.1524843949 |
| /workspace/coverage/default/19.prim_esc_test.3001003100 |
| /workspace/coverage/default/2.prim_esc_test.3365774002 |
| /workspace/coverage/default/4.prim_esc_test.1754884509 |
| /workspace/coverage/default/5.prim_esc_test.1573524539 |
| /workspace/coverage/default/6.prim_esc_test.4098308415 |
| /workspace/coverage/default/7.prim_esc_test.3841293891 |
| /workspace/coverage/default/8.prim_esc_test.358614567 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_esc_test.1740362300 | Feb 25 12:34:19 PM PST 24 | Feb 25 12:34:19 PM PST 24 | 5409303 ps | ||
| T2 | /workspace/coverage/default/9.prim_esc_test.1131224639 | Feb 25 12:34:00 PM PST 24 | Feb 25 12:34:00 PM PST 24 | 4736904 ps | ||
| T3 | /workspace/coverage/default/1.prim_esc_test.2132236722 | Feb 25 12:34:07 PM PST 24 | Feb 25 12:34:07 PM PST 24 | 5023165 ps | ||
| T5 | /workspace/coverage/default/3.prim_esc_test.1799006736 | Feb 25 12:33:59 PM PST 24 | Feb 25 12:34:00 PM PST 24 | 4697037 ps | ||
| T4 | /workspace/coverage/default/11.prim_esc_test.1588133795 | Feb 25 12:34:21 PM PST 24 | Feb 25 12:34:22 PM PST 24 | 4813563 ps | ||
| T15 | /workspace/coverage/default/18.prim_esc_test.1524843949 | Feb 25 12:34:15 PM PST 24 | Feb 25 12:34:16 PM PST 24 | 4833665 ps | ||
| T6 | /workspace/coverage/default/8.prim_esc_test.358614567 | Feb 25 12:34:03 PM PST 24 | Feb 25 12:34:03 PM PST 24 | 4674751 ps | ||
| T8 | /workspace/coverage/default/14.prim_esc_test.383795341 | Feb 25 12:34:01 PM PST 24 | Feb 25 12:34:02 PM PST 24 | 4951929 ps | ||
| T11 | /workspace/coverage/default/13.prim_esc_test.469536554 | Feb 25 12:34:10 PM PST 24 | Feb 25 12:34:10 PM PST 24 | 5274877 ps | ||
| T13 | /workspace/coverage/default/0.prim_esc_test.3834154734 | Feb 25 12:34:02 PM PST 24 | Feb 25 12:34:03 PM PST 24 | 4653437 ps | ||
| T17 | /workspace/coverage/default/7.prim_esc_test.3841293891 | Feb 25 12:34:06 PM PST 24 | Feb 25 12:34:07 PM PST 24 | 4390211 ps | ||
| T16 | /workspace/coverage/default/12.prim_esc_test.3652674896 | Feb 25 12:34:12 PM PST 24 | Feb 25 12:34:13 PM PST 24 | 4775185 ps | ||
| T9 | /workspace/coverage/default/4.prim_esc_test.1754884509 | Feb 25 12:34:03 PM PST 24 | Feb 25 12:34:03 PM PST 24 | 4405809 ps | ||
| T14 | /workspace/coverage/default/5.prim_esc_test.1573524539 | Feb 25 12:34:18 PM PST 24 | Feb 25 12:34:18 PM PST 24 | 5603124 ps | ||
| T7 | /workspace/coverage/default/16.prim_esc_test.2794067871 | Feb 25 12:34:12 PM PST 24 | Feb 25 12:34:13 PM PST 24 | 4885399 ps | ||
| T18 | /workspace/coverage/default/19.prim_esc_test.3001003100 | Feb 25 12:34:36 PM PST 24 | Feb 25 12:34:37 PM PST 24 | 4509087 ps | ||
| T12 | /workspace/coverage/default/2.prim_esc_test.3365774002 | Feb 25 12:34:21 PM PST 24 | Feb 25 12:34:21 PM PST 24 | 4822048 ps | ||
| T19 | /workspace/coverage/default/15.prim_esc_test.4288065011 | Feb 25 12:34:05 PM PST 24 | Feb 25 12:34:05 PM PST 24 | 4773210 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.988060767 | Feb 25 12:34:41 PM PST 24 | Feb 25 12:34:42 PM PST 24 | 4870707 ps | ||
| T20 | /workspace/coverage/default/6.prim_esc_test.4098308415 | Feb 25 12:34:21 PM PST 24 | Feb 25 12:34:21 PM PST 24 | 5060096 ps |
| Test location | /workspace/coverage/default/3.prim_esc_test.1799006736 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4697037 ps |
| CPU time | 0.36 seconds |
| Started | Feb 25 12:33:59 PM PST 24 |
| Finished | Feb 25 12:34:00 PM PST 24 |
| Peak memory | 146256 kb |
| Host | smart-80c99824-2c3f-42bb-9e3f-30aa2d4f4b45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799006736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1799006736 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.383795341 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4951929 ps |
| CPU time | 0.39 seconds |
| Started | Feb 25 12:34:01 PM PST 24 |
| Finished | Feb 25 12:34:02 PM PST 24 |
| Peak memory | 146264 kb |
| Host | smart-c856ba03-a3a6-4f39-a825-645a8c48667f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383795341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.383795341 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1131224639 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4736904 ps |
| CPU time | 0.36 seconds |
| Started | Feb 25 12:34:00 PM PST 24 |
| Finished | Feb 25 12:34:00 PM PST 24 |
| Peak memory | 146328 kb |
| Host | smart-dd59f59b-35a9-40ca-8905-a784c57e2605 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131224639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1131224639 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3834154734 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4653437 ps |
| CPU time | 0.38 seconds |
| Started | Feb 25 12:34:02 PM PST 24 |
| Finished | Feb 25 12:34:03 PM PST 24 |
| Peak memory | 146240 kb |
| Host | smart-c2cb460e-8897-458f-a2cd-a0e1fc53ce02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3834154734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3834154734 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2132236722 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5023165 ps |
| CPU time | 0.38 seconds |
| Started | Feb 25 12:34:07 PM PST 24 |
| Finished | Feb 25 12:34:07 PM PST 24 |
| Peak memory | 146252 kb |
| Host | smart-8f6de4e4-fed0-4260-91d0-6dc3f5d7dae3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132236722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2132236722 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.988060767 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4870707 ps |
| CPU time | 0.39 seconds |
| Started | Feb 25 12:34:41 PM PST 24 |
| Finished | Feb 25 12:34:42 PM PST 24 |
| Peak memory | 146268 kb |
| Host | smart-88ef6cab-077b-4a6b-9a77-8b4c029b0783 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988060767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.988060767 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1588133795 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4813563 ps |
| CPU time | 0.41 seconds |
| Started | Feb 25 12:34:21 PM PST 24 |
| Finished | Feb 25 12:34:22 PM PST 24 |
| Peak memory | 146260 kb |
| Host | smart-00170650-a8be-4353-9b97-a2776b9d9692 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1588133795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1588133795 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3652674896 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4775185 ps |
| CPU time | 0.36 seconds |
| Started | Feb 25 12:34:12 PM PST 24 |
| Finished | Feb 25 12:34:13 PM PST 24 |
| Peak memory | 146252 kb |
| Host | smart-ee45acc6-61c4-442c-ab12-5688b6b41ecd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652674896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3652674896 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.469536554 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5274877 ps |
| CPU time | 0.39 seconds |
| Started | Feb 25 12:34:10 PM PST 24 |
| Finished | Feb 25 12:34:10 PM PST 24 |
| Peak memory | 146268 kb |
| Host | smart-597c6eda-803b-4485-9ed5-1e07aaf21a7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=469536554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.469536554 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.4288065011 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4773210 ps |
| CPU time | 0.38 seconds |
| Started | Feb 25 12:34:05 PM PST 24 |
| Finished | Feb 25 12:34:05 PM PST 24 |
| Peak memory | 146244 kb |
| Host | smart-1c15ade0-be06-4f6c-bd49-a829590272a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288065011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.4288065011 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2794067871 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4885399 ps |
| CPU time | 0.38 seconds |
| Started | Feb 25 12:34:12 PM PST 24 |
| Finished | Feb 25 12:34:13 PM PST 24 |
| Peak memory | 146260 kb |
| Host | smart-e5e1cb10-4675-4bdc-a7b3-2d385a196402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794067871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2794067871 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1740362300 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5409303 ps |
| CPU time | 0.37 seconds |
| Started | Feb 25 12:34:19 PM PST 24 |
| Finished | Feb 25 12:34:19 PM PST 24 |
| Peak memory | 146236 kb |
| Host | smart-9f58db2f-a98c-4f4c-977a-ea20bcc842e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740362300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1740362300 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1524843949 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4833665 ps |
| CPU time | 0.37 seconds |
| Started | Feb 25 12:34:15 PM PST 24 |
| Finished | Feb 25 12:34:16 PM PST 24 |
| Peak memory | 146256 kb |
| Host | smart-fdffdb65-8637-4bea-bad6-c330194b1a1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524843949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1524843949 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3001003100 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4509087 ps |
| CPU time | 0.37 seconds |
| Started | Feb 25 12:34:36 PM PST 24 |
| Finished | Feb 25 12:34:37 PM PST 24 |
| Peak memory | 146188 kb |
| Host | smart-0ff10694-4586-4d02-8753-6b66cc94f5e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001003100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3001003100 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3365774002 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4822048 ps |
| CPU time | 0.39 seconds |
| Started | Feb 25 12:34:21 PM PST 24 |
| Finished | Feb 25 12:34:21 PM PST 24 |
| Peak memory | 146260 kb |
| Host | smart-a2e75b61-19ad-4537-b115-457aefadaa1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365774002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3365774002 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1754884509 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4405809 ps |
| CPU time | 0.39 seconds |
| Started | Feb 25 12:34:03 PM PST 24 |
| Finished | Feb 25 12:34:03 PM PST 24 |
| Peak memory | 146240 kb |
| Host | smart-5a1548a2-638a-4abe-bc1e-58c0b3ec7de8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754884509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1754884509 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1573524539 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5603124 ps |
| CPU time | 0.38 seconds |
| Started | Feb 25 12:34:18 PM PST 24 |
| Finished | Feb 25 12:34:18 PM PST 24 |
| Peak memory | 146252 kb |
| Host | smart-006b3940-b726-4178-86f5-4704c5839f3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1573524539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1573524539 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.4098308415 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5060096 ps |
| CPU time | 0.36 seconds |
| Started | Feb 25 12:34:21 PM PST 24 |
| Finished | Feb 25 12:34:21 PM PST 24 |
| Peak memory | 146260 kb |
| Host | smart-3cc88143-f958-42c4-bbb2-45d1f7a82c9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098308415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4098308415 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3841293891 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4390211 ps |
| CPU time | 0.4 seconds |
| Started | Feb 25 12:34:06 PM PST 24 |
| Finished | Feb 25 12:34:07 PM PST 24 |
| Peak memory | 146244 kb |
| Host | smart-8414b8d0-1e8d-4fb5-9e4d-0ba858a1290b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841293891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3841293891 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.358614567 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4674751 ps |
| CPU time | 0.38 seconds |
| Started | Feb 25 12:34:03 PM PST 24 |
| Finished | Feb 25 12:34:03 PM PST 24 |
| Peak memory | 146252 kb |
| Host | smart-204cc118-133c-4590-b5ec-96a62d1f3116 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=358614567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.358614567 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |