| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.40 | 85.40 | 90.48 | 90.48 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/6.prim_esc_test.4079092966 |
| 87.84 | 2.44 | 93.33 | 2.86 | 86.36 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.3899122269 |
| 88.98 | 1.14 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.490633891 |
| 90.12 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.3972996086 |
| 90.72 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/18.prim_esc_test.953165236 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.2076378622 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2073658149 |
| /workspace/coverage/default/1.prim_esc_test.3727305516 |
| /workspace/coverage/default/11.prim_esc_test.2073989759 |
| /workspace/coverage/default/14.prim_esc_test.4008478731 |
| /workspace/coverage/default/15.prim_esc_test.2337692582 |
| /workspace/coverage/default/16.prim_esc_test.3525209465 |
| /workspace/coverage/default/17.prim_esc_test.2521753460 |
| /workspace/coverage/default/2.prim_esc_test.1293834669 |
| /workspace/coverage/default/3.prim_esc_test.4076862815 |
| /workspace/coverage/default/4.prim_esc_test.65892653 |
| /workspace/coverage/default/5.prim_esc_test.1659404372 |
| /workspace/coverage/default/7.prim_esc_test.3670139782 |
| /workspace/coverage/default/8.prim_esc_test.3663550836 |
| /workspace/coverage/default/9.prim_esc_test.27383235 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/7.prim_esc_test.3670139782 | Feb 29 12:16:51 PM PST 24 | Feb 29 12:16:52 PM PST 24 | 4727194 ps | ||
| T2 | /workspace/coverage/default/2.prim_esc_test.1293834669 | Feb 29 12:16:59 PM PST 24 | Feb 29 12:17:03 PM PST 24 | 4734879 ps | ||
| T3 | /workspace/coverage/default/0.prim_esc_test.2073658149 | Feb 29 12:16:49 PM PST 24 | Feb 29 12:16:50 PM PST 24 | 4503058 ps | ||
| T4 | /workspace/coverage/default/8.prim_esc_test.3663550836 | Feb 29 12:16:51 PM PST 24 | Feb 29 12:16:52 PM PST 24 | 4907314 ps | ||
| T5 | /workspace/coverage/default/10.prim_esc_test.490633891 | Feb 29 12:16:50 PM PST 24 | Feb 29 12:16:51 PM PST 24 | 4617196 ps | ||
| T11 | /workspace/coverage/default/5.prim_esc_test.1659404372 | Feb 29 12:16:59 PM PST 24 | Feb 29 12:17:03 PM PST 24 | 4567180 ps | ||
| T6 | /workspace/coverage/default/9.prim_esc_test.27383235 | Feb 29 12:16:59 PM PST 24 | Feb 29 12:17:03 PM PST 24 | 4492333 ps | ||
| T16 | /workspace/coverage/default/18.prim_esc_test.953165236 | Feb 29 12:16:52 PM PST 24 | Feb 29 12:16:53 PM PST 24 | 5528704 ps | ||
| T12 | /workspace/coverage/default/6.prim_esc_test.4079092966 | Feb 29 12:16:50 PM PST 24 | Feb 29 12:16:51 PM PST 24 | 4452124 ps | ||
| T17 | /workspace/coverage/default/1.prim_esc_test.3727305516 | Feb 29 12:16:51 PM PST 24 | Feb 29 12:16:51 PM PST 24 | 4744556 ps | ||
| T8 | /workspace/coverage/default/12.prim_esc_test.3899122269 | Feb 29 12:16:50 PM PST 24 | Feb 29 12:16:50 PM PST 24 | 4788769 ps | ||
| T18 | /workspace/coverage/default/11.prim_esc_test.2073989759 | Feb 29 12:16:51 PM PST 24 | Feb 29 12:16:52 PM PST 24 | 5443218 ps | ||
| T14 | /workspace/coverage/default/15.prim_esc_test.2337692582 | Feb 29 12:16:50 PM PST 24 | Feb 29 12:16:51 PM PST 24 | 4628457 ps | ||
| T15 | /workspace/coverage/default/13.prim_esc_test.3972996086 | Feb 29 12:16:51 PM PST 24 | Feb 29 12:16:52 PM PST 24 | 4706947 ps | ||
| T19 | /workspace/coverage/default/17.prim_esc_test.2521753460 | Feb 29 12:16:51 PM PST 24 | Feb 29 12:16:52 PM PST 24 | 5277495 ps | ||
| T9 | /workspace/coverage/default/3.prim_esc_test.4076862815 | Feb 29 12:16:54 PM PST 24 | Feb 29 12:16:54 PM PST 24 | 4667229 ps | ||
| T20 | /workspace/coverage/default/4.prim_esc_test.65892653 | Feb 29 12:16:52 PM PST 24 | Feb 29 12:16:53 PM PST 24 | 4967903 ps | ||
| T13 | /workspace/coverage/default/19.prim_esc_test.2076378622 | Feb 29 12:16:52 PM PST 24 | Feb 29 12:16:53 PM PST 24 | 4755618 ps | ||
| T10 | /workspace/coverage/default/14.prim_esc_test.4008478731 | Feb 29 12:16:54 PM PST 24 | Feb 29 12:16:55 PM PST 24 | 5143792 ps | ||
| T7 | /workspace/coverage/default/16.prim_esc_test.3525209465 | Feb 29 12:16:52 PM PST 24 | Feb 29 12:16:53 PM PST 24 | 5123326 ps |
| Test location | /workspace/coverage/default/6.prim_esc_test.4079092966 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4452124 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:50 PM PST 24 |
| Finished | Feb 29 12:16:51 PM PST 24 |
| Peak memory | 146252 kb |
| Host | smart-b02547a7-f7c0-4708-b5bc-ff0b992fa971 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079092966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4079092966 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3899122269 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4788769 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:50 PM PST 24 |
| Finished | Feb 29 12:16:50 PM PST 24 |
| Peak memory | 146252 kb |
| Host | smart-fec2fdcd-7df1-4e9e-96c7-71cdd5fe0006 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899122269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3899122269 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.490633891 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4617196 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:50 PM PST 24 |
| Finished | Feb 29 12:16:51 PM PST 24 |
| Peak memory | 146428 kb |
| Host | smart-769830b3-ec2b-4fdd-af40-f311f9538bd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490633891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.490633891 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3972996086 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4706947 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:51 PM PST 24 |
| Finished | Feb 29 12:16:52 PM PST 24 |
| Peak memory | 146440 kb |
| Host | smart-5df4b7f1-4b64-4334-aa2d-23e1d4cb3895 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972996086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3972996086 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.953165236 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5528704 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:52 PM PST 24 |
| Finished | Feb 29 12:16:53 PM PST 24 |
| Peak memory | 146328 kb |
| Host | smart-6805a720-adab-4140-b713-5006c3464c03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=953165236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.953165236 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2076378622 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4755618 ps |
| CPU time | 0.39 seconds |
| Started | Feb 29 12:16:52 PM PST 24 |
| Finished | Feb 29 12:16:53 PM PST 24 |
| Peak memory | 146180 kb |
| Host | smart-9d87200d-605a-4322-a81e-d229ce5d5bf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076378622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2076378622 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2073658149 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4503058 ps |
| CPU time | 0.37 seconds |
| Started | Feb 29 12:16:49 PM PST 24 |
| Finished | Feb 29 12:16:50 PM PST 24 |
| Peak memory | 146252 kb |
| Host | smart-bf2b9f6b-b1ba-4ba0-9acf-2fb514131ecf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073658149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2073658149 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3727305516 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4744556 ps |
| CPU time | 0.37 seconds |
| Started | Feb 29 12:16:51 PM PST 24 |
| Finished | Feb 29 12:16:51 PM PST 24 |
| Peak memory | 146296 kb |
| Host | smart-3ead3dc5-2d8d-4b10-94da-1358671333e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727305516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3727305516 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2073989759 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5443218 ps |
| CPU time | 0.37 seconds |
| Started | Feb 29 12:16:51 PM PST 24 |
| Finished | Feb 29 12:16:52 PM PST 24 |
| Peak memory | 146180 kb |
| Host | smart-6a64df58-15be-4f38-b7fa-d12d0e6ced10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073989759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2073989759 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.4008478731 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5143792 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:54 PM PST 24 |
| Finished | Feb 29 12:16:55 PM PST 24 |
| Peak memory | 146280 kb |
| Host | smart-ed6a416c-2be8-4278-91ea-57b73e1b471b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008478731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.4008478731 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2337692582 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4628457 ps |
| CPU time | 0.37 seconds |
| Started | Feb 29 12:16:50 PM PST 24 |
| Finished | Feb 29 12:16:51 PM PST 24 |
| Peak memory | 146196 kb |
| Host | smart-9ebaf4f4-7534-49d8-9a59-86ffc75fc14a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337692582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2337692582 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3525209465 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5123326 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:52 PM PST 24 |
| Finished | Feb 29 12:16:53 PM PST 24 |
| Peak memory | 146260 kb |
| Host | smart-1d8fe7ca-18b1-4043-8718-10b1da87a2b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3525209465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3525209465 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2521753460 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5277495 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:51 PM PST 24 |
| Finished | Feb 29 12:16:52 PM PST 24 |
| Peak memory | 146196 kb |
| Host | smart-65e826cd-f783-4a45-833c-11266f0e0d8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2521753460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2521753460 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1293834669 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4734879 ps |
| CPU time | 0.4 seconds |
| Started | Feb 29 12:16:59 PM PST 24 |
| Finished | Feb 29 12:17:03 PM PST 24 |
| Peak memory | 146252 kb |
| Host | smart-1227c08d-7016-4819-af34-061239919e4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293834669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1293834669 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.4076862815 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4667229 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:54 PM PST 24 |
| Finished | Feb 29 12:16:54 PM PST 24 |
| Peak memory | 146304 kb |
| Host | smart-f03ff8ac-8bc9-4ee1-b9c4-606f56667001 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4076862815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.4076862815 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.65892653 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4967903 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:52 PM PST 24 |
| Finished | Feb 29 12:16:53 PM PST 24 |
| Peak memory | 146344 kb |
| Host | smart-696138f8-a9a3-485e-bea5-0b74332aba62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65892653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.65892653 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1659404372 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4567180 ps |
| CPU time | 0.37 seconds |
| Started | Feb 29 12:16:59 PM PST 24 |
| Finished | Feb 29 12:17:03 PM PST 24 |
| Peak memory | 146440 kb |
| Host | smart-abfa1826-00c1-4565-be4f-5d9d96a1b0f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659404372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1659404372 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3670139782 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4727194 ps |
| CPU time | 0.4 seconds |
| Started | Feb 29 12:16:51 PM PST 24 |
| Finished | Feb 29 12:16:52 PM PST 24 |
| Peak memory | 146368 kb |
| Host | smart-09bc30f6-8dc4-4662-bf2f-93063f84b875 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670139782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3670139782 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3663550836 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4907314 ps |
| CPU time | 0.39 seconds |
| Started | Feb 29 12:16:51 PM PST 24 |
| Finished | Feb 29 12:16:52 PM PST 24 |
| Peak memory | 146440 kb |
| Host | smart-fbc86345-555d-46ae-b381-3e1266c2aabe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3663550836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3663550836 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.27383235 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4492333 ps |
| CPU time | 0.38 seconds |
| Started | Feb 29 12:16:59 PM PST 24 |
| Finished | Feb 29 12:17:03 PM PST 24 |
| Peak memory | 146332 kb |
| Host | smart-0354af97-8a38-419e-98dd-af354f0a3a4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27383235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.27383235 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |