| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 90.17 | 94.29 | 86.36 | 100.00 | 92.86 | 86.05 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.70 | 86.70 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/2.prim_esc_test.2701087145 |
| 89.03 | 2.33 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/6.prim_esc_test.933934135 |
| 90.17 | 1.14 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.1800046775 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2188228885 |
| /workspace/coverage/default/10.prim_esc_test.1854006218 |
| /workspace/coverage/default/11.prim_esc_test.1161058617 |
| /workspace/coverage/default/12.prim_esc_test.3297522921 |
| /workspace/coverage/default/13.prim_esc_test.1261763521 |
| /workspace/coverage/default/14.prim_esc_test.849827493 |
| /workspace/coverage/default/15.prim_esc_test.879286305 |
| /workspace/coverage/default/16.prim_esc_test.3786015730 |
| /workspace/coverage/default/17.prim_esc_test.916649615 |
| /workspace/coverage/default/18.prim_esc_test.3675121174 |
| /workspace/coverage/default/19.prim_esc_test.3402891998 |
| /workspace/coverage/default/3.prim_esc_test.1570514340 |
| /workspace/coverage/default/4.prim_esc_test.1324122861 |
| /workspace/coverage/default/5.prim_esc_test.803218733 |
| /workspace/coverage/default/7.prim_esc_test.1452121270 |
| /workspace/coverage/default/8.prim_esc_test.4012013063 |
| /workspace/coverage/default/9.prim_esc_test.1226685770 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.prim_esc_test.933934135 | Mar 03 12:33:02 PM PST 24 | Mar 03 12:33:03 PM PST 24 | 4509589 ps | ||
| T2 | /workspace/coverage/default/5.prim_esc_test.803218733 | Mar 03 12:33:39 PM PST 24 | Mar 03 12:33:40 PM PST 24 | 4768737 ps | ||
| T3 | /workspace/coverage/default/17.prim_esc_test.916649615 | Mar 03 12:33:35 PM PST 24 | Mar 03 12:33:35 PM PST 24 | 4833676 ps | ||
| T4 | /workspace/coverage/default/15.prim_esc_test.879286305 | Mar 03 12:33:15 PM PST 24 | Mar 03 12:33:15 PM PST 24 | 4711691 ps | ||
| T11 | /workspace/coverage/default/7.prim_esc_test.1452121270 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 5033775 ps | ||
| T6 | /workspace/coverage/default/3.prim_esc_test.1570514340 | Mar 03 12:33:17 PM PST 24 | Mar 03 12:33:18 PM PST 24 | 4758696 ps | ||
| T12 | /workspace/coverage/default/14.prim_esc_test.849827493 | Mar 03 12:33:44 PM PST 24 | Mar 03 12:33:44 PM PST 24 | 5308570 ps | ||
| T7 | /workspace/coverage/default/2.prim_esc_test.2701087145 | Mar 03 12:33:15 PM PST 24 | Mar 03 12:33:16 PM PST 24 | 4735033 ps | ||
| T10 | /workspace/coverage/default/1.prim_esc_test.1800046775 | Mar 03 12:33:04 PM PST 24 | Mar 03 12:33:05 PM PST 24 | 5118193 ps | ||
| T13 | /workspace/coverage/default/11.prim_esc_test.1161058617 | Mar 03 12:33:26 PM PST 24 | Mar 03 12:33:26 PM PST 24 | 4612478 ps | ||
| T8 | /workspace/coverage/default/16.prim_esc_test.3786015730 | Mar 03 12:33:30 PM PST 24 | Mar 03 12:33:31 PM PST 24 | 4638304 ps | ||
| T14 | /workspace/coverage/default/4.prim_esc_test.1324122861 | Mar 03 12:33:11 PM PST 24 | Mar 03 12:33:11 PM PST 24 | 5087129 ps | ||
| T5 | /workspace/coverage/default/19.prim_esc_test.3402891998 | Mar 03 12:33:35 PM PST 24 | Mar 03 12:33:36 PM PST 24 | 4620549 ps | ||
| T15 | /workspace/coverage/default/10.prim_esc_test.1854006218 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 4169364 ps | ||
| T16 | /workspace/coverage/default/0.prim_esc_test.2188228885 | Mar 03 12:33:08 PM PST 24 | Mar 03 12:33:08 PM PST 24 | 4655324 ps | ||
| T17 | /workspace/coverage/default/8.prim_esc_test.4012013063 | Mar 03 12:33:08 PM PST 24 | Mar 03 12:33:09 PM PST 24 | 4892948 ps | ||
| T18 | /workspace/coverage/default/13.prim_esc_test.1261763521 | Mar 03 12:33:07 PM PST 24 | Mar 03 12:33:08 PM PST 24 | 5035052 ps | ||
| T9 | /workspace/coverage/default/9.prim_esc_test.1226685770 | Mar 03 12:33:22 PM PST 24 | Mar 03 12:33:23 PM PST 24 | 4812671 ps | ||
| T19 | /workspace/coverage/default/18.prim_esc_test.3675121174 | Mar 03 12:33:18 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 4753475 ps | ||
| T20 | /workspace/coverage/default/12.prim_esc_test.3297522921 | Mar 03 12:33:03 PM PST 24 | Mar 03 12:33:04 PM PST 24 | 4579006 ps |
| Test location | /workspace/coverage/default/2.prim_esc_test.2701087145 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4735033 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:15 PM PST 24 |
| Finished | Mar 03 12:33:16 PM PST 24 |
| Peak memory | 146328 kb |
| Host | smart-850a095b-5fa4-43d9-b1ad-6160cba5a20c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2701087145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2701087145 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.933934135 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4509589 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:33:02 PM PST 24 |
| Finished | Mar 03 12:33:03 PM PST 24 |
| Peak memory | 146332 kb |
| Host | smart-149cdd4b-378a-4e29-b6c4-d3a9082fc496 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933934135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.933934135 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1800046775 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5118193 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:04 PM PST 24 |
| Finished | Mar 03 12:33:05 PM PST 24 |
| Peak memory | 146268 kb |
| Host | smart-4ebb6864-152a-47be-8ac7-7c9a95833966 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800046775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1800046775 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2188228885 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4655324 ps |
| CPU time | 0.36 seconds |
| Started | Mar 03 12:33:08 PM PST 24 |
| Finished | Mar 03 12:33:08 PM PST 24 |
| Peak memory | 146268 kb |
| Host | smart-317d8a5a-5025-4a5c-8f83-ca1dbaeae6cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188228885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2188228885 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1854006218 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4169364 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 146324 kb |
| Host | smart-36ee757f-7801-4def-b5c7-945dd6005d05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854006218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1854006218 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1161058617 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4612478 ps |
| CPU time | 0.41 seconds |
| Started | Mar 03 12:33:26 PM PST 24 |
| Finished | Mar 03 12:33:26 PM PST 24 |
| Peak memory | 146184 kb |
| Host | smart-27efada1-5875-430a-955c-0ef9e5048216 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1161058617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1161058617 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3297522921 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4579006 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:33:03 PM PST 24 |
| Finished | Mar 03 12:33:04 PM PST 24 |
| Peak memory | 146124 kb |
| Host | smart-554a563a-6a8a-48f6-9dfc-325634ceb0f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3297522921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3297522921 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1261763521 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5035052 ps |
| CPU time | 0.35 seconds |
| Started | Mar 03 12:33:07 PM PST 24 |
| Finished | Mar 03 12:33:08 PM PST 24 |
| Peak memory | 146228 kb |
| Host | smart-93cdc7ac-2375-41fd-9c71-574f1f65c456 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1261763521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1261763521 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.849827493 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5308570 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:44 PM PST 24 |
| Finished | Mar 03 12:33:44 PM PST 24 |
| Peak memory | 146416 kb |
| Host | smart-01240734-fe6a-4492-9750-8c4417ec8dca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=849827493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.849827493 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.879286305 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4711691 ps |
| CPU time | 0.35 seconds |
| Started | Mar 03 12:33:15 PM PST 24 |
| Finished | Mar 03 12:33:15 PM PST 24 |
| Peak memory | 146036 kb |
| Host | smart-1eda8c04-b740-4e13-b6db-a049a2401f31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879286305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.879286305 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3786015730 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4638304 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:30 PM PST 24 |
| Finished | Mar 03 12:33:31 PM PST 24 |
| Peak memory | 146200 kb |
| Host | smart-b0bbce18-647b-4053-9a24-113b215f781a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3786015730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3786015730 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.916649615 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4833676 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:33:35 PM PST 24 |
| Finished | Mar 03 12:33:35 PM PST 24 |
| Peak memory | 146196 kb |
| Host | smart-f1456130-27ff-4524-8ca8-1f479a28bdc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916649615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.916649615 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3675121174 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4753475 ps |
| CPU time | 0.38 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 146176 kb |
| Host | smart-482a904a-4419-4fa4-bb20-ae81fbab0ccd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3675121174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3675121174 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3402891998 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4620549 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:33:35 PM PST 24 |
| Finished | Mar 03 12:33:36 PM PST 24 |
| Peak memory | 146268 kb |
| Host | smart-2f3eee33-a581-4b42-b7ee-b47a1c84b117 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3402891998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3402891998 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1570514340 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4758696 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:18 PM PST 24 |
| Peak memory | 146328 kb |
| Host | smart-290b9213-8ada-46dd-9d34-6f71075f5e38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570514340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1570514340 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1324122861 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5087129 ps |
| CPU time | 0.36 seconds |
| Started | Mar 03 12:33:11 PM PST 24 |
| Finished | Mar 03 12:33:11 PM PST 24 |
| Peak memory | 146264 kb |
| Host | smart-7b4b8b0d-efbb-4838-912c-24bf8d0ba9f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324122861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1324122861 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.803218733 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4768737 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:33:39 PM PST 24 |
| Finished | Mar 03 12:33:40 PM PST 24 |
| Peak memory | 146276 kb |
| Host | smart-888dcd65-2b7a-4f8a-8a81-868c503c3bb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803218733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.803218733 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1452121270 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5033775 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 146268 kb |
| Host | smart-adbc4845-058f-4ff9-9924-a9e5a050be3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452121270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1452121270 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.4012013063 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4892948 ps |
| CPU time | 0.39 seconds |
| Started | Mar 03 12:33:08 PM PST 24 |
| Finished | Mar 03 12:33:09 PM PST 24 |
| Peak memory | 146324 kb |
| Host | smart-e6bf06cd-624b-4641-9cca-643ff007ddfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012013063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.4012013063 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1226685770 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4812671 ps |
| CPU time | 0.37 seconds |
| Started | Mar 03 12:33:22 PM PST 24 |
| Finished | Mar 03 12:33:23 PM PST 24 |
| Peak memory | 146324 kb |
| Host | smart-2bc94080-2565-4687-9070-a8014c7fc547 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226685770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1226685770 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |