Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.70 86.70 92.38 92.38 86.36 86.36 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/10.prim_esc_test.1299164616
89.03 2.33 93.33 0.95 86.36 0.00 100.00 0.00 89.29 10.71 83.72 2.33 81.48 0.00 /workspace/coverage/default/14.prim_esc_test.2228700941
90.17 1.14 94.29 0.95 86.36 0.00 100.00 0.00 92.86 3.57 86.05 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.457097494
91.31 1.14 95.24 0.95 86.36 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/1.prim_esc_test.2123900935

Tests that do not contribute to grading

Name
/workspace/coverage/default/11.prim_esc_test.1633952788
/workspace/coverage/default/12.prim_esc_test.1270710688
/workspace/coverage/default/13.prim_esc_test.3342840043
/workspace/coverage/default/15.prim_esc_test.1027044580
/workspace/coverage/default/16.prim_esc_test.140666300
/workspace/coverage/default/17.prim_esc_test.3266051665
/workspace/coverage/default/18.prim_esc_test.1065232989
/workspace/coverage/default/19.prim_esc_test.2599670951
/workspace/coverage/default/2.prim_esc_test.3262320181
/workspace/coverage/default/3.prim_esc_test.1812426210
/workspace/coverage/default/4.prim_esc_test.2816203643
/workspace/coverage/default/5.prim_esc_test.3066074640
/workspace/coverage/default/6.prim_esc_test.2626220316
/workspace/coverage/default/7.prim_esc_test.4139606688
/workspace/coverage/default/8.prim_esc_test.3443054121
/workspace/coverage/default/9.prim_esc_test.505310508



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.prim_esc_test.1812426210 Mar 05 12:17:10 PM PST 24 Mar 05 12:17:11 PM PST 24 4758742 ps
T2 /workspace/coverage/default/6.prim_esc_test.2626220316 Mar 05 12:17:11 PM PST 24 Mar 05 12:17:12 PM PST 24 4710881 ps
T3 /workspace/coverage/default/11.prim_esc_test.1633952788 Mar 05 12:17:22 PM PST 24 Mar 05 12:17:23 PM PST 24 4844303 ps
T6 /workspace/coverage/default/8.prim_esc_test.3443054121 Mar 05 12:17:06 PM PST 24 Mar 05 12:17:07 PM PST 24 4691411 ps
T4 /workspace/coverage/default/1.prim_esc_test.2123900935 Mar 05 12:17:14 PM PST 24 Mar 05 12:17:15 PM PST 24 4716186 ps
T5 /workspace/coverage/default/10.prim_esc_test.1299164616 Mar 05 12:17:22 PM PST 24 Mar 05 12:17:23 PM PST 24 4257062 ps
T13 /workspace/coverage/default/16.prim_esc_test.140666300 Mar 05 12:22:10 PM PST 24 Mar 05 12:22:10 PM PST 24 4326745 ps
T15 /workspace/coverage/default/12.prim_esc_test.1270710688 Mar 05 12:17:22 PM PST 24 Mar 05 12:17:23 PM PST 24 4704144 ps
T12 /workspace/coverage/default/15.prim_esc_test.1027044580 Mar 05 12:22:27 PM PST 24 Mar 05 12:22:27 PM PST 24 4941529 ps
T7 /workspace/coverage/default/14.prim_esc_test.2228700941 Mar 05 12:17:15 PM PST 24 Mar 05 12:17:15 PM PST 24 4678720 ps
T11 /workspace/coverage/default/7.prim_esc_test.4139606688 Mar 05 12:17:22 PM PST 24 Mar 05 12:17:23 PM PST 24 5288315 ps
T9 /workspace/coverage/default/19.prim_esc_test.2599670951 Mar 05 12:17:30 PM PST 24 Mar 05 12:17:31 PM PST 24 4771643 ps
T14 /workspace/coverage/default/18.prim_esc_test.1065232989 Mar 05 12:22:10 PM PST 24 Mar 05 12:22:10 PM PST 24 5554339 ps
T16 /workspace/coverage/default/17.prim_esc_test.3266051665 Mar 05 12:20:13 PM PST 24 Mar 05 12:20:14 PM PST 24 4793339 ps
T8 /workspace/coverage/default/9.prim_esc_test.505310508 Mar 05 12:17:10 PM PST 24 Mar 05 12:17:11 PM PST 24 4537539 ps
T10 /workspace/coverage/default/5.prim_esc_test.3066074640 Mar 05 12:17:11 PM PST 24 Mar 05 12:17:12 PM PST 24 4849663 ps
T17 /workspace/coverage/default/0.prim_esc_test.457097494 Mar 05 12:17:10 PM PST 24 Mar 05 12:17:10 PM PST 24 5351215 ps
T18 /workspace/coverage/default/4.prim_esc_test.2816203643 Mar 05 12:17:07 PM PST 24 Mar 05 12:17:07 PM PST 24 4647274 ps
T19 /workspace/coverage/default/13.prim_esc_test.3342840043 Mar 05 12:17:28 PM PST 24 Mar 05 12:17:28 PM PST 24 5163917 ps
T20 /workspace/coverage/default/2.prim_esc_test.3262320181 Mar 05 12:17:10 PM PST 24 Mar 05 12:17:11 PM PST 24 5271268 ps

Test location /workspace/coverage/default/10.prim_esc_test.1299164616
Short name T5
Test name
Test status
Simulation time 4257062 ps
CPU time 0.41 seconds
Started Mar 05 12:17:22 PM PST 24
Finished Mar 05 12:17:23 PM PST 24
Peak memory 146056 kb
Host smart-20b0415c-6847-4f69-9bd0-d46f7c17d7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299164616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1299164616
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.2228700941
Short name T7
Test name
Test status
Simulation time 4678720 ps
CPU time 0.4 seconds
Started Mar 05 12:17:15 PM PST 24
Finished Mar 05 12:17:15 PM PST 24
Peak memory 146268 kb
Host smart-fe784111-9d0d-401a-be63-547fabdec8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228700941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2228700941
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.457097494
Short name T17
Test name
Test status
Simulation time 5351215 ps
CPU time 0.38 seconds
Started Mar 05 12:17:10 PM PST 24
Finished Mar 05 12:17:10 PM PST 24
Peak memory 146324 kb
Host smart-c559c921-0692-49b5-9216-17804d459582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457097494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.457097494
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.2123900935
Short name T4
Test name
Test status
Simulation time 4716186 ps
CPU time 0.38 seconds
Started Mar 05 12:17:14 PM PST 24
Finished Mar 05 12:17:15 PM PST 24
Peak memory 146296 kb
Host smart-b220b2c7-447e-41fe-a070-21536bde70a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123900935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2123900935
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1633952788
Short name T3
Test name
Test status
Simulation time 4844303 ps
CPU time 0.38 seconds
Started Mar 05 12:17:22 PM PST 24
Finished Mar 05 12:17:23 PM PST 24
Peak memory 146308 kb
Host smart-3a464a05-39dd-4e74-b1f7-b4c96279483e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633952788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1633952788
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.1270710688
Short name T15
Test name
Test status
Simulation time 4704144 ps
CPU time 0.4 seconds
Started Mar 05 12:17:22 PM PST 24
Finished Mar 05 12:17:23 PM PST 24
Peak memory 146272 kb
Host smart-4540d01a-ed43-4abd-9615-b4fbb848d6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270710688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1270710688
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.3342840043
Short name T19
Test name
Test status
Simulation time 5163917 ps
CPU time 0.37 seconds
Started Mar 05 12:17:28 PM PST 24
Finished Mar 05 12:17:28 PM PST 24
Peak memory 146308 kb
Host smart-07d086d9-5e35-42ef-b4c4-10df273071f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342840043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3342840043
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.1027044580
Short name T12
Test name
Test status
Simulation time 4941529 ps
CPU time 0.37 seconds
Started Mar 05 12:22:27 PM PST 24
Finished Mar 05 12:22:27 PM PST 24
Peak memory 146120 kb
Host smart-5d6a177f-ce59-43f5-b466-6243b91dcc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027044580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1027044580
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.140666300
Short name T13
Test name
Test status
Simulation time 4326745 ps
CPU time 0.4 seconds
Started Mar 05 12:22:10 PM PST 24
Finished Mar 05 12:22:10 PM PST 24
Peak memory 145172 kb
Host smart-783718b0-fb19-4ff0-b8d3-122f938ac390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140666300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.140666300
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.3266051665
Short name T16
Test name
Test status
Simulation time 4793339 ps
CPU time 0.39 seconds
Started Mar 05 12:20:13 PM PST 24
Finished Mar 05 12:20:14 PM PST 24
Peak memory 146348 kb
Host smart-2c988e9e-9664-4713-8b18-c9d668228af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266051665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3266051665
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.1065232989
Short name T14
Test name
Test status
Simulation time 5554339 ps
CPU time 0.4 seconds
Started Mar 05 12:22:10 PM PST 24
Finished Mar 05 12:22:10 PM PST 24
Peak memory 144916 kb
Host smart-48dff77b-b174-4147-a638-74aa5efe318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065232989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1065232989
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2599670951
Short name T9
Test name
Test status
Simulation time 4771643 ps
CPU time 0.38 seconds
Started Mar 05 12:17:30 PM PST 24
Finished Mar 05 12:17:31 PM PST 24
Peak memory 146364 kb
Host smart-c01099e5-1c26-46e2-a720-30260d8e2353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599670951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2599670951
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.3262320181
Short name T20
Test name
Test status
Simulation time 5271268 ps
CPU time 0.4 seconds
Started Mar 05 12:17:10 PM PST 24
Finished Mar 05 12:17:11 PM PST 24
Peak memory 146296 kb
Host smart-9f68939b-16b3-4d38-aa67-f1c5b8c6b4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262320181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3262320181
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.1812426210
Short name T1
Test name
Test status
Simulation time 4758742 ps
CPU time 0.38 seconds
Started Mar 05 12:17:10 PM PST 24
Finished Mar 05 12:17:11 PM PST 24
Peak memory 146296 kb
Host smart-e2432a35-39f6-4f52-9447-9c44b7f33316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812426210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1812426210
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.2816203643
Short name T18
Test name
Test status
Simulation time 4647274 ps
CPU time 0.39 seconds
Started Mar 05 12:17:07 PM PST 24
Finished Mar 05 12:17:07 PM PST 24
Peak memory 146348 kb
Host smart-28e8f9af-ed43-416f-9f0b-c6b5f6f2e61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816203643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2816203643
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.3066074640
Short name T10
Test name
Test status
Simulation time 4849663 ps
CPU time 0.47 seconds
Started Mar 05 12:17:11 PM PST 24
Finished Mar 05 12:17:12 PM PST 24
Peak memory 144968 kb
Host smart-20414251-4b09-4254-a925-953446ce2d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066074640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3066074640
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2626220316
Short name T2
Test name
Test status
Simulation time 4710881 ps
CPU time 0.47 seconds
Started Mar 05 12:17:11 PM PST 24
Finished Mar 05 12:17:12 PM PST 24
Peak memory 144620 kb
Host smart-a8aba750-c183-4eff-b66d-337726fe269b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626220316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2626220316
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.4139606688
Short name T11
Test name
Test status
Simulation time 5288315 ps
CPU time 0.41 seconds
Started Mar 05 12:17:22 PM PST 24
Finished Mar 05 12:17:23 PM PST 24
Peak memory 146068 kb
Host smart-9d1290d5-f327-40bc-9dac-86588551c5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139606688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4139606688
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.3443054121
Short name T6
Test name
Test status
Simulation time 4691411 ps
CPU time 0.4 seconds
Started Mar 05 12:17:06 PM PST 24
Finished Mar 05 12:17:07 PM PST 24
Peak memory 146348 kb
Host smart-3fea9e2a-8c61-47b1-9860-519221971b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443054121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3443054121
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.505310508
Short name T8
Test name
Test status
Simulation time 4537539 ps
CPU time 0.39 seconds
Started Mar 05 12:17:10 PM PST 24
Finished Mar 05 12:17:11 PM PST 24
Peak memory 146288 kb
Host smart-df889aec-bb17-44ff-8387-c09916b80bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505310508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.505310508
Directory /workspace/9.prim_esc_test/latest
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