| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.72 | 85.72 | 92.38 | 92.38 | 84.09 | 84.09 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/4.prim_esc_test.1413556241 |
| 88.44 | 2.71 | 93.33 | 0.95 | 86.36 | 2.27 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/3.prim_esc_test.3329821372 |
| 89.58 | 1.14 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.297075121 |
| 90.72 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.2712687416 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1374405190 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3939809003 |
| /workspace/coverage/default/11.prim_esc_test.3807208484 |
| /workspace/coverage/default/12.prim_esc_test.1246931960 |
| /workspace/coverage/default/13.prim_esc_test.1446842180 |
| /workspace/coverage/default/15.prim_esc_test.3133589369 |
| /workspace/coverage/default/16.prim_esc_test.2132151087 |
| /workspace/coverage/default/17.prim_esc_test.1132108139 |
| /workspace/coverage/default/18.prim_esc_test.1817576240 |
| /workspace/coverage/default/19.prim_esc_test.2272802543 |
| /workspace/coverage/default/2.prim_esc_test.1254436536 |
| /workspace/coverage/default/5.prim_esc_test.1912356016 |
| /workspace/coverage/default/6.prim_esc_test.1630300002 |
| /workspace/coverage/default/7.prim_esc_test.84604048 |
| /workspace/coverage/default/8.prim_esc_test.3067671997 |
| /workspace/coverage/default/9.prim_esc_test.2944765406 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.prim_esc_test.1630300002 | Mar 07 12:18:51 PM PST 24 | Mar 07 12:18:52 PM PST 24 | 4962812 ps | ||
| T2 | /workspace/coverage/default/7.prim_esc_test.84604048 | Mar 07 12:18:44 PM PST 24 | Mar 07 12:18:45 PM PST 24 | 5194097 ps | ||
| T3 | /workspace/coverage/default/8.prim_esc_test.3067671997 | Mar 07 12:18:52 PM PST 24 | Mar 07 12:18:53 PM PST 24 | 4479249 ps | ||
| T4 | /workspace/coverage/default/11.prim_esc_test.3807208484 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:19:11 PM PST 24 | 4758649 ps | ||
| T14 | /workspace/coverage/default/18.prim_esc_test.1817576240 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:19:11 PM PST 24 | 4855804 ps | ||
| T5 | /workspace/coverage/default/15.prim_esc_test.3133589369 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:19:12 PM PST 24 | 5344591 ps | ||
| T6 | /workspace/coverage/default/19.prim_esc_test.2272802543 | Mar 07 12:19:14 PM PST 24 | Mar 07 12:19:15 PM PST 24 | 4663016 ps | ||
| T7 | /workspace/coverage/default/4.prim_esc_test.1413556241 | Mar 07 12:18:51 PM PST 24 | Mar 07 12:18:52 PM PST 24 | 5014048 ps | ||
| T16 | /workspace/coverage/default/12.prim_esc_test.1246931960 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:19:11 PM PST 24 | 4787787 ps | ||
| T15 | /workspace/coverage/default/5.prim_esc_test.1912356016 | Mar 07 12:18:45 PM PST 24 | Mar 07 12:18:46 PM PST 24 | 5161828 ps | ||
| T17 | /workspace/coverage/default/1.prim_esc_test.297075121 | Mar 07 12:18:45 PM PST 24 | Mar 07 12:18:46 PM PST 24 | 4966929 ps | ||
| T8 | /workspace/coverage/default/13.prim_esc_test.1446842180 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:19:13 PM PST 24 | 5137059 ps | ||
| T9 | /workspace/coverage/default/14.prim_esc_test.2712687416 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:19:12 PM PST 24 | 4767890 ps | ||
| T18 | /workspace/coverage/default/0.prim_esc_test.3939809003 | Mar 07 12:18:52 PM PST 24 | Mar 07 12:18:53 PM PST 24 | 4540208 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.1374405190 | Mar 07 12:21:19 PM PST 24 | Mar 07 12:21:20 PM PST 24 | 4808617 ps | ||
| T19 | /workspace/coverage/default/16.prim_esc_test.2132151087 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:19:12 PM PST 24 | 5137199 ps | ||
| T11 | /workspace/coverage/default/3.prim_esc_test.3329821372 | Mar 07 12:18:52 PM PST 24 | Mar 07 12:18:53 PM PST 24 | 4694689 ps | ||
| T12 | /workspace/coverage/default/2.prim_esc_test.1254436536 | Mar 07 12:18:54 PM PST 24 | Mar 07 12:18:55 PM PST 24 | 5592471 ps | ||
| T20 | /workspace/coverage/default/9.prim_esc_test.2944765406 | Mar 07 12:18:54 PM PST 24 | Mar 07 12:18:55 PM PST 24 | 4254055 ps | ||
| T13 | /workspace/coverage/default/17.prim_esc_test.1132108139 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:19:12 PM PST 24 | 5194911 ps |
| Test location | /workspace/coverage/default/4.prim_esc_test.1413556241 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5014048 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:18:51 PM PST 24 |
| Finished | Mar 07 12:18:52 PM PST 24 |
| Peak memory | 146284 kb |
| Host | smart-4f9a22b2-a306-4a73-bce4-6c59abcff4a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413556241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1413556241 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3329821372 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4694689 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:18:52 PM PST 24 |
| Finished | Mar 07 12:18:53 PM PST 24 |
| Peak memory | 146316 kb |
| Host | smart-d79f5246-9ce8-41dc-9ea9-ba1392ae85b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329821372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3329821372 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.297075121 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4966929 ps |
| CPU time | 0.37 seconds |
| Started | Mar 07 12:18:45 PM PST 24 |
| Finished | Mar 07 12:18:46 PM PST 24 |
| Peak memory | 146292 kb |
| Host | smart-93b2b61d-be16-49fd-9aab-c1f7a0371247 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=297075121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.297075121 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2712687416 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4767890 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:19:12 PM PST 24 |
| Peak memory | 146320 kb |
| Host | smart-84089374-49cc-4c82-b8e6-f4ec6c0974d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2712687416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2712687416 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1374405190 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4808617 ps |
| CPU time | 0.37 seconds |
| Started | Mar 07 12:21:19 PM PST 24 |
| Finished | Mar 07 12:21:20 PM PST 24 |
| Peak memory | 145992 kb |
| Host | smart-81baddc8-1850-404c-bd67-a9bdb1044541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1374405190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1374405190 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3939809003 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4540208 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:18:52 PM PST 24 |
| Finished | Mar 07 12:18:53 PM PST 24 |
| Peak memory | 146316 kb |
| Host | smart-d2e80682-360a-4ef7-89bd-cafabdbb4ed3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3939809003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3939809003 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3807208484 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4758649 ps |
| CPU time | 0.37 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:19:11 PM PST 24 |
| Peak memory | 146432 kb |
| Host | smart-980f2aae-6db2-4c4c-b435-a30d5834e759 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807208484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3807208484 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1246931960 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4787787 ps |
| CPU time | 0.37 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:19:11 PM PST 24 |
| Peak memory | 146248 kb |
| Host | smart-146ae205-c569-42ee-a277-5ee354ee8aba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246931960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1246931960 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1446842180 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5137059 ps |
| CPU time | 0.41 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:19:13 PM PST 24 |
| Peak memory | 146328 kb |
| Host | smart-841c7b47-e2fb-4946-90bf-b6d2c964e0ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1446842180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1446842180 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3133589369 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5344591 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:19:12 PM PST 24 |
| Peak memory | 146180 kb |
| Host | smart-4b7352e4-e1b0-4c6a-a4c7-3d1debf7aa1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3133589369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3133589369 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2132151087 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5137199 ps |
| CPU time | 0.4 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:19:12 PM PST 24 |
| Peak memory | 146284 kb |
| Host | smart-7a6ec151-fefa-4f97-8e27-2ca3460fe005 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132151087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2132151087 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1132108139 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5194911 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:19:12 PM PST 24 |
| Peak memory | 146284 kb |
| Host | smart-0ccf8c74-c886-483c-bced-d4d0b95e7c00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132108139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1132108139 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1817576240 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4855804 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:19:11 PM PST 24 |
| Peak memory | 146284 kb |
| Host | smart-90559cbd-c641-4f18-8938-9eb195682ac2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1817576240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1817576240 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2272802543 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4663016 ps |
| CPU time | 0.37 seconds |
| Started | Mar 07 12:19:14 PM PST 24 |
| Finished | Mar 07 12:19:15 PM PST 24 |
| Peak memory | 146224 kb |
| Host | smart-a04fe990-7e83-47ef-b643-4a9d6a9d762f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272802543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2272802543 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1254436536 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5592471 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:18:54 PM PST 24 |
| Finished | Mar 07 12:18:55 PM PST 24 |
| Peak memory | 146348 kb |
| Host | smart-f9be264c-b8d9-41c3-bba8-80d307fa465d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254436536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1254436536 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1912356016 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5161828 ps |
| CPU time | 0.37 seconds |
| Started | Mar 07 12:18:45 PM PST 24 |
| Finished | Mar 07 12:18:46 PM PST 24 |
| Peak memory | 146292 kb |
| Host | smart-2a2a53b9-7195-4f3c-8d37-3830c587ae3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1912356016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1912356016 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1630300002 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4962812 ps |
| CPU time | 0.38 seconds |
| Started | Mar 07 12:18:51 PM PST 24 |
| Finished | Mar 07 12:18:52 PM PST 24 |
| Peak memory | 146280 kb |
| Host | smart-b118e7db-0c33-418f-9e78-5d3ed5875337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630300002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1630300002 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.84604048 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5194097 ps |
| CPU time | 0.37 seconds |
| Started | Mar 07 12:18:44 PM PST 24 |
| Finished | Mar 07 12:18:45 PM PST 24 |
| Peak memory | 146292 kb |
| Host | smart-d7e486f4-14eb-43b3-8414-0f247dc8c561 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84604048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.84604048 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3067671997 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4479249 ps |
| CPU time | 0.37 seconds |
| Started | Mar 07 12:18:52 PM PST 24 |
| Finished | Mar 07 12:18:53 PM PST 24 |
| Peak memory | 146316 kb |
| Host | smart-9d637cc5-2f47-467b-8802-5d45e2f49e3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067671997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3067671997 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2944765406 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4254055 ps |
| CPU time | 0.39 seconds |
| Started | Mar 07 12:18:54 PM PST 24 |
| Finished | Mar 07 12:18:55 PM PST 24 |
| Peak memory | 146348 kb |
| Host | smart-13954c24-6ec0-428e-9145-61cf7ea115cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2944765406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2944765406 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |