| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.72 | 85.72 | 92.38 | 92.38 | 84.09 | 84.09 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/16.prim_esc_test.2718380639 |
| 87.46 | 1.74 | 93.33 | 0.95 | 84.09 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/3.prim_esc_test.2437559141 |
| 88.98 | 1.52 | 94.29 | 0.95 | 86.36 | 2.27 | 100.00 | 0.00 | 85.71 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.32553162 |
| 90.12 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.755956314 |
| 90.72 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.1996722276 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/2.prim_esc_test.33393049 |
| Name |
|---|
| /workspace/coverage/default/10.prim_esc_test.3112364565 |
| /workspace/coverage/default/11.prim_esc_test.2011517347 |
| /workspace/coverage/default/12.prim_esc_test.2117682372 |
| /workspace/coverage/default/13.prim_esc_test.461671085 |
| /workspace/coverage/default/14.prim_esc_test.1826659794 |
| /workspace/coverage/default/17.prim_esc_test.4020801805 |
| /workspace/coverage/default/18.prim_esc_test.1422507255 |
| /workspace/coverage/default/19.prim_esc_test.2686015092 |
| /workspace/coverage/default/4.prim_esc_test.3196516181 |
| /workspace/coverage/default/5.prim_esc_test.1482257233 |
| /workspace/coverage/default/6.prim_esc_test.2162708715 |
| /workspace/coverage/default/7.prim_esc_test.4067735477 |
| /workspace/coverage/default/8.prim_esc_test.3350480602 |
| /workspace/coverage/default/9.prim_esc_test.4039340425 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_esc_test.1422507255 | Mar 10 12:23:58 PM PDT 24 | Mar 10 12:23:59 PM PDT 24 | 4384737 ps | ||
| T2 | /workspace/coverage/default/16.prim_esc_test.2718380639 | Mar 10 12:23:02 PM PDT 24 | Mar 10 12:23:03 PM PDT 24 | 4832279 ps | ||
| T3 | /workspace/coverage/default/8.prim_esc_test.3350480602 | Mar 10 12:17:58 PM PDT 24 | Mar 10 12:17:59 PM PDT 24 | 4955109 ps | ||
| T7 | /workspace/coverage/default/1.prim_esc_test.755956314 | Mar 10 12:19:07 PM PDT 24 | Mar 10 12:19:08 PM PDT 24 | 4989884 ps | ||
| T4 | /workspace/coverage/default/15.prim_esc_test.32553162 | Mar 10 12:17:31 PM PDT 24 | Mar 10 12:17:32 PM PDT 24 | 4593611 ps | ||
| T5 | /workspace/coverage/default/13.prim_esc_test.461671085 | Mar 10 12:17:31 PM PDT 24 | Mar 10 12:17:32 PM PDT 24 | 5012129 ps | ||
| T6 | /workspace/coverage/default/19.prim_esc_test.2686015092 | Mar 10 12:23:03 PM PDT 24 | Mar 10 12:23:04 PM PDT 24 | 4441010 ps | ||
| T11 | /workspace/coverage/default/3.prim_esc_test.2437559141 | Mar 10 12:19:37 PM PDT 24 | Mar 10 12:19:38 PM PDT 24 | 4369645 ps | ||
| T13 | /workspace/coverage/default/10.prim_esc_test.3112364565 | Mar 10 12:22:36 PM PDT 24 | Mar 10 12:22:37 PM PDT 24 | 4888399 ps | ||
| T14 | /workspace/coverage/default/7.prim_esc_test.4067735477 | Mar 10 12:17:32 PM PDT 24 | Mar 10 12:17:33 PM PDT 24 | 4429604 ps | ||
| T16 | /workspace/coverage/default/11.prim_esc_test.2011517347 | Mar 10 12:17:48 PM PDT 24 | Mar 10 12:17:48 PM PDT 24 | 4866802 ps | ||
| T8 | /workspace/coverage/default/9.prim_esc_test.4039340425 | Mar 10 12:18:57 PM PDT 24 | Mar 10 12:18:58 PM PDT 24 | 4550789 ps | ||
| T10 | /workspace/coverage/default/6.prim_esc_test.2162708715 | Mar 10 12:19:55 PM PDT 24 | Mar 10 12:19:55 PM PDT 24 | 5007058 ps | ||
| T17 | /workspace/coverage/default/5.prim_esc_test.1482257233 | Mar 10 12:17:23 PM PDT 24 | Mar 10 12:17:24 PM PDT 24 | 4791512 ps | ||
| T15 | /workspace/coverage/default/2.prim_esc_test.33393049 | Mar 10 12:23:03 PM PDT 24 | Mar 10 12:23:04 PM PDT 24 | 4990598 ps | ||
| T9 | /workspace/coverage/default/12.prim_esc_test.2117682372 | Mar 10 12:17:24 PM PDT 24 | Mar 10 12:17:24 PM PDT 24 | 4883914 ps | ||
| T18 | /workspace/coverage/default/4.prim_esc_test.3196516181 | Mar 10 12:19:07 PM PDT 24 | Mar 10 12:19:07 PM PDT 24 | 5036279 ps | ||
| T19 | /workspace/coverage/default/14.prim_esc_test.1826659794 | Mar 10 12:17:32 PM PDT 24 | Mar 10 12:17:33 PM PDT 24 | 3977088 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.4020801805 | Mar 10 12:18:03 PM PDT 24 | Mar 10 12:18:03 PM PDT 24 | 4365876 ps | ||
| T12 | /workspace/coverage/default/0.prim_esc_test.1996722276 | Mar 10 12:17:31 PM PDT 24 | Mar 10 12:17:32 PM PDT 24 | 4685729 ps |
| Test location | /workspace/coverage/default/16.prim_esc_test.2718380639 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4832279 ps |
| CPU time | 0.4 seconds |
| Started | Mar 10 12:23:02 PM PDT 24 |
| Finished | Mar 10 12:23:03 PM PDT 24 |
| Peak memory | 146112 kb |
| Host | smart-9f8cc5c9-5776-4f5d-ab77-ecc2a720c775 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2718380639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2718380639 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2437559141 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4369645 ps |
| CPU time | 0.41 seconds |
| Started | Mar 10 12:19:37 PM PDT 24 |
| Finished | Mar 10 12:19:38 PM PDT 24 |
| Peak memory | 146268 kb |
| Host | smart-d6f244b2-232e-4179-9f35-e65c2ac643e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437559141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2437559141 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.32553162 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4593611 ps |
| CPU time | 0.37 seconds |
| Started | Mar 10 12:17:31 PM PDT 24 |
| Finished | Mar 10 12:17:32 PM PDT 24 |
| Peak memory | 145752 kb |
| Host | smart-4891ddf6-09c5-4a89-b8de-4c177a4bae14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32553162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.32553162 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.755956314 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4989884 ps |
| CPU time | 0.39 seconds |
| Started | Mar 10 12:19:07 PM PDT 24 |
| Finished | Mar 10 12:19:08 PM PDT 24 |
| Peak memory | 146196 kb |
| Host | smart-53d172f3-e9d0-4338-a366-f52e3f6ed059 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755956314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.755956314 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1996722276 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4685729 ps |
| CPU time | 0.37 seconds |
| Started | Mar 10 12:17:31 PM PDT 24 |
| Finished | Mar 10 12:17:32 PM PDT 24 |
| Peak memory | 146360 kb |
| Host | smart-d41ee013-3ece-4131-890a-028c88722bd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1996722276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1996722276 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.33393049 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4990598 ps |
| CPU time | 0.38 seconds |
| Started | Mar 10 12:23:03 PM PDT 24 |
| Finished | Mar 10 12:23:04 PM PDT 24 |
| Peak memory | 146116 kb |
| Host | smart-c21a6fe3-90cf-4b55-9d7f-a2ef5213f65f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33393049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.33393049 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3112364565 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4888399 ps |
| CPU time | 0.37 seconds |
| Started | Mar 10 12:22:36 PM PDT 24 |
| Finished | Mar 10 12:22:37 PM PDT 24 |
| Peak memory | 144828 kb |
| Host | smart-cb5613df-b9a5-43dd-bad5-6352304a1997 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3112364565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3112364565 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2011517347 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4866802 ps |
| CPU time | 0.41 seconds |
| Started | Mar 10 12:17:48 PM PDT 24 |
| Finished | Mar 10 12:17:48 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-fc9d8de3-8364-4834-ae67-b53fbfc31fb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011517347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2011517347 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2117682372 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4883914 ps |
| CPU time | 0.41 seconds |
| Started | Mar 10 12:17:24 PM PDT 24 |
| Finished | Mar 10 12:17:24 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-d6fb876d-a99d-4774-a779-2fd33bf603f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117682372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2117682372 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.461671085 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5012129 ps |
| CPU time | 0.38 seconds |
| Started | Mar 10 12:17:31 PM PDT 24 |
| Finished | Mar 10 12:17:32 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-486f5430-80ea-4b59-b5ed-b8b8722eabde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461671085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.461671085 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1826659794 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3977088 ps |
| CPU time | 0.39 seconds |
| Started | Mar 10 12:17:32 PM PDT 24 |
| Finished | Mar 10 12:17:33 PM PDT 24 |
| Peak memory | 145848 kb |
| Host | smart-d70a7d99-5add-4f4a-acdd-5590cf6dc7b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826659794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1826659794 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.4020801805 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4365876 ps |
| CPU time | 0.38 seconds |
| Started | Mar 10 12:18:03 PM PDT 24 |
| Finished | Mar 10 12:18:03 PM PDT 24 |
| Peak memory | 145936 kb |
| Host | smart-46d58d31-195d-4465-b53a-ecb4982bfabb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020801805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.4020801805 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1422507255 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4384737 ps |
| CPU time | 0.39 seconds |
| Started | Mar 10 12:23:58 PM PDT 24 |
| Finished | Mar 10 12:23:59 PM PDT 24 |
| Peak memory | 145952 kb |
| Host | smart-5fc77fd4-a9d0-49b8-bf4c-91af20904478 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422507255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1422507255 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2686015092 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4441010 ps |
| CPU time | 0.38 seconds |
| Started | Mar 10 12:23:03 PM PDT 24 |
| Finished | Mar 10 12:23:04 PM PDT 24 |
| Peak memory | 146124 kb |
| Host | smart-76861df6-0c78-4d37-8447-fb22daf37dce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686015092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2686015092 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3196516181 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5036279 ps |
| CPU time | 0.39 seconds |
| Started | Mar 10 12:19:07 PM PDT 24 |
| Finished | Mar 10 12:19:07 PM PDT 24 |
| Peak memory | 146200 kb |
| Host | smart-0d761abb-6139-4250-9dc6-b1f05ea4e658 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196516181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3196516181 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1482257233 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4791512 ps |
| CPU time | 0.44 seconds |
| Started | Mar 10 12:17:23 PM PDT 24 |
| Finished | Mar 10 12:17:24 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-c9f0f627-4329-4390-9968-dd51cee777af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482257233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1482257233 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2162708715 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5007058 ps |
| CPU time | 0.4 seconds |
| Started | Mar 10 12:19:55 PM PDT 24 |
| Finished | Mar 10 12:19:55 PM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-5064170f-9e57-4c6a-8b1d-ed8fc43f4ed8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162708715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2162708715 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4067735477 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4429604 ps |
| CPU time | 0.39 seconds |
| Started | Mar 10 12:17:32 PM PDT 24 |
| Finished | Mar 10 12:17:33 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-8177fae0-0122-4d5d-8488-15c4a2c2c878 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067735477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4067735477 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3350480602 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4955109 ps |
| CPU time | 0.38 seconds |
| Started | Mar 10 12:17:58 PM PDT 24 |
| Finished | Mar 10 12:17:59 PM PDT 24 |
| Peak memory | 146364 kb |
| Host | smart-76fe9d40-1daa-440a-bfc1-16995aad84a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350480602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3350480602 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.4039340425 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4550789 ps |
| CPU time | 0.42 seconds |
| Started | Mar 10 12:18:57 PM PDT 24 |
| Finished | Mar 10 12:18:58 PM PDT 24 |
| Peak memory | 146224 kb |
| Host | smart-94ee35e5-02c9-4a9e-9b87-97b94c9a1ba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4039340425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.4039340425 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |