Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.17 94.29 86.36 100.00 92.86 86.05 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.40 85.40 90.48 90.48 86.36 86.36 100.00 100.00 75.00 75.00 79.07 79.07 81.48 81.48 /workspace/coverage/default/1.prim_esc_test.2290067615
88.44 3.04 93.33 2.86 86.36 0.00 100.00 0.00 85.71 10.71 83.72 4.65 81.48 0.00 /workspace/coverage/default/19.prim_esc_test.2674793009
89.58 1.14 94.29 0.95 86.36 0.00 100.00 0.00 89.29 3.57 86.05 2.33 81.48 0.00 /workspace/coverage/default/17.prim_esc_test.981726330
90.17 0.60 94.29 0.00 86.36 0.00 100.00 0.00 92.86 3.57 86.05 0.00 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.378975880

Tests that do not contribute to grading

Name
/workspace/coverage/default/10.prim_esc_test.2809076055
/workspace/coverage/default/11.prim_esc_test.2683469050
/workspace/coverage/default/12.prim_esc_test.1657738831
/workspace/coverage/default/13.prim_esc_test.1265058968
/workspace/coverage/default/14.prim_esc_test.2806022475
/workspace/coverage/default/15.prim_esc_test.65216738
/workspace/coverage/default/16.prim_esc_test.1933878545
/workspace/coverage/default/18.prim_esc_test.1955913881
/workspace/coverage/default/2.prim_esc_test.2679286624
/workspace/coverage/default/3.prim_esc_test.1247656231
/workspace/coverage/default/4.prim_esc_test.509588151
/workspace/coverage/default/5.prim_esc_test.73562561
/workspace/coverage/default/6.prim_esc_test.2184852355
/workspace/coverage/default/7.prim_esc_test.1444950950
/workspace/coverage/default/8.prim_esc_test.2700327315
/workspace/coverage/default/9.prim_esc_test.501966496



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/6.prim_esc_test.2184852355 Mar 12 12:29:46 PM PDT 24 Mar 12 12:29:47 PM PDT 24 5137093 ps
T2 /workspace/coverage/default/5.prim_esc_test.73562561 Mar 12 12:30:12 PM PDT 24 Mar 12 12:30:13 PM PDT 24 4963850 ps
T3 /workspace/coverage/default/1.prim_esc_test.2290067615 Mar 12 12:30:21 PM PDT 24 Mar 12 12:30:21 PM PDT 24 5138287 ps
T4 /workspace/coverage/default/3.prim_esc_test.1247656231 Mar 12 12:29:57 PM PDT 24 Mar 12 12:29:58 PM PDT 24 5018679 ps
T5 /workspace/coverage/default/0.prim_esc_test.378975880 Mar 12 12:30:00 PM PDT 24 Mar 12 12:30:01 PM PDT 24 5174536 ps
T6 /workspace/coverage/default/10.prim_esc_test.2809076055 Mar 12 12:29:56 PM PDT 24 Mar 12 12:29:56 PM PDT 24 5051756 ps
T9 /workspace/coverage/default/9.prim_esc_test.501966496 Mar 12 12:29:50 PM PDT 24 Mar 12 12:29:51 PM PDT 24 4258748 ps
T10 /workspace/coverage/default/16.prim_esc_test.1933878545 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:49 PM PDT 24 4479451 ps
T12 /workspace/coverage/default/7.prim_esc_test.1444950950 Mar 12 12:30:03 PM PDT 24 Mar 12 12:30:03 PM PDT 24 4676271 ps
T14 /workspace/coverage/default/11.prim_esc_test.2683469050 Mar 12 12:30:44 PM PDT 24 Mar 12 12:30:44 PM PDT 24 4802055 ps
T13 /workspace/coverage/default/15.prim_esc_test.65216738 Mar 12 12:30:04 PM PDT 24 Mar 12 12:30:05 PM PDT 24 5036164 ps
T16 /workspace/coverage/default/13.prim_esc_test.1265058968 Mar 12 12:29:53 PM PDT 24 Mar 12 12:29:53 PM PDT 24 5059311 ps
T7 /workspace/coverage/default/12.prim_esc_test.1657738831 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:53 PM PDT 24 4791789 ps
T8 /workspace/coverage/default/18.prim_esc_test.1955913881 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:52 PM PDT 24 4505595 ps
T17 /workspace/coverage/default/4.prim_esc_test.509588151 Mar 12 12:29:58 PM PDT 24 Mar 12 12:29:58 PM PDT 24 4206052 ps
T18 /workspace/coverage/default/8.prim_esc_test.2700327315 Mar 12 12:29:56 PM PDT 24 Mar 12 12:29:57 PM PDT 24 5124114 ps
T15 /workspace/coverage/default/19.prim_esc_test.2674793009 Mar 12 12:29:58 PM PDT 24 Mar 12 12:29:59 PM PDT 24 5405414 ps
T19 /workspace/coverage/default/14.prim_esc_test.2806022475 Mar 12 12:29:49 PM PDT 24 Mar 12 12:29:50 PM PDT 24 4953313 ps
T11 /workspace/coverage/default/17.prim_esc_test.981726330 Mar 12 12:29:59 PM PDT 24 Mar 12 12:29:59 PM PDT 24 5537112 ps
T20 /workspace/coverage/default/2.prim_esc_test.2679286624 Mar 12 12:29:59 PM PDT 24 Mar 12 12:30:00 PM PDT 24 4524820 ps

Test location /workspace/coverage/default/1.prim_esc_test.2290067615
Short name T3
Test name
Test status
Simulation time 5138287 ps
CPU time 0.39 seconds
Started Mar 12 12:30:21 PM PDT 24
Finished Mar 12 12:30:21 PM PDT 24
Peak memory 146204 kb
Host smart-74773ce3-11a5-4522-8ec6-72eec0436dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290067615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2290067615
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2674793009
Short name T15
Test name
Test status
Simulation time 5405414 ps
CPU time 0.39 seconds
Started Mar 12 12:29:58 PM PDT 24
Finished Mar 12 12:29:59 PM PDT 24
Peak memory 146276 kb
Host smart-7d1a3ada-93e8-49aa-b96b-df15fe859ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674793009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2674793009
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.981726330
Short name T11
Test name
Test status
Simulation time 5537112 ps
CPU time 0.36 seconds
Started Mar 12 12:29:59 PM PDT 24
Finished Mar 12 12:29:59 PM PDT 24
Peak memory 146292 kb
Host smart-040602bf-0bc2-478d-8f75-4d869346aee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981726330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.981726330
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.378975880
Short name T5
Test name
Test status
Simulation time 5174536 ps
CPU time 0.38 seconds
Started Mar 12 12:30:00 PM PDT 24
Finished Mar 12 12:30:01 PM PDT 24
Peak memory 146284 kb
Host smart-942a649f-653b-41ce-aa04-9211cb9c6960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378975880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.378975880
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.2809076055
Short name T6
Test name
Test status
Simulation time 5051756 ps
CPU time 0.38 seconds
Started Mar 12 12:29:56 PM PDT 24
Finished Mar 12 12:29:56 PM PDT 24
Peak memory 146284 kb
Host smart-8279144c-50f6-4aff-b541-f9b08b32834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809076055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2809076055
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.2683469050
Short name T14
Test name
Test status
Simulation time 4802055 ps
CPU time 0.35 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:30:44 PM PDT 24
Peak memory 146296 kb
Host smart-3df7ba71-60eb-4600-8297-b2873c143c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683469050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2683469050
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.1657738831
Short name T7
Test name
Test status
Simulation time 4791789 ps
CPU time 0.38 seconds
Started Mar 12 12:29:52 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 146360 kb
Host smart-d71620b7-1928-4378-b5d6-95e5649c03f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657738831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1657738831
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.1265058968
Short name T16
Test name
Test status
Simulation time 5059311 ps
CPU time 0.36 seconds
Started Mar 12 12:29:53 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 146292 kb
Host smart-3b583f9d-f381-4f12-9714-e7c6b184c489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265058968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1265058968
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.2806022475
Short name T19
Test name
Test status
Simulation time 4953313 ps
CPU time 0.36 seconds
Started Mar 12 12:29:49 PM PDT 24
Finished Mar 12 12:29:50 PM PDT 24
Peak memory 146292 kb
Host smart-17d277b9-0fae-4000-96d4-7f0a41e1dbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806022475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2806022475
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.65216738
Short name T13
Test name
Test status
Simulation time 5036164 ps
CPU time 0.38 seconds
Started Mar 12 12:30:04 PM PDT 24
Finished Mar 12 12:30:05 PM PDT 24
Peak memory 146312 kb
Host smart-36d3d9de-401a-4061-812f-19b8c87320e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65216738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.65216738
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1933878545
Short name T10
Test name
Test status
Simulation time 4479451 ps
CPU time 0.38 seconds
Started Mar 12 12:29:48 PM PDT 24
Finished Mar 12 12:29:49 PM PDT 24
Peak memory 146312 kb
Host smart-3a232691-2cc0-48fc-8fc5-4605b46be1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933878545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1933878545
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.1955913881
Short name T8
Test name
Test status
Simulation time 4505595 ps
CPU time 0.38 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:52 PM PDT 24
Peak memory 146312 kb
Host smart-fb911211-4ad5-4508-8ad7-65b4a38e1211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955913881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1955913881
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2679286624
Short name T20
Test name
Test status
Simulation time 4524820 ps
CPU time 0.38 seconds
Started Mar 12 12:29:59 PM PDT 24
Finished Mar 12 12:30:00 PM PDT 24
Peak memory 146284 kb
Host smart-641e2615-504d-4df7-a2f3-2dc4e50af9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679286624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2679286624
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.1247656231
Short name T4
Test name
Test status
Simulation time 5018679 ps
CPU time 0.37 seconds
Started Mar 12 12:29:57 PM PDT 24
Finished Mar 12 12:29:58 PM PDT 24
Peak memory 145892 kb
Host smart-452e01e4-7c09-4d02-ab35-6194a40ad4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247656231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1247656231
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.509588151
Short name T17
Test name
Test status
Simulation time 4206052 ps
CPU time 0.39 seconds
Started Mar 12 12:29:58 PM PDT 24
Finished Mar 12 12:29:58 PM PDT 24
Peak memory 146304 kb
Host smart-d08b5e62-26d4-4b87-8e60-006415fcd112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509588151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.509588151
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.73562561
Short name T2
Test name
Test status
Simulation time 4963850 ps
CPU time 0.38 seconds
Started Mar 12 12:30:12 PM PDT 24
Finished Mar 12 12:30:13 PM PDT 24
Peak memory 146188 kb
Host smart-3c8a4e41-ebf3-4a47-94a5-6436bf9cf818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73562561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.73562561
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2184852355
Short name T1
Test name
Test status
Simulation time 5137093 ps
CPU time 0.4 seconds
Started Mar 12 12:29:46 PM PDT 24
Finished Mar 12 12:29:47 PM PDT 24
Peak memory 146312 kb
Host smart-d035ec38-e813-4e54-8db7-c5323da24fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184852355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2184852355
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.1444950950
Short name T12
Test name
Test status
Simulation time 4676271 ps
CPU time 0.36 seconds
Started Mar 12 12:30:03 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 146272 kb
Host smart-65cc7bb5-8cf3-4e08-b7e1-a56328423c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444950950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1444950950
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.2700327315
Short name T18
Test name
Test status
Simulation time 5124114 ps
CPU time 0.43 seconds
Started Mar 12 12:29:56 PM PDT 24
Finished Mar 12 12:29:57 PM PDT 24
Peak memory 146276 kb
Host smart-eb0e4dc1-6ff5-42e7-8ab8-d0a51f0f00f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700327315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2700327315
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.501966496
Short name T9
Test name
Test status
Simulation time 4258748 ps
CPU time 0.39 seconds
Started Mar 12 12:29:50 PM PDT 24
Finished Mar 12 12:29:51 PM PDT 24
Peak memory 146268 kb
Host smart-c1711bfb-734c-4399-bf0f-fc908e9e4554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501966496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.501966496
Directory /workspace/9.prim_esc_test/latest
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