Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.70 86.70 92.38 92.38 86.36 86.36 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/4.prim_esc_test.2760721950
88.44 1.74 93.33 0.95 86.36 0.00 100.00 0.00 85.71 7.14 83.72 2.33 81.48 0.00 /workspace/coverage/default/10.prim_esc_test.1137156837
89.58 1.14 94.29 0.95 86.36 0.00 100.00 0.00 89.29 3.57 86.05 2.33 81.48 0.00 /workspace/coverage/default/18.prim_esc_test.2354771245
90.72 1.14 95.24 0.95 86.36 0.00 100.00 0.00 92.86 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/19.prim_esc_test.3744627962
91.31 0.60 95.24 0.00 86.36 0.00 100.00 0.00 96.43 3.57 88.37 0.00 81.48 0.00 /workspace/coverage/default/3.prim_esc_test.375905556

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.1879516152
/workspace/coverage/default/1.prim_esc_test.3256784204
/workspace/coverage/default/11.prim_esc_test.354848839
/workspace/coverage/default/12.prim_esc_test.1382480138
/workspace/coverage/default/13.prim_esc_test.4070827277
/workspace/coverage/default/14.prim_esc_test.2382330638
/workspace/coverage/default/15.prim_esc_test.2121084487
/workspace/coverage/default/16.prim_esc_test.4047534290
/workspace/coverage/default/17.prim_esc_test.2130638374
/workspace/coverage/default/2.prim_esc_test.2963178099
/workspace/coverage/default/5.prim_esc_test.1327512897
/workspace/coverage/default/6.prim_esc_test.1880318651
/workspace/coverage/default/7.prim_esc_test.520422237
/workspace/coverage/default/8.prim_esc_test.933205988
/workspace/coverage/default/9.prim_esc_test.3836803640



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/14.prim_esc_test.2382330638 Mar 14 12:21:15 PM PDT 24 Mar 14 12:21:15 PM PDT 24 4800439 ps
T2 /workspace/coverage/default/13.prim_esc_test.4070827277 Mar 14 12:18:32 PM PDT 24 Mar 14 12:18:33 PM PDT 24 4641619 ps
T3 /workspace/coverage/default/5.prim_esc_test.1327512897 Mar 14 12:18:23 PM PDT 24 Mar 14 12:18:24 PM PDT 24 5271624 ps
T10 /workspace/coverage/default/18.prim_esc_test.2354771245 Mar 14 12:18:31 PM PDT 24 Mar 14 12:18:31 PM PDT 24 4729569 ps
T5 /workspace/coverage/default/19.prim_esc_test.3744627962 Mar 14 12:18:23 PM PDT 24 Mar 14 12:18:24 PM PDT 24 4449028 ps
T11 /workspace/coverage/default/7.prim_esc_test.520422237 Mar 14 12:18:32 PM PDT 24 Mar 14 12:18:33 PM PDT 24 5091606 ps
T4 /workspace/coverage/default/2.prim_esc_test.2963178099 Mar 14 12:18:24 PM PDT 24 Mar 14 12:18:25 PM PDT 24 5190263 ps
T7 /workspace/coverage/default/4.prim_esc_test.2760721950 Mar 14 12:18:23 PM PDT 24 Mar 14 12:18:24 PM PDT 24 4576380 ps
T12 /workspace/coverage/default/11.prim_esc_test.354848839 Mar 14 12:18:34 PM PDT 24 Mar 14 12:18:34 PM PDT 24 4760053 ps
T6 /workspace/coverage/default/17.prim_esc_test.2130638374 Mar 14 12:18:36 PM PDT 24 Mar 14 12:18:37 PM PDT 24 5295128 ps
T8 /workspace/coverage/default/1.prim_esc_test.3256784204 Mar 14 12:18:24 PM PDT 24 Mar 14 12:18:25 PM PDT 24 5157910 ps
T9 /workspace/coverage/default/12.prim_esc_test.1382480138 Mar 14 12:21:08 PM PDT 24 Mar 14 12:21:09 PM PDT 24 5022105 ps
T14 /workspace/coverage/default/3.prim_esc_test.375905556 Mar 14 12:18:33 PM PDT 24 Mar 14 12:18:34 PM PDT 24 4711929 ps
T13 /workspace/coverage/default/6.prim_esc_test.1880318651 Mar 14 12:18:26 PM PDT 24 Mar 14 12:18:26 PM PDT 24 4829050 ps
T15 /workspace/coverage/default/16.prim_esc_test.4047534290 Mar 14 12:18:23 PM PDT 24 Mar 14 12:18:24 PM PDT 24 4509455 ps
T16 /workspace/coverage/default/9.prim_esc_test.3836803640 Mar 14 12:18:33 PM PDT 24 Mar 14 12:18:33 PM PDT 24 4702494 ps
T17 /workspace/coverage/default/8.prim_esc_test.933205988 Mar 14 12:21:09 PM PDT 24 Mar 14 12:21:09 PM PDT 24 4680599 ps
T18 /workspace/coverage/default/10.prim_esc_test.1137156837 Mar 14 12:18:33 PM PDT 24 Mar 14 12:18:34 PM PDT 24 4811862 ps
T19 /workspace/coverage/default/0.prim_esc_test.1879516152 Mar 14 12:18:23 PM PDT 24 Mar 14 12:18:24 PM PDT 24 4690123 ps
T20 /workspace/coverage/default/15.prim_esc_test.2121084487 Mar 14 12:18:26 PM PDT 24 Mar 14 12:18:26 PM PDT 24 4802466 ps

Test location /workspace/coverage/default/4.prim_esc_test.2760721950
Short name T7
Test name
Test status
Simulation time 4576380 ps
CPU time 0.4 seconds
Started Mar 14 12:18:23 PM PDT 24
Finished Mar 14 12:18:24 PM PDT 24
Peak memory 145688 kb
Host smart-bc167298-b3c8-4db7-b709-39de1bfd564f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760721950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2760721950
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.1137156837
Short name T18
Test name
Test status
Simulation time 4811862 ps
CPU time 0.41 seconds
Started Mar 14 12:18:33 PM PDT 24
Finished Mar 14 12:18:34 PM PDT 24
Peak memory 145520 kb
Host smart-4054e4f5-6c7a-4241-a103-e158b99ab520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137156837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1137156837
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.2354771245
Short name T10
Test name
Test status
Simulation time 4729569 ps
CPU time 0.41 seconds
Started Mar 14 12:18:31 PM PDT 24
Finished Mar 14 12:18:31 PM PDT 24
Peak memory 146092 kb
Host smart-63b2893e-21de-4875-b2ad-39c1b335fb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354771245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2354771245
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.3744627962
Short name T5
Test name
Test status
Simulation time 4449028 ps
CPU time 0.45 seconds
Started Mar 14 12:18:23 PM PDT 24
Finished Mar 14 12:18:24 PM PDT 24
Peak memory 144648 kb
Host smart-f878f371-2781-432d-9089-6f6d49ef4a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744627962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3744627962
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.375905556
Short name T14
Test name
Test status
Simulation time 4711929 ps
CPU time 0.43 seconds
Started Mar 14 12:18:33 PM PDT 24
Finished Mar 14 12:18:34 PM PDT 24
Peak memory 145516 kb
Host smart-80d56b22-c693-4701-a15e-5be61eb56190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375905556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.375905556
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.1879516152
Short name T19
Test name
Test status
Simulation time 4690123 ps
CPU time 0.41 seconds
Started Mar 14 12:18:23 PM PDT 24
Finished Mar 14 12:18:24 PM PDT 24
Peak memory 145604 kb
Host smart-a0c4c376-f11a-4871-b3e5-f7d97071700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879516152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1879516152
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.3256784204
Short name T8
Test name
Test status
Simulation time 5157910 ps
CPU time 0.44 seconds
Started Mar 14 12:18:24 PM PDT 24
Finished Mar 14 12:18:25 PM PDT 24
Peak memory 144396 kb
Host smart-d31d8b0f-b8fd-4890-9165-b7d9a283ee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256784204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3256784204
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.354848839
Short name T12
Test name
Test status
Simulation time 4760053 ps
CPU time 0.42 seconds
Started Mar 14 12:18:34 PM PDT 24
Finished Mar 14 12:18:34 PM PDT 24
Peak memory 146292 kb
Host smart-74aa0942-f1e1-44ee-8938-7ded52471c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354848839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.354848839
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.1382480138
Short name T9
Test name
Test status
Simulation time 5022105 ps
CPU time 0.39 seconds
Started Mar 14 12:21:08 PM PDT 24
Finished Mar 14 12:21:09 PM PDT 24
Peak memory 146348 kb
Host smart-e35aef60-6394-4f07-9a55-e6fbc57dece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382480138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1382480138
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.4070827277
Short name T2
Test name
Test status
Simulation time 4641619 ps
CPU time 0.38 seconds
Started Mar 14 12:18:32 PM PDT 24
Finished Mar 14 12:18:33 PM PDT 24
Peak memory 146028 kb
Host smart-18504eca-7927-45f5-92f5-ca5278c949da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070827277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4070827277
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.2382330638
Short name T1
Test name
Test status
Simulation time 4800439 ps
CPU time 0.43 seconds
Started Mar 14 12:21:15 PM PDT 24
Finished Mar 14 12:21:15 PM PDT 24
Peak memory 146436 kb
Host smart-d908a17f-7321-437d-af56-3b956bb1ff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382330638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2382330638
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.2121084487
Short name T20
Test name
Test status
Simulation time 4802466 ps
CPU time 0.38 seconds
Started Mar 14 12:18:26 PM PDT 24
Finished Mar 14 12:18:26 PM PDT 24
Peak memory 146004 kb
Host smart-1039cb89-6cc2-4877-ab56-8890f186b1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121084487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2121084487
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.4047534290
Short name T15
Test name
Test status
Simulation time 4509455 ps
CPU time 0.38 seconds
Started Mar 14 12:18:23 PM PDT 24
Finished Mar 14 12:18:24 PM PDT 24
Peak memory 145984 kb
Host smart-6f8f2521-1aef-4db7-ba9c-b6afab368ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047534290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.4047534290
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.2130638374
Short name T6
Test name
Test status
Simulation time 5295128 ps
CPU time 0.38 seconds
Started Mar 14 12:18:36 PM PDT 24
Finished Mar 14 12:18:37 PM PDT 24
Peak memory 146636 kb
Host smart-0e6a56c3-2c8e-46ba-aa42-980ef0a310a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130638374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2130638374
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2963178099
Short name T4
Test name
Test status
Simulation time 5190263 ps
CPU time 0.44 seconds
Started Mar 14 12:18:24 PM PDT 24
Finished Mar 14 12:18:25 PM PDT 24
Peak memory 144356 kb
Host smart-b2dfcfe0-59f9-47cf-9001-c150763305c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963178099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2963178099
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.1327512897
Short name T3
Test name
Test status
Simulation time 5271624 ps
CPU time 0.46 seconds
Started Mar 14 12:18:23 PM PDT 24
Finished Mar 14 12:18:24 PM PDT 24
Peak memory 144428 kb
Host smart-10851e3d-0f70-42b8-8b03-b42bd93e206a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327512897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1327512897
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.1880318651
Short name T13
Test name
Test status
Simulation time 4829050 ps
CPU time 0.42 seconds
Started Mar 14 12:18:26 PM PDT 24
Finished Mar 14 12:18:26 PM PDT 24
Peak memory 146004 kb
Host smart-bde736c3-71da-466b-8083-609dd3cdc5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880318651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1880318651
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.520422237
Short name T11
Test name
Test status
Simulation time 5091606 ps
CPU time 0.38 seconds
Started Mar 14 12:18:32 PM PDT 24
Finished Mar 14 12:18:33 PM PDT 24
Peak memory 146044 kb
Host smart-9f42ca25-ac75-4fc3-afb3-41330ace42c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520422237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.520422237
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.933205988
Short name T17
Test name
Test status
Simulation time 4680599 ps
CPU time 0.4 seconds
Started Mar 14 12:21:09 PM PDT 24
Finished Mar 14 12:21:09 PM PDT 24
Peak memory 146340 kb
Host smart-9f7c1105-51e2-462e-a9ec-713dc94109e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933205988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.933205988
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.3836803640
Short name T16
Test name
Test status
Simulation time 4702494 ps
CPU time 0.38 seconds
Started Mar 14 12:18:33 PM PDT 24
Finished Mar 14 12:18:33 PM PDT 24
Peak memory 146236 kb
Host smart-fc891ba6-da10-4f6d-97b4-d2fd279f9985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836803640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3836803640
Directory /workspace/9.prim_esc_test/latest
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