Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.02 85.02 90.48 90.48 84.09 84.09 100.00 100.00 75.00 75.00 79.07 79.07 81.48 81.48 /workspace/coverage/default/12.prim_esc_test.453093505
88.44 3.42 93.33 2.86 86.36 2.27 100.00 0.00 85.71 10.71 83.72 4.65 81.48 0.00 /workspace/coverage/default/8.prim_esc_test.3359971776
90.17 1.74 94.29 0.95 86.36 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/1.prim_esc_test.130359206
91.31 1.14 95.24 0.95 86.36 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/13.prim_esc_test.3351954558

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.997554237
/workspace/coverage/default/10.prim_esc_test.460366473
/workspace/coverage/default/11.prim_esc_test.1629425294
/workspace/coverage/default/14.prim_esc_test.4014086962
/workspace/coverage/default/15.prim_esc_test.3646504837
/workspace/coverage/default/16.prim_esc_test.2754114126
/workspace/coverage/default/17.prim_esc_test.1858768366
/workspace/coverage/default/18.prim_esc_test.3950222220
/workspace/coverage/default/19.prim_esc_test.2116874092
/workspace/coverage/default/2.prim_esc_test.4067015051
/workspace/coverage/default/3.prim_esc_test.2510110782
/workspace/coverage/default/4.prim_esc_test.3488937951
/workspace/coverage/default/5.prim_esc_test.1881546194
/workspace/coverage/default/6.prim_esc_test.879966113
/workspace/coverage/default/7.prim_esc_test.3987077939
/workspace/coverage/default/9.prim_esc_test.2076388536



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.prim_esc_test.2510110782 Mar 17 12:21:17 PM PDT 24 Mar 17 12:21:17 PM PDT 24 5339993 ps
T2 /workspace/coverage/default/11.prim_esc_test.1629425294 Mar 17 12:21:21 PM PDT 24 Mar 17 12:21:22 PM PDT 24 5428208 ps
T3 /workspace/coverage/default/12.prim_esc_test.453093505 Mar 17 12:21:18 PM PDT 24 Mar 17 12:21:19 PM PDT 24 4942981 ps
T4 /workspace/coverage/default/18.prim_esc_test.3950222220 Mar 17 12:21:21 PM PDT 24 Mar 17 12:21:22 PM PDT 24 4548505 ps
T5 /workspace/coverage/default/10.prim_esc_test.460366473 Mar 17 12:21:26 PM PDT 24 Mar 17 12:21:27 PM PDT 24 4572480 ps
T9 /workspace/coverage/default/7.prim_esc_test.3987077939 Mar 17 12:21:20 PM PDT 24 Mar 17 12:21:21 PM PDT 24 4835760 ps
T10 /workspace/coverage/default/1.prim_esc_test.130359206 Mar 17 12:21:17 PM PDT 24 Mar 17 12:21:18 PM PDT 24 4656934 ps
T12 /workspace/coverage/default/6.prim_esc_test.879966113 Mar 17 12:21:21 PM PDT 24 Mar 17 12:21:22 PM PDT 24 4114850 ps
T13 /workspace/coverage/default/5.prim_esc_test.1881546194 Mar 17 12:21:26 PM PDT 24 Mar 17 12:21:27 PM PDT 24 4282886 ps
T14 /workspace/coverage/default/4.prim_esc_test.3488937951 Mar 17 12:21:21 PM PDT 24 Mar 17 12:21:21 PM PDT 24 4769476 ps
T16 /workspace/coverage/default/14.prim_esc_test.4014086962 Mar 17 12:21:21 PM PDT 24 Mar 17 12:21:22 PM PDT 24 4641838 ps
T17 /workspace/coverage/default/2.prim_esc_test.4067015051 Mar 17 12:21:18 PM PDT 24 Mar 17 12:21:19 PM PDT 24 4991724 ps
T11 /workspace/coverage/default/19.prim_esc_test.2116874092 Mar 17 12:21:21 PM PDT 24 Mar 17 12:21:22 PM PDT 24 5223985 ps
T18 /workspace/coverage/default/15.prim_esc_test.3646504837 Mar 17 12:21:26 PM PDT 24 Mar 17 12:21:27 PM PDT 24 4976558 ps
T19 /workspace/coverage/default/0.prim_esc_test.997554237 Mar 17 12:21:17 PM PDT 24 Mar 17 12:21:18 PM PDT 24 4967195 ps
T8 /workspace/coverage/default/8.prim_esc_test.3359971776 Mar 17 12:21:17 PM PDT 24 Mar 17 12:21:18 PM PDT 24 5357265 ps
T20 /workspace/coverage/default/16.prim_esc_test.2754114126 Mar 17 12:21:18 PM PDT 24 Mar 17 12:21:18 PM PDT 24 4427058 ps
T6 /workspace/coverage/default/9.prim_esc_test.2076388536 Mar 17 12:21:19 PM PDT 24 Mar 17 12:21:19 PM PDT 24 4257050 ps
T15 /workspace/coverage/default/17.prim_esc_test.1858768366 Mar 17 12:21:26 PM PDT 24 Mar 17 12:21:27 PM PDT 24 4691975 ps
T7 /workspace/coverage/default/13.prim_esc_test.3351954558 Mar 17 12:21:22 PM PDT 24 Mar 17 12:21:23 PM PDT 24 4707321 ps

Test location /workspace/coverage/default/12.prim_esc_test.453093505
Short name T3
Test name
Test status
Simulation time 4942981 ps
CPU time 0.47 seconds
Started Mar 17 12:21:18 PM PDT 24
Finished Mar 17 12:21:19 PM PDT 24
Peak memory 145980 kb
Host smart-0c4e5f13-9c95-4a6f-afcb-0bb27a7c1e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453093505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.453093505
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.3359971776
Short name T8
Test name
Test status
Simulation time 5357265 ps
CPU time 0.38 seconds
Started Mar 17 12:21:17 PM PDT 24
Finished Mar 17 12:21:18 PM PDT 24
Peak memory 145616 kb
Host smart-1b2ac9a7-485d-4e0a-9076-3f1ad364043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359971776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3359971776
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.130359206
Short name T10
Test name
Test status
Simulation time 4656934 ps
CPU time 0.37 seconds
Started Mar 17 12:21:17 PM PDT 24
Finished Mar 17 12:21:18 PM PDT 24
Peak memory 145900 kb
Host smart-ee7f8350-7ab5-40a0-a5b1-490d5f934fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130359206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.130359206
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.3351954558
Short name T7
Test name
Test status
Simulation time 4707321 ps
CPU time 0.38 seconds
Started Mar 17 12:21:22 PM PDT 24
Finished Mar 17 12:21:23 PM PDT 24
Peak memory 145896 kb
Host smart-89cef8d8-1982-4e8d-871f-538a69b2e516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351954558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3351954558
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.997554237
Short name T19
Test name
Test status
Simulation time 4967195 ps
CPU time 0.41 seconds
Started Mar 17 12:21:17 PM PDT 24
Finished Mar 17 12:21:18 PM PDT 24
Peak memory 145768 kb
Host smart-f1547942-a70f-4c18-b155-f57354296314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997554237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.997554237
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.460366473
Short name T5
Test name
Test status
Simulation time 4572480 ps
CPU time 0.42 seconds
Started Mar 17 12:21:26 PM PDT 24
Finished Mar 17 12:21:27 PM PDT 24
Peak memory 145632 kb
Host smart-94ed29af-5a36-4aa9-a5bd-c1d86d2f9c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460366473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.460366473
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1629425294
Short name T2
Test name
Test status
Simulation time 5428208 ps
CPU time 0.36 seconds
Started Mar 17 12:21:21 PM PDT 24
Finished Mar 17 12:21:22 PM PDT 24
Peak memory 145792 kb
Host smart-1abcd71e-890b-4f61-9d23-959888fec6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629425294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1629425294
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.4014086962
Short name T16
Test name
Test status
Simulation time 4641838 ps
CPU time 0.39 seconds
Started Mar 17 12:21:21 PM PDT 24
Finished Mar 17 12:21:22 PM PDT 24
Peak memory 146420 kb
Host smart-e75fdb66-bf48-4826-bc39-7ea4f856658f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014086962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.4014086962
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.3646504837
Short name T18
Test name
Test status
Simulation time 4976558 ps
CPU time 0.37 seconds
Started Mar 17 12:21:26 PM PDT 24
Finished Mar 17 12:21:27 PM PDT 24
Peak memory 146084 kb
Host smart-2a510d51-8340-4ca0-a5af-c86307bed9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646504837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3646504837
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.2754114126
Short name T20
Test name
Test status
Simulation time 4427058 ps
CPU time 0.37 seconds
Started Mar 17 12:21:18 PM PDT 24
Finished Mar 17 12:21:18 PM PDT 24
Peak memory 145900 kb
Host smart-9b2ca9a8-bf19-41a0-9333-19531c857b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754114126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2754114126
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1858768366
Short name T15
Test name
Test status
Simulation time 4691975 ps
CPU time 0.38 seconds
Started Mar 17 12:21:26 PM PDT 24
Finished Mar 17 12:21:27 PM PDT 24
Peak memory 146080 kb
Host smart-791753a2-d4b9-48d6-a6fc-fb052bf7b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858768366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1858768366
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.3950222220
Short name T4
Test name
Test status
Simulation time 4548505 ps
CPU time 0.39 seconds
Started Mar 17 12:21:21 PM PDT 24
Finished Mar 17 12:21:22 PM PDT 24
Peak memory 146420 kb
Host smart-c6c4fa20-d10f-4ae3-98ae-8d8422855c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950222220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3950222220
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2116874092
Short name T11
Test name
Test status
Simulation time 5223985 ps
CPU time 0.39 seconds
Started Mar 17 12:21:21 PM PDT 24
Finished Mar 17 12:21:22 PM PDT 24
Peak memory 146420 kb
Host smart-6bf5080f-6dce-4837-9bef-1bdeceac01af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116874092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2116874092
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.4067015051
Short name T17
Test name
Test status
Simulation time 4991724 ps
CPU time 0.41 seconds
Started Mar 17 12:21:18 PM PDT 24
Finished Mar 17 12:21:19 PM PDT 24
Peak memory 146088 kb
Host smart-c3f24e28-5ad3-4dcb-a9b3-e5acca3eb815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067015051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.4067015051
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.2510110782
Short name T1
Test name
Test status
Simulation time 5339993 ps
CPU time 0.4 seconds
Started Mar 17 12:21:17 PM PDT 24
Finished Mar 17 12:21:17 PM PDT 24
Peak memory 145520 kb
Host smart-6afe8723-2b78-4b2f-9ba4-f7a1b019bdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510110782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2510110782
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.3488937951
Short name T14
Test name
Test status
Simulation time 4769476 ps
CPU time 0.4 seconds
Started Mar 17 12:21:21 PM PDT 24
Finished Mar 17 12:21:21 PM PDT 24
Peak memory 145884 kb
Host smart-3ba63577-cba2-45ea-84c2-5a161300229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488937951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3488937951
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.1881546194
Short name T13
Test name
Test status
Simulation time 4282886 ps
CPU time 0.41 seconds
Started Mar 17 12:21:26 PM PDT 24
Finished Mar 17 12:21:27 PM PDT 24
Peak memory 145568 kb
Host smart-a2f80516-f3d9-445a-9087-9fd6097ffdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881546194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1881546194
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.879966113
Short name T12
Test name
Test status
Simulation time 4114850 ps
CPU time 0.44 seconds
Started Mar 17 12:21:21 PM PDT 24
Finished Mar 17 12:21:22 PM PDT 24
Peak memory 145908 kb
Host smart-7b64a5c5-467a-4f4b-bf74-1dc8d05968f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879966113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.879966113
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.3987077939
Short name T9
Test name
Test status
Simulation time 4835760 ps
CPU time 0.38 seconds
Started Mar 17 12:21:20 PM PDT 24
Finished Mar 17 12:21:21 PM PDT 24
Peak memory 146420 kb
Host smart-838499cb-8d3a-4b15-a358-a5ea998b1a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987077939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3987077939
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.2076388536
Short name T6
Test name
Test status
Simulation time 4257050 ps
CPU time 0.38 seconds
Started Mar 17 12:21:19 PM PDT 24
Finished Mar 17 12:21:19 PM PDT 24
Peak memory 146084 kb
Host smart-0d97c8f9-7018-4608-9f42-b8edee361209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076388536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2076388536
Directory /workspace/9.prim_esc_test/latest
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