| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.10 | 86.10 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/1.prim_esc_test.2373493257 |
| 87.84 | 1.74 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1649873178 |
| 88.98 | 1.14 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.2229729299 |
| 90.12 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.372680237 |
| 90.72 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.3212719683 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.222874940 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3980802309 |
| /workspace/coverage/default/14.prim_esc_test.3100443857 |
| /workspace/coverage/default/15.prim_esc_test.1661599594 |
| /workspace/coverage/default/16.prim_esc_test.1577876820 |
| /workspace/coverage/default/18.prim_esc_test.1805677543 |
| /workspace/coverage/default/19.prim_esc_test.996605349 |
| /workspace/coverage/default/2.prim_esc_test.2385227222 |
| /workspace/coverage/default/3.prim_esc_test.2594048928 |
| /workspace/coverage/default/4.prim_esc_test.1360245527 |
| /workspace/coverage/default/5.prim_esc_test.1528155182 |
| /workspace/coverage/default/6.prim_esc_test.1727456588 |
| /workspace/coverage/default/7.prim_esc_test.1929046931 |
| /workspace/coverage/default/8.prim_esc_test.3980606086 |
| /workspace/coverage/default/9.prim_esc_test.1972995862 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_esc_test.1649873178 | Mar 19 12:26:12 PM PDT 24 | Mar 19 12:26:13 PM PDT 24 | 5155092 ps | ||
| T2 | /workspace/coverage/default/0.prim_esc_test.3980802309 | Mar 19 12:26:08 PM PDT 24 | Mar 19 12:26:09 PM PDT 24 | 5108258 ps | ||
| T3 | /workspace/coverage/default/13.prim_esc_test.3212719683 | Mar 19 12:26:23 PM PDT 24 | Mar 19 12:26:24 PM PDT 24 | 4670865 ps | ||
| T7 | /workspace/coverage/default/7.prim_esc_test.1929046931 | Mar 19 12:26:23 PM PDT 24 | Mar 19 12:26:24 PM PDT 24 | 4750097 ps | ||
| T4 | /workspace/coverage/default/1.prim_esc_test.2373493257 | Mar 19 12:26:51 PM PDT 24 | Mar 19 12:26:52 PM PDT 24 | 4430272 ps | ||
| T8 | /workspace/coverage/default/19.prim_esc_test.996605349 | Mar 19 12:26:32 PM PDT 24 | Mar 19 12:26:34 PM PDT 24 | 5508621 ps | ||
| T5 | /workspace/coverage/default/8.prim_esc_test.3980606086 | Mar 19 12:26:36 PM PDT 24 | Mar 19 12:26:37 PM PDT 24 | 5107543 ps | ||
| T6 | /workspace/coverage/default/15.prim_esc_test.1661599594 | Mar 19 12:26:21 PM PDT 24 | Mar 19 12:26:22 PM PDT 24 | 5148214 ps | ||
| T9 | /workspace/coverage/default/14.prim_esc_test.3100443857 | Mar 19 12:26:28 PM PDT 24 | Mar 19 12:26:29 PM PDT 24 | 4654703 ps | ||
| T17 | /workspace/coverage/default/16.prim_esc_test.1577876820 | Mar 19 12:26:11 PM PDT 24 | Mar 19 12:26:11 PM PDT 24 | 4775085 ps | ||
| T14 | /workspace/coverage/default/2.prim_esc_test.2385227222 | Mar 19 12:26:13 PM PDT 24 | Mar 19 12:26:14 PM PDT 24 | 5412701 ps | ||
| T18 | /workspace/coverage/default/3.prim_esc_test.2594048928 | Mar 19 12:26:22 PM PDT 24 | Mar 19 12:26:23 PM PDT 24 | 5226082 ps | ||
| T12 | /workspace/coverage/default/5.prim_esc_test.1528155182 | Mar 19 12:26:31 PM PDT 24 | Mar 19 12:26:32 PM PDT 24 | 5016939 ps | ||
| T10 | /workspace/coverage/default/6.prim_esc_test.1727456588 | Mar 19 12:26:10 PM PDT 24 | Mar 19 12:26:11 PM PDT 24 | 5251965 ps | ||
| T15 | /workspace/coverage/default/11.prim_esc_test.2229729299 | Mar 19 12:26:26 PM PDT 24 | Mar 19 12:26:26 PM PDT 24 | 4783198 ps | ||
| T19 | /workspace/coverage/default/4.prim_esc_test.1360245527 | Mar 19 12:26:25 PM PDT 24 | Mar 19 12:26:26 PM PDT 24 | 4877132 ps | ||
| T13 | /workspace/coverage/default/17.prim_esc_test.222874940 | Mar 19 12:26:26 PM PDT 24 | Mar 19 12:26:26 PM PDT 24 | 4688676 ps | ||
| T11 | /workspace/coverage/default/12.prim_esc_test.372680237 | Mar 19 12:26:11 PM PDT 24 | Mar 19 12:26:12 PM PDT 24 | 4972949 ps | ||
| T20 | /workspace/coverage/default/18.prim_esc_test.1805677543 | Mar 19 12:26:22 PM PDT 24 | Mar 19 12:26:23 PM PDT 24 | 5329425 ps | ||
| T16 | /workspace/coverage/default/9.prim_esc_test.1972995862 | Mar 19 12:26:12 PM PDT 24 | Mar 19 12:26:13 PM PDT 24 | 4556593 ps |
| Test location | /workspace/coverage/default/1.prim_esc_test.2373493257 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4430272 ps |
| CPU time | 0.37 seconds |
| Started | Mar 19 12:26:51 PM PDT 24 |
| Finished | Mar 19 12:26:52 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-687b8a15-1818-48c6-83fc-895143ba3ecb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373493257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2373493257 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1649873178 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5155092 ps |
| CPU time | 0.41 seconds |
| Started | Mar 19 12:26:12 PM PDT 24 |
| Finished | Mar 19 12:26:13 PM PDT 24 |
| Peak memory | 145968 kb |
| Host | smart-bcd641db-7fc9-4fcd-9ae5-3e3cbd7ce521 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649873178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1649873178 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2229729299 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4783198 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:26:26 PM PDT 24 |
| Finished | Mar 19 12:26:26 PM PDT 24 |
| Peak memory | 146052 kb |
| Host | smart-ed060fd7-cf4c-4550-a660-d3a2ce837488 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2229729299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2229729299 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.372680237 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4972949 ps |
| CPU time | 0.44 seconds |
| Started | Mar 19 12:26:11 PM PDT 24 |
| Finished | Mar 19 12:26:12 PM PDT 24 |
| Peak memory | 145980 kb |
| Host | smart-61761ade-1a54-475c-acec-0a8765a970a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372680237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.372680237 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3212719683 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4670865 ps |
| CPU time | 0.36 seconds |
| Started | Mar 19 12:26:23 PM PDT 24 |
| Finished | Mar 19 12:26:24 PM PDT 24 |
| Peak memory | 146020 kb |
| Host | smart-b7f121f6-7274-49da-bdd2-9b73bb75f8b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212719683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3212719683 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.222874940 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4688676 ps |
| CPU time | 0.36 seconds |
| Started | Mar 19 12:26:26 PM PDT 24 |
| Finished | Mar 19 12:26:26 PM PDT 24 |
| Peak memory | 146048 kb |
| Host | smart-02cb77d1-ae1f-4483-9460-94d1203adedf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=222874940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.222874940 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3980802309 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5108258 ps |
| CPU time | 0.37 seconds |
| Started | Mar 19 12:26:08 PM PDT 24 |
| Finished | Mar 19 12:26:09 PM PDT 24 |
| Peak memory | 146000 kb |
| Host | smart-2dda14c1-30b6-48c8-ae8f-d0f87cb0de4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980802309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3980802309 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3100443857 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4654703 ps |
| CPU time | 0.37 seconds |
| Started | Mar 19 12:26:28 PM PDT 24 |
| Finished | Mar 19 12:26:29 PM PDT 24 |
| Peak memory | 146176 kb |
| Host | smart-b0a1d8bd-27c1-4888-bf33-c6065b182b9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3100443857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3100443857 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1661599594 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5148214 ps |
| CPU time | 0.45 seconds |
| Started | Mar 19 12:26:21 PM PDT 24 |
| Finished | Mar 19 12:26:22 PM PDT 24 |
| Peak memory | 145888 kb |
| Host | smart-6ad82747-c4ee-41d4-8c31-b89ad2441fba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661599594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1661599594 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1577876820 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4775085 ps |
| CPU time | 0.42 seconds |
| Started | Mar 19 12:26:11 PM PDT 24 |
| Finished | Mar 19 12:26:11 PM PDT 24 |
| Peak memory | 145964 kb |
| Host | smart-01742323-782f-4c66-a8e8-5d8c81256a5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577876820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1577876820 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1805677543 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5329425 ps |
| CPU time | 0.52 seconds |
| Started | Mar 19 12:26:22 PM PDT 24 |
| Finished | Mar 19 12:26:23 PM PDT 24 |
| Peak memory | 145968 kb |
| Host | smart-500a64c9-d676-4b9c-a0bc-c392ee9ed2b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805677543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1805677543 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.996605349 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5508621 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:26:32 PM PDT 24 |
| Finished | Mar 19 12:26:34 PM PDT 24 |
| Peak memory | 146088 kb |
| Host | smart-f4084648-443e-459c-bda8-4647c6b215ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996605349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.996605349 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2385227222 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5412701 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:26:13 PM PDT 24 |
| Finished | Mar 19 12:26:14 PM PDT 24 |
| Peak memory | 145952 kb |
| Host | smart-050d3199-5e30-4c20-b905-d14d31cf0ec8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385227222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2385227222 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2594048928 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5226082 ps |
| CPU time | 0.37 seconds |
| Started | Mar 19 12:26:22 PM PDT 24 |
| Finished | Mar 19 12:26:23 PM PDT 24 |
| Peak memory | 146056 kb |
| Host | smart-df0cb7f6-235f-412d-b384-92939e7773ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594048928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2594048928 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1360245527 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4877132 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:26:25 PM PDT 24 |
| Finished | Mar 19 12:26:26 PM PDT 24 |
| Peak memory | 145976 kb |
| Host | smart-fa468c11-4772-416c-855b-023b4cfb95d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1360245527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1360245527 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1528155182 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5016939 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:26:31 PM PDT 24 |
| Finished | Mar 19 12:26:32 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-129b06ee-6faa-462c-9676-a06550435eed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528155182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1528155182 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1727456588 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5251965 ps |
| CPU time | 0.43 seconds |
| Started | Mar 19 12:26:10 PM PDT 24 |
| Finished | Mar 19 12:26:11 PM PDT 24 |
| Peak memory | 145952 kb |
| Host | smart-d7b3602d-ed16-4724-a4c3-0b7b6d3994b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727456588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1727456588 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1929046931 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4750097 ps |
| CPU time | 0.41 seconds |
| Started | Mar 19 12:26:23 PM PDT 24 |
| Finished | Mar 19 12:26:24 PM PDT 24 |
| Peak memory | 145952 kb |
| Host | smart-f1b9ed9f-b2e3-42b7-8d5e-820c7e076be6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1929046931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1929046931 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3980606086 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5107543 ps |
| CPU time | 0.37 seconds |
| Started | Mar 19 12:26:36 PM PDT 24 |
| Finished | Mar 19 12:26:37 PM PDT 24 |
| Peak memory | 146272 kb |
| Host | smart-7110e4a3-6362-45df-9265-433657521704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980606086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3980606086 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1972995862 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4556593 ps |
| CPU time | 0.38 seconds |
| Started | Mar 19 12:26:12 PM PDT 24 |
| Finished | Mar 19 12:26:13 PM PDT 24 |
| Peak memory | 146036 kb |
| Host | smart-3850d8fe-75cd-46ad-8a74-39b388949c2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972995862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1972995862 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |