Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.31 95.24 86.36 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.32 86.32 92.38 92.38 84.09 84.09 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/12.prim_esc_test.1802175372
88.44 2.12 93.33 0.95 86.36 2.27 100.00 0.00 85.71 7.14 83.72 2.33 81.48 0.00 /workspace/coverage/default/13.prim_esc_test.4227996223
89.58 1.14 94.29 0.95 86.36 0.00 100.00 0.00 89.29 3.57 86.05 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.3659939442
90.72 1.14 95.24 0.95 86.36 0.00 100.00 0.00 92.86 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/19.prim_esc_test.3424465323
91.31 0.60 95.24 0.00 86.36 0.00 100.00 0.00 96.43 3.57 88.37 0.00 81.48 0.00 /workspace/coverage/default/10.prim_esc_test.3295839180

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.1466594290
/workspace/coverage/default/11.prim_esc_test.166085194
/workspace/coverage/default/14.prim_esc_test.2816343804
/workspace/coverage/default/15.prim_esc_test.2049711745
/workspace/coverage/default/16.prim_esc_test.545720625
/workspace/coverage/default/17.prim_esc_test.2819556627
/workspace/coverage/default/18.prim_esc_test.1187227525
/workspace/coverage/default/2.prim_esc_test.2731391746
/workspace/coverage/default/3.prim_esc_test.3544576518
/workspace/coverage/default/4.prim_esc_test.3404889471
/workspace/coverage/default/5.prim_esc_test.3985140242
/workspace/coverage/default/6.prim_esc_test.2712169367
/workspace/coverage/default/7.prim_esc_test.635976272
/workspace/coverage/default/8.prim_esc_test.2008748824
/workspace/coverage/default/9.prim_esc_test.3139887120



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/1.prim_esc_test.1466594290 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:02 PM PDT 24 4878645 ps
T2 /workspace/coverage/default/11.prim_esc_test.166085194 Mar 21 12:24:02 PM PDT 24 Mar 21 12:24:03 PM PDT 24 4989197 ps
T3 /workspace/coverage/default/14.prim_esc_test.2816343804 Mar 21 12:23:55 PM PDT 24 Mar 21 12:23:56 PM PDT 24 4771891 ps
T7 /workspace/coverage/default/8.prim_esc_test.2008748824 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:00 PM PDT 24 5165727 ps
T8 /workspace/coverage/default/19.prim_esc_test.3424465323 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:02 PM PDT 24 4733768 ps
T17 /workspace/coverage/default/4.prim_esc_test.3404889471 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:01 PM PDT 24 4290380 ps
T14 /workspace/coverage/default/2.prim_esc_test.2731391746 Mar 21 12:23:58 PM PDT 24 Mar 21 12:23:59 PM PDT 24 4875640 ps
T9 /workspace/coverage/default/12.prim_esc_test.1802175372 Mar 21 12:23:52 PM PDT 24 Mar 21 12:23:53 PM PDT 24 4836881 ps
T4 /workspace/coverage/default/6.prim_esc_test.2712169367 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:01 PM PDT 24 4546055 ps
T12 /workspace/coverage/default/3.prim_esc_test.3544576518 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:01 PM PDT 24 4851492 ps
T5 /workspace/coverage/default/7.prim_esc_test.635976272 Mar 21 12:23:58 PM PDT 24 Mar 21 12:23:59 PM PDT 24 5128570 ps
T6 /workspace/coverage/default/13.prim_esc_test.4227996223 Mar 21 12:24:10 PM PDT 24 Mar 21 12:24:10 PM PDT 24 4919027 ps
T10 /workspace/coverage/default/5.prim_esc_test.3985140242 Mar 21 12:24:02 PM PDT 24 Mar 21 12:24:03 PM PDT 24 4586052 ps
T18 /workspace/coverage/default/10.prim_esc_test.3295839180 Mar 21 12:23:56 PM PDT 24 Mar 21 12:23:57 PM PDT 24 4783519 ps
T11 /workspace/coverage/default/15.prim_esc_test.2049711745 Mar 21 12:24:03 PM PDT 24 Mar 21 12:24:03 PM PDT 24 4794322 ps
T15 /workspace/coverage/default/17.prim_esc_test.2819556627 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:01 PM PDT 24 4325714 ps
T19 /workspace/coverage/default/18.prim_esc_test.1187227525 Mar 21 12:24:04 PM PDT 24 Mar 21 12:24:05 PM PDT 24 4593923 ps
T20 /workspace/coverage/default/9.prim_esc_test.3139887120 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:01 PM PDT 24 4756938 ps
T13 /workspace/coverage/default/16.prim_esc_test.545720625 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:02 PM PDT 24 4793398 ps
T16 /workspace/coverage/default/0.prim_esc_test.3659939442 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:02 PM PDT 24 4497494 ps

Test location /workspace/coverage/default/12.prim_esc_test.1802175372
Short name T9
Test name
Test status
Simulation time 4836881 ps
CPU time 0.38 seconds
Started Mar 21 12:23:52 PM PDT 24
Finished Mar 21 12:23:53 PM PDT 24
Peak memory 146072 kb
Host smart-45364fe5-6fe2-4c5e-9c5b-8f3943a42a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802175372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1802175372
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.4227996223
Short name T6
Test name
Test status
Simulation time 4919027 ps
CPU time 0.37 seconds
Started Mar 21 12:24:10 PM PDT 24
Finished Mar 21 12:24:10 PM PDT 24
Peak memory 146200 kb
Host smart-b81013cd-851b-45fd-a52a-413bd1bd7036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227996223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4227996223
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.3659939442
Short name T16
Test name
Test status
Simulation time 4497494 ps
CPU time 0.39 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:02 PM PDT 24
Peak memory 146060 kb
Host smart-7539ed40-6ed2-4d0a-80fa-196e9509bcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659939442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3659939442
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.3424465323
Short name T8
Test name
Test status
Simulation time 4733768 ps
CPU time 0.41 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:02 PM PDT 24
Peak memory 146244 kb
Host smart-c153458e-e7e4-43fa-bc4c-10cce1508adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424465323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3424465323
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.3295839180
Short name T18
Test name
Test status
Simulation time 4783519 ps
CPU time 0.39 seconds
Started Mar 21 12:23:56 PM PDT 24
Finished Mar 21 12:23:57 PM PDT 24
Peak memory 146104 kb
Host smart-51870c84-bdd8-4317-be36-4ab6195db361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295839180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3295839180
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.1466594290
Short name T1
Test name
Test status
Simulation time 4878645 ps
CPU time 0.37 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:02 PM PDT 24
Peak memory 146068 kb
Host smart-fc301f8b-48de-47e3-bd66-029841243533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466594290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1466594290
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.166085194
Short name T2
Test name
Test status
Simulation time 4989197 ps
CPU time 0.4 seconds
Started Mar 21 12:24:02 PM PDT 24
Finished Mar 21 12:24:03 PM PDT 24
Peak memory 146012 kb
Host smart-ef1bf35c-ffe0-4762-a4a1-7a1327408b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166085194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.166085194
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.2816343804
Short name T3
Test name
Test status
Simulation time 4771891 ps
CPU time 0.39 seconds
Started Mar 21 12:23:55 PM PDT 24
Finished Mar 21 12:23:56 PM PDT 24
Peak memory 146544 kb
Host smart-53fb8d0e-4541-4f21-acf1-e8b02019db1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816343804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2816343804
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.2049711745
Short name T11
Test name
Test status
Simulation time 4794322 ps
CPU time 0.38 seconds
Started Mar 21 12:24:03 PM PDT 24
Finished Mar 21 12:24:03 PM PDT 24
Peak memory 146100 kb
Host smart-69a66000-1ba1-4b8e-8d0d-14271fe53dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049711745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2049711745
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.545720625
Short name T13
Test name
Test status
Simulation time 4793398 ps
CPU time 0.42 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:02 PM PDT 24
Peak memory 146280 kb
Host smart-f4946986-afa0-43e2-996a-8ef5e9fb7eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545720625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.545720625
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.2819556627
Short name T15
Test name
Test status
Simulation time 4325714 ps
CPU time 0.42 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:01 PM PDT 24
Peak memory 145044 kb
Host smart-80f4a1fd-d0ca-4ead-a19e-0567e62743c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819556627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2819556627
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.1187227525
Short name T19
Test name
Test status
Simulation time 4593923 ps
CPU time 0.38 seconds
Started Mar 21 12:24:04 PM PDT 24
Finished Mar 21 12:24:05 PM PDT 24
Peak memory 146036 kb
Host smart-1d84147e-8563-490f-805b-98c630572ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187227525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1187227525
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2731391746
Short name T14
Test name
Test status
Simulation time 4875640 ps
CPU time 0.43 seconds
Started Mar 21 12:23:58 PM PDT 24
Finished Mar 21 12:23:59 PM PDT 24
Peak memory 145964 kb
Host smart-6ba2632b-935e-4807-8028-38bde2dff7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731391746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2731391746
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.3544576518
Short name T12
Test name
Test status
Simulation time 4851492 ps
CPU time 0.39 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:01 PM PDT 24
Peak memory 146056 kb
Host smart-c1812133-5a4a-416f-8dd8-390272eeb797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544576518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3544576518
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.3404889471
Short name T17
Test name
Test status
Simulation time 4290380 ps
CPU time 0.38 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:01 PM PDT 24
Peak memory 146372 kb
Host smart-2e953fee-57d4-49ff-a571-334ff12f00e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404889471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3404889471
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.3985140242
Short name T10
Test name
Test status
Simulation time 4586052 ps
CPU time 0.38 seconds
Started Mar 21 12:24:02 PM PDT 24
Finished Mar 21 12:24:03 PM PDT 24
Peak memory 146068 kb
Host smart-030ade2c-40b9-4c90-89de-bb856856425c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985140242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3985140242
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2712169367
Short name T4
Test name
Test status
Simulation time 4546055 ps
CPU time 0.38 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:01 PM PDT 24
Peak memory 146060 kb
Host smart-f6c0b9a7-edd5-4f08-ba2d-1ac3ae36097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712169367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2712169367
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.635976272
Short name T5
Test name
Test status
Simulation time 5128570 ps
CPU time 0.42 seconds
Started Mar 21 12:23:58 PM PDT 24
Finished Mar 21 12:23:59 PM PDT 24
Peak memory 145980 kb
Host smart-6f54e413-8f95-40c8-be4f-cfc659a20677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635976272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.635976272
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.2008748824
Short name T7
Test name
Test status
Simulation time 5165727 ps
CPU time 0.37 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:00 PM PDT 24
Peak memory 146060 kb
Host smart-55104c84-5645-4742-b95e-8aff931113a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008748824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2008748824
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.3139887120
Short name T20
Test name
Test status
Simulation time 4756938 ps
CPU time 0.37 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:01 PM PDT 24
Peak memory 146068 kb
Host smart-a1aa8f0d-24e3-4dc2-b367-2df73a298402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139887120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3139887120
Directory /workspace/9.prim_esc_test/latest
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